CN111540817A - Micro light-emitting diode chip - Google Patents

Micro light-emitting diode chip Download PDF

Info

Publication number
CN111540817A
CN111540817A CN202010424748.XA CN202010424748A CN111540817A CN 111540817 A CN111540817 A CN 111540817A CN 202010424748 A CN202010424748 A CN 202010424748A CN 111540817 A CN111540817 A CN 111540817A
Authority
CN
China
Prior art keywords
layer
type
emitting diode
diode chip
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010424748.XA
Other languages
Chinese (zh)
Inventor
王资文
方信乔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chuangchuang Display Technology Co ltd
Original Assignee
Chuangchuang Display Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chuangchuang Display Technology Co ltd filed Critical Chuangchuang Display Technology Co ltd
Priority to CN202010424748.XA priority Critical patent/CN111540817A/en
Publication of CN111540817A publication Critical patent/CN111540817A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

Abstract

The invention provides a micro light-emitting diode chip for emitting red light. The micro light emitting diode chip comprises a gallium arsenide epitaxial structure layer, a first electrode and a second electrode. The GaAs epitaxial structure layer sequentially comprises an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light emitting layer, an N-type semiconductor layer and an N-type window layer along a stacking direction. The first electrode is electrically contacted with the N-type contact layer. The second electrode is electrically contacted with the N-type window layer.

Description

Micro light-emitting diode chip
Technical Field
The present disclosure relates to chips, and particularly to a micro light emitting diode chip.
Background
Generally, for producing red light, an N-type gaas substrate is used as an epitaxial growth substrate, and after an N-type semiconductor layer is formed on the growth substrate, a light emitting layer and a P-type semiconductor layer are sequentially formed. The N-type GaAs substrate has a low material cost but a high yield control difficulty.
In some cases, a P-type gaas substrate is used as a growth substrate for epitaxy, and after a P-type semiconductor layer is formed on the growth substrate, a light-emitting layer and an N-type semiconductor layer are sequentially formed. However, the cost of the P-type gaas substrate is more than twice as high as that of the N-type gaas substrate, so that how to balance the cost and the yield quality is one of the research and development issues of the present technology.
Disclosure of Invention
The invention is directed to a micro light emitting diode chip, and the structure of the chip can improve the yield in the manufacturing process.
An embodiment of the invention provides a micro light emitting diode chip for emitting a red light, which includes a gallium arsenide epitaxial structure layer, a first electrode and a second electrode. The GaAs epitaxial structure layer sequentially comprises an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light emitting layer, an N-type semiconductor layer and an N-type window layer along a stacking direction. The first electrode is electrically contacted with the N-type contact layer. The second electrode is electrically contacted with the N-type window layer.
In an embodiment of the invention, the first electrode and the second electrode are located on a side of the micro light emitting diode chip opposite to the stacking direction.
In an embodiment of the invention, the gallium arsenide epitaxial structure layer has a recess. The recess defines a mesa structure, and the recess exposes a first surface of the N-type window layer on a side opposite to the stacking direction.
In an embodiment of the invention, the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer, the N-type semiconductor layer and a portion of the N-type window layer of the gaas epitaxial structure layer form a mesa structure. The area of the platform surface of the platform structure is smaller than that of the second surface of the N-type window layer on one side facing the stacking direction, wherein the platform surface is the surface of the N-type contact layer on the side opposite to the stacking direction.
In an embodiment of the invention, the gallium arsenide epitaxial structure layer has a trench. The trench penetrates through the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer, the N-type semiconductor layer and a part of the N-type window layer, and exposes a third surface of the N-type window layer on one side opposite to the stacking direction.
In an embodiment of the invention, the second electrode is disposed in the trench and electrically contacts the third surface of the N-type window layer.
In an embodiment of the invention, the micro led chip further includes an insulating layer. The insulating layer covers the inner wall of the groove, so that the second electrode is electrically insulated from the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer. The insulating layer is extended and arranged on the surface of the N-type contact layer on the side opposite to the stacking direction.
In an embodiment of the present invention, the thickness of the tunneling junction layer along the stacking direction is in a range of 50 to 500 angstroms.
In an embodiment of the invention, the thicknesses of the N-type contact layer, the tunneling junction layer and the light emitting layer along the stacking direction are less than the thicknesses of the other layers of the gaas epitaxial structure layer along the stacking direction.
In an embodiment of the invention, the tunnel junction layer is doped with N-type and P-type dopants simultaneously, and a ratio of a molar concentration of the P-type dopant to a molar concentration of the N-type dopant falls within a range of 10 to 100.
In an embodiment of the invention, a molar concentration of the P-type dopant of the tunneling junction layer is greater than a molar concentration of the P-type dopant of the P-type semiconductor layer.
In an embodiment of the invention, the substrate of the tunneling junction layer is (Al)xGa1-x)yIn1-yAszP1-zWherein 0 ≦ x, y, z ≦ 1.
In an embodiment of the invention, the P-type semiconductor layer has a magnesium dopant.
In view of the above, in the micro light emitting diode chip according to the embodiment of the invention, since the micro light emitting diode chip has the tunnel junction layer, and the tunnel junction layer is formed between the N-type contact layer and the P-type semiconductor layer, the P-type semiconductor layer can be formed earlier than the N-type semiconductor layer in the temperature raising process of semiconductor manufacturing. Therefore, the processing of the P-type semiconductor layer can be performed at a lower temperature, so that the micro light-emitting diode chip is not affected too much in the temperature rise process in the subsequent processing, and the yield of the micro light-emitting diode chip is higher.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a manufacturing process of a micro light emitting diode chip according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to another embodiment of the invention.
Description of the reference numerals
10A, 10B micro light-emitting diode chip
20 first substrate
30 second substrate
40: third substrate
100. 100A, 100B gallium arsenide epitaxial structure layer
110N type contact layer
110S surface
120 tunnel junction layer
130P-type semiconductor layer
140 luminescent layer
150N-type semiconductor layer
160: N-type window layer
160-1, 160-2 part
160S1 first surface
160S2 second surface
160S3 third surface
200 first electrode
300 second electrode
D, stacking direction
M is platform structure
MS platform surface
O1, O2 opening
R is a concave part
T is a groove
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a micro light emitting diode chip according to an embodiment of the invention. Referring to fig. 1A to fig. 1E, an embodiment of the invention provides a micro light emitting diode chip 10A, which includes a gallium arsenide epitaxial structure layer 100A, a first electrode 200, and a second electrode 300. In the present embodiment, the micro led chip 10A is, for example, a red or infrared micro led chip, but the invention is not limited thereto.
Referring to fig. 1A, first, a gallium arsenide epitaxial structure layer 100 is formed on a first substrate 20. In the present embodiment, the material of the first substrate 20 is low-doped N-gallium arsenide (GaAs) or neutral GaAs. The gaas epitaxial structure layer 100 sequentially includes an N-type contact layer 110, a tunneling junction layer 120, a P-type semiconductor layer 130, a light emitting layer 140, an N-type semiconductor layer 150, and an N-type window layer 160 along a stacking direction D. That is, the two outermost semiconductor layers of the gaas epitaxial structure layer 100 are both N-type.
Generally, the temperature of the semiconductor process is usually raised gradually. In order to form the P-type semiconductor layer 130 in the front-end process with a lower temperature during the temperature raising process of the semiconductor process, the gallium arsenide epitaxial structure layer 100 of the embodiment of the invention forms a tunneling junction layer (tunneling junction layer)120 between the N-type contact layer 110 and the P-type semiconductor layer 130. That is, the tunneling junction layer 120 is used to convert the N-type contact layer 110 into the P-type semiconductor layer 130 in the gaas epitaxial structure layer 100. Furthermore, in order to reduce the lattice matching problem during the epitaxy process, the material of the first substrate 20 is preferably selected to be low-doped N-gaas or neutral gaas. When the material of the first substrate 20 is P-gaas with low doping, another tunneling junction layer is formed between the first substrate 20 and the N-type contact layer 110.
In the present embodiment, the N-type contact layer 110 may be highly doped N + gaas.
In the present embodiment, the substrate of the tunneling junction layer 120 may be (Al)xGa1-x)yIn1-yAszP1-zWherein 0 ≦ x, y, z ≦ 1. The tunnel junction layer 120 may be highly doped with both N-type and P-type dopants. The N-type dopant of tunnel junction layer 120 is, for example, silicon (Si) or tellurium (Te), and the P-type dopant is, for example, carbon (C)C) Magnesium or zinc (Zn). In the present embodiment, the molar concentration of the P-type dopant is preferably greater than the molar concentration of the N-type dopant. In one embodiment, the ratio of the molar concentration of the P-type dopant to the molar concentration of the N-type dopant in the tunnel junction layer 120 is in the range of 10 to 100. If the molar concentration of the P-type dopant is too low, tunneling effect cannot be formed; if the molar concentration of the P-type dopant is too high, the chip appearance tends to be problematic. In addition, the thickness of tunnel interface layer 120 in the direction along the stacking direction D falls within 50 to 500 angstroms (angstrom,
Figure BDA0002498273210000051
) Within the range of (1).
In the present embodiment, the P-type semiconductor layer 130 is used to provide holes for the light emitting layer 140, and the N-type semiconductor layer 150 is used to provide electrons for the light emitting layer 140, so that the electrons and the holes are combined in the light emitting layer 140 and the energy is converted into photons to emit light.
In the present embodiment, the substrate of the P-type semiconductor layer 130 may be (Al)xGa1-x)yIn1-yAszP1-zAnd the dopant can be carbon, magnesium (Mg), or zinc, where 0 ≦ x, y, z ≦ 1. In addition, the molar concentration of the P-type dopant in the tunnel junction layer 120 is preferably greater than the molar concentration of the P-type dopant in the P-type semiconductor layer 130.
In the embodiment, the structure of the light emitting layer 140 may be a Multiple-Quantum Well (MQW) structure, a single Quantum Well structure, a Double Heterostructure (Double Heterostructure), a single Heterostructure, or a combination thereof. The material of the light emitting layer 140 may be a semiconductor material of gallium arsenide system, and is preferably (Al)xGa1-x)yIn1-yAszP1-zWherein 0 ≦ x, y, z ≦ 1.
In the present embodiment, the substrate of the N-type semiconductor layer 150 may be (Al)xGa1-x)yIn1-yAszP1-zAnd the dopant can be silicon or tellurium, where 0 ≦ x, y, z ≦ 1.
In the present embodiment, the N-type window layer 160 is used as a light extraction (light extraction) layer. The substrate of the N-type window layer 160 may be (Al)xGa1-x)yIn1-yAszP1-zAnd the dopant can be silicon or tellurium, where 0 ≦ x, y, z ≦ 1.
In one embodiment, the molar concentration of the P-type dopant in the P-type semiconductor layer 130 is between 1E17 and 2E18, the molar concentration of the N-type dopant in the N-type semiconductor layer 150 is between 1E18 and 2E18, and the molar concentrations of the P-type dopant and the N-type dopant in the tunneling junction layer 120 are greater than 1E 19.
Referring to fig. 1B, the second substrate 30 is then disposed on the N-type window layer 160 of the gaas epitaxial structure layer 100 by bonding (bonding), and the first substrate 20 is removed. In the present embodiment, the material of the second substrate 30 can be sapphire (sapphire)
Referring to fig. 1C, the gaas epitaxial structure layer 100 is etched by using an Inductively Coupled plasma Etching (ICP Etching) method, so that the gaas epitaxial structure layer 100A has a recess R. In the present embodiment, the recess R defines a mesa structure M, and the recess R exposes the first surface 160S1 of the N-type window layer 160 on the side opposite to the stacking direction D. In detail, the N-type contact layer 110, the tunneling junction layer 120, the P-type semiconductor layer 130, the light emitting layer 140, the N-type semiconductor layer 150, and the N-type window layer 160 of the portion 160-1 of the gaas epitaxial structure layer 100A form a mesa structure M. The area of the mesa surface MS of the mesa structure M, which is the surface of the N-type contact layer 110 on the side opposite to the stacking direction D, is smaller than the area of the second surface 160S2 of the N-type window layer 160 on the side facing the stacking direction D.
Referring to fig. 1D, the first electrode 200 and the second electrode 300 may be simultaneously bonded to the gaas epitaxial structure layer 100A. In the present embodiment, the first electrode 200 is electrically contacted with the N-type contact layer 110. The second electrode 300 is in electrical contact with the N-type window layer 160. Furthermore, the second electrode 300 is electrically contacted with the first surface 160S1 exposed by the N-type window layer 160, and the first surface 160S1 is a surface of the N-type window layer 160 not belonging to the portion 160-2 of the mesa structure M. In the present embodiment, the material of the first electrode 200 and the second electrode 300 may be germanium-gold alloy (GeAu) or other metals that can generate ohmic contact (ohmic contact) with an N-type semiconductor.
Referring to fig. 1E, finally, the first electrode 200 and the second electrode 300 are bonded to the third substrate 40, so as to manufacture the micro light emitting diode chip 10A according to the embodiment of the invention. In this embodiment, the third substrate 40 may be made of sapphire or glass. In addition, the first electrode 200 and the second electrode 300 are both located on the side of the micro light emitting diode chip 10A opposite to the stacking direction D.
In another embodiment, the second substrate 30 of the micro led chip 10A in fig. 1E can be further removed to facilitate the subsequent transfer of the micro led chip 10A.
In view of the above, in the micro led chip 10A according to the embodiment of the invention, since the micro led chip 10A has the tunnel junction layer 120 and the tunnel junction layer 120 is formed between the N-type contact layer 110 and the P-type semiconductor layer 130, the P-type semiconductor layer 130 can be formed earlier than the N-type semiconductor layer 150 during the temperature raising process of the semiconductor manufacturing. Thus, the P-type semiconductor layer 130 can be processed at a lower temperature. Furthermore, in the micro led chip 10A according to the embodiment of the invention, only the P-type semiconductor layer 130 needs to be formed, and even if the P-type semiconductor layer 130 uses a component such as magnesium that is easily diffused as a dopant, the structure of the P-type semiconductor layer 130 is formed at a lower temperature, so that the temperature rise process in the subsequent manufacturing process does not have much influence on the micro led chip 10A. Therefore, the yield of the micro led chip 10A is high. Moreover, when the P-type semiconductor layer 130 is a P-type semiconductor and the N-type semiconductor layer 150 is an N-type semiconductor, the N-window layer 160 does not need to be made into a P-type semiconductor, and the micro light emitting diode chip 10A can reduce the use of, for example, magnesium as a dopant. Therefore, the yield of the micro led chip 10A according to the embodiment of the invention is high.
Furthermore, an ohmic contact layer is usually additionally formed on the P-type semiconductor layer to effectively distribute the current from the P-type contact electrode to the light emitting layer. The ohmic contact layer is, for example, Indium Tin Oxide (ITO). However, the alloy temperature is about 500 to 550 degrees C during the process of forming the P-type contact electrode on the ohmic contact layer. Such high temperature is likely to damage the semiconductor device, thereby affecting the yield of the led. In the micro led chip 10A according to the embodiment of the invention, since the first electrode 200 and the second electrode 300 are both electrically contacted to the N-type semiconductor, the surfaces 160S1 and MS of the gaas epitaxial structure layer 100A contacting the first electrode 200 and the second electrode 300 do not need to be additionally formed with an ohmic contact layer, and the bonding between the metal and the semiconductor can be performed at a lower temperature, for example, 300 to 350 ℃. The yield of the micro light-emitting diode chip 10A of the embodiment of the invention can be improved, and the cost can be reduced.
In addition, in one embodiment, the thicknesses of the N-type contact layer 110, the tunneling junction layer 120, and the light-emitting layer 140 of the gaas epitaxial structure layer 100, 100A along the stacking direction D are preferably smaller than the thicknesses of the other layers of the gaas epitaxial structure layer 100, 100A along the stacking direction D.
Fig. 2 is a schematic cross-sectional view of a micro light emitting diode chip according to another embodiment of the invention. Referring to fig. 2, in the present embodiment, the gallium arsenide epitaxial structure layer 100B of the micro light emitting diode chip 10B has a trench T. The trench T passes through the N-type contact layer 110, the tunnel junction layer 120, the P-type semiconductor layer 130, the light emitting layer 140, the N-type semiconductor layer 150, and a portion of the N-type window layer 160, and exposes a third surface 160S3 of the N-type window layer 160 on a side opposite to the stacking direction D.
In the present embodiment, the second electrode 300 is disposed in the trench T and electrically contacts the third surface 160S3 of the N-type window layer 160.
In the present embodiment, the micro light emitting diode chip 10B further includes an insulating layer 170. The insulating layer 170 covers the inner wall of the trench T, so that the second electrode 300 electrically insulates the N-type contact layer 110, the tunneling junction layer 120, the P-type semiconductor layer 130, the light emitting layer 140, and the N-type semiconductor layer 150. The insulating layer 170 extends from the surface 110S of the N-type contact layer 110 on the side opposite to the stacking direction D. In addition, the insulating layer 170 has an opening O2 on the surface 110S of the N-type contact layer 110 on the side opposite to the stacking direction D. The first electrode 200 is electrically connected to the N-type contact layer 110 through the opening O2. Furthermore, the insulating layer 170 has another opening O1 at the trench T, and the second electrode 300 is electrically contacted to the third surface 160S3 of the N-type window layer 160 through the opening O1.
In view of the above, in the micro light emitting diode chip 10B according to the embodiment of the invention, since the gallium arsenide epitaxial structure layer 100B of the micro light emitting diode chip 10B has the trench T and the micro light emitting diode chip 10B further includes the insulating layer 170, the second electrode 300 can be electrically contacted with the N-type window layer 160 through the trench T under the condition that the N-type contact layer 110, the tunneling junction layer 120, the P-type semiconductor layer 130, the light emitting layer 140 and the N-type semiconductor layer 150 are electrically insulated. The micro light-emitting diode Chip 10B of the embodiment of the invention can be applied to Flip Chip technology, so that the Chip packaging process is more convenient.
In summary, in the micro led chip according to the embodiment of the invention, since the micro led chip has the tunneling junction layer, and the tunneling junction layer is formed between the N-type contact layer and the P-type semiconductor layer, the P-type semiconductor layer can be formed earlier than the N-type semiconductor layer in the temperature raising process of the semiconductor manufacturing. Therefore, the processing of the P-type semiconductor layer can be performed at a lower temperature, so that the micro light-emitting diode chip is not affected too much in the temperature rise process in the subsequent processing, and the yield of the micro light-emitting diode chip is higher. In addition, in the micro light emitting diode chip of the embodiment of the invention, the surface of the gallium arsenide epitaxial structure layer, the first electrode and the second electrode in contact does not need to be additionally provided with an ohmic N-type contact layer, and the metal and the semiconductor can be bonded at a lower temperature, so that the yield of the micro light emitting diode chip of the embodiment of the invention can be improved, and the cost can be reduced.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (13)

1. A micro light emitting diode chip for emitting red or infrared light, the micro light emitting diode chip comprising:
the gallium arsenide epitaxial structure layer sequentially comprises an N-type contact layer, a tunneling junction layer, a P-type semiconductor layer, a light emitting layer, an N-type semiconductor layer and an N-type window layer along the stacking direction;
the first electrode is electrically contacted with the N-type contact layer; and
and the second electrode is electrically contacted with the N-type window layer.
2. The micro light-emitting diode chip of claim 1, wherein the first electrode and the second electrode are located on a side of the micro light-emitting diode chip opposite to the stacking direction.
3. The micro light emitting diode chip of claim 1, wherein the gallium arsenide epitaxial structure layer has a recess, the recess defines a mesa structure, and the recess exposes a first surface of the N-type window layer on a side opposite to the stacking direction.
4. The micro light emitting diode chip of claim 3, wherein the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer, the N-type semiconductor layer, and a portion of the N-type window layer of the GaAs epitaxial structure layer form the mesa structure, and an area of a mesa surface of the mesa structure is smaller than an area of a second surface of the N-type window layer on a side facing the stacking direction, wherein the mesa surface is a surface of the N-type contact layer on a side opposite to the stacking direction.
5. The micro light emitting diode chip as claimed in claim 1, wherein the GaAs epitaxial structure layer has a trench passing through the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer, the N-type semiconductor layer and a portion of the N-type window layer, and the trench exposes a third surface of the N-type window layer on a side opposite to the stacking direction.
6. The micro light emitting diode chip as claimed in claim 5, wherein the second electrode is disposed in the trench and electrically contacts the third surface of the N-type window layer.
7. The micro light-emitting diode chip of claim 5, further comprising:
and the insulating layer covers the inner wall of the groove, so that the second electrode is electrically insulated from the N-type contact layer, the tunneling junction layer, the P-type semiconductor layer, the light emitting layer and the N-type semiconductor layer, and the insulating layer extends and is arranged on the surface of the N-type contact layer on the side opposite to the stacking direction.
8. The micro light-emitting diode chip of claim 1, wherein the thickness of the tunneling interface layer along the stacking direction falls within a range of 50 to 500 angstroms.
9. The micro light emitting diode chip as claimed in claim 1, wherein the thickness of the N-type contact layer, the tunneling junction layer and the light emitting layer along the stacking direction is smaller than the thickness of other layers of the gallium arsenide epitaxial structure layer along the stacking direction.
10. The micro light emitting diode chip of claim 1, wherein the tunneling junction layer is doped with N-type and P-type dopants simultaneously, and a ratio of a molar concentration of the P-type dopant to a molar concentration of the N-type dopant is in a range of 10 to 100.
11. The micro light emitting diode chip of claim 10, wherein the molar concentration of the P-type dopant of the tunneling junction layer is greater than the molar concentration of the P-type dopant of the P-type semiconductor layer.
12. The micro light emitting diode chip of claim 10, wherein the tunneling junction layer has a matrix of (AlxGa1-x) yIn1-yAszP1-z, where 0 ≦ x, y, z ≦ 1.
13. The micro light-emitting diode chip of claim 1, wherein the P-type semiconductor layer has a magnesium dopant.
CN202010424748.XA 2020-05-19 2020-05-19 Micro light-emitting diode chip Pending CN111540817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010424748.XA CN111540817A (en) 2020-05-19 2020-05-19 Micro light-emitting diode chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010424748.XA CN111540817A (en) 2020-05-19 2020-05-19 Micro light-emitting diode chip

Publications (1)

Publication Number Publication Date
CN111540817A true CN111540817A (en) 2020-08-14

Family

ID=71976009

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010424748.XA Pending CN111540817A (en) 2020-05-19 2020-05-19 Micro light-emitting diode chip

Country Status (1)

Country Link
CN (1) CN111540817A (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287687A1 (en) * 2004-06-28 2005-12-29 Tien-Fu Liao Method of fabricating algainp light-emitting diode and structure thereof
CN1819285A (en) * 2005-02-07 2006-08-16 日立电线株式会社 Epitaxial wafer for light emitting diode
CN101897048A (en) * 2007-12-14 2010-11-24 皇家飞利浦电子股份有限公司 Be used for the contact of light emitting semiconductor device
CN104538527A (en) * 2014-12-31 2015-04-22 山东浪潮华光光电子股份有限公司 Distributed n-face ohmic contact reversed polarity AlGaInP light emitting diode
TW201801343A (en) * 2016-06-29 2018-01-01 光鋐科技股份有限公司 Epitaxial structure with tunnel junction, p-side up processing intermediate structure and manufacturing process thereof
CN107546303A (en) * 2017-08-25 2018-01-05 扬州乾照光电有限公司 A kind of AlGaInP based light-emitting diodes and its manufacture method
CN107681034A (en) * 2017-08-30 2018-02-09 天津三安光电有限公司 It is micro-led and preparation method thereof
CN109244205A (en) * 2018-09-12 2019-01-18 肖和平 A kind of inverted structure AlGaInP feux rouges Micro-LED and preparation method thereof
CN109545940A (en) * 2018-11-23 2019-03-29 江苏新广联半导体有限公司 It is a kind of to carry on the back out light red light chips and preparation method thereof
CN110915005A (en) * 2018-05-02 2020-03-24 天津三安光电有限公司 Light emitting diode and manufacturing method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050287687A1 (en) * 2004-06-28 2005-12-29 Tien-Fu Liao Method of fabricating algainp light-emitting diode and structure thereof
CN1819285A (en) * 2005-02-07 2006-08-16 日立电线株式会社 Epitaxial wafer for light emitting diode
CN101897048A (en) * 2007-12-14 2010-11-24 皇家飞利浦电子股份有限公司 Be used for the contact of light emitting semiconductor device
CN104538527A (en) * 2014-12-31 2015-04-22 山东浪潮华光光电子股份有限公司 Distributed n-face ohmic contact reversed polarity AlGaInP light emitting diode
TW201801343A (en) * 2016-06-29 2018-01-01 光鋐科技股份有限公司 Epitaxial structure with tunnel junction, p-side up processing intermediate structure and manufacturing process thereof
CN107546303A (en) * 2017-08-25 2018-01-05 扬州乾照光电有限公司 A kind of AlGaInP based light-emitting diodes and its manufacture method
CN107681034A (en) * 2017-08-30 2018-02-09 天津三安光电有限公司 It is micro-led and preparation method thereof
CN110915005A (en) * 2018-05-02 2020-03-24 天津三安光电有限公司 Light emitting diode and manufacturing method thereof
CN109244205A (en) * 2018-09-12 2019-01-18 肖和平 A kind of inverted structure AlGaInP feux rouges Micro-LED and preparation method thereof
CN109545940A (en) * 2018-11-23 2019-03-29 江苏新广联半导体有限公司 It is a kind of to carry on the back out light red light chips and preparation method thereof

Similar Documents

Publication Publication Date Title
TWI750664B (en) Micro light emitting diode chip
JP5496104B2 (en) Contact for semiconductor light emitting devices
US7807521B2 (en) Nitride semiconductor light emitting device and method of manufacturing the same
WO2018003374A1 (en) Manufacturing method for semiconductor optical device, and semiconductor optical device
JP3207773B2 (en) Compound semiconductor light emitting device and method of manufacturing the same
KR20200123126A (en) Light-emitting diode and its manufacturing method
JP2004153241A (en) Semiconductor light emitting device and method of manufacturing same
TWI594459B (en) Light-emitting device and the manufacturing method thereof
TWI755761B (en) Manufacturing method of semiconductor optical element
JP3665243B2 (en) Nitride semiconductor device and manufacturing method thereof
CN111540817A (en) Micro light-emitting diode chip
JP2005235798A (en) Light-emitting diode, and epitaxial wafer for the same
KR20190133382A (en) A surface-emitting laser device and light emitting device including the same
US20150263229A1 (en) Semiconductor light-emitting device and method of manufacturing the same
JP2006032665A (en) Light emitting diode
CN111354842A (en) Semiconductor device with a plurality of semiconductor chips
WO2023142147A1 (en) Micro led structure and micro display panel
WO2023142146A1 (en) Micro led structure and micro display panel
WO2023142152A1 (en) Micro led structure and micro display panel
WO2023142150A1 (en) Micro led structure and micro display panel
WO2023142149A1 (en) Micro led structure and micro display panel
WO2023142151A1 (en) Micro led structure and micro display panel
WO2023142145A1 (en) Micro led structure and micro display panel
WO2023142148A1 (en) Micro led structure and micro display panel
US20240030387A1 (en) Light-emitting device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20200814

RJ01 Rejection of invention patent application after publication