CN111538687A - Memory control method, memory storage device and memory control circuit unit - Google Patents

Memory control method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN111538687A
CN111538687A CN202010322828.4A CN202010322828A CN111538687A CN 111538687 A CN111538687 A CN 111538687A CN 202010322828 A CN202010322828 A CN 202010322828A CN 111538687 A CN111538687 A CN 111538687A
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voltage level
data
read voltage
read
memory
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CN111538687B (en
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林纬
曾士家
许祐诚
杨宇翔
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a memory control method, which comprises the following steps: sending a first read command sequence instructing to read a first physical unit using a first read voltage level to obtain first data; decoding the first data; if the first data decoding fails, sending a second read command sequence indicating that the first entity unit is read by using a second read voltage level to obtain second data; if the second read voltage level meets the first condition or the second data meets the second condition, decoding the second data by using the auxiliary information to improve the decoding success rate of the second data; and if the second read voltage level does not meet the first condition and the second data does not meet the second condition, decoding the second data without using the auxiliary information. In addition, the invention also provides a memory storage device and a memory control circuit unit.

Description

Memory control method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Some types of memory storage devices support both hard bit pattern decoding and soft bit pattern decoding. The hard bit mode decoding has a faster decoding speed, while the soft bit mode decoding has a higher decoding success rate. In the hard bit pattern decoding, each time the decoding fails, a read voltage level for reading a memory cell in the rewritable nonvolatile memory module may be adjusted with reference to the re-read table, and the adjusted read voltage level may be used to re-read data (also referred to as a hard bit). Once the number of retries of the hard bit pattern decoding exceeds a preset value, the soft bit pattern decoding may be performed. In soft bit mode decoding, more read voltage levels can be used to read the memory cells to obtain additional information (also referred to as soft bits) about the hard bits to improve the decoding success rate by introducing the additional information.
However, for the rewritable nonvolatile memory module with a severe voltage offset, the decoding success rate of the hard bit mode decoding is low, so that the system needs to spend much time waiting for the end of the hard bit mode decoding to successfully decode data in the soft bit mode decoding.
Disclosure of Invention
The invention provides a memory control method, a memory storage device and a memory control circuit unit, which can effectively improve the decoding success rate of data in hard bit mode decoding.
An exemplary embodiment of the present invention provides a memory control method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control method includes: sending a first read command sequence instructing reading a first physical cell of the plurality of physical cells using a first read voltage level to obtain first data; decoding the first data; if the decoding of the first data fails, sending a second read command sequence indicating that a second read voltage level is used for reading the first entity unit to obtain second data, wherein the second read voltage level is different from the first read voltage level; if the second read voltage level meets a first condition or the second data meets a second condition, decoding the second data by using auxiliary information, wherein the auxiliary information is used for improving the decoding success rate of the second data; and if the second read voltage level does not meet the first condition and the second data does not meet the second condition, decoding the second data without using the assistance information.
In an exemplary embodiment of the invention, the memory control method further includes: and determining whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range.
In an exemplary embodiment of the invention, the memory control method further includes: obtaining a syndrome value of the second data, wherein the syndrome value is related to a bit error rate of the second data; and determining whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
In an exemplary embodiment of the invention, the memory control method further includes: prior to sending the first sequence of read instructions, sending a third sequence of read instructions that indicates to read the first physical unit using a third read voltage level to obtain third data; decoding the third data; and determining a specific voltage range according to the first read voltage level and the third read voltage level, wherein one of the first read voltage level and the third read voltage level is used for defining an upper boundary of the specific voltage range, and the other one of the first read voltage level and the third read voltage level is used for defining a lower boundary of the specific voltage range.
In an exemplary embodiment of the invention, the memory control method further includes: updating a boundary of the particular voltage range according to the second read voltage level.
In an exemplary embodiment of the present invention, the step of updating the boundary value of the specific voltage range according to the second read voltage level includes: and determining whether to update the boundary of the specific voltage range according to the relative relation between the second reading voltage level and the specific voltage range.
In an exemplary embodiment of the invention, the memory control method further includes: if the second read voltage level meets the first condition or the second data meets the second condition, dividing a plurality of voltage intervals according to the first read voltage level and the second read voltage level; and determining the auxiliary information according to the divided voltage intervals.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to send a first read command sequence instructing a first physical unit of the plurality of physical units to be read using a first read voltage level to obtain first data. The memory control circuitry unit is also to decode the first data. If the decoding of the first data fails, the memory control circuit unit is further configured to send a second read instruction sequence, which indicates to read the first entity unit using a second read voltage level to obtain second data. The second read voltage level is different from the first read voltage level. The memory control circuit unit is further configured to decode the second data using auxiliary information if the second read voltage level meets a first condition or the second data meets a second condition, wherein the auxiliary information is used to increase a decoding success rate of the second data. The memory control circuitry unit is further configured to decode the second data without using the assist information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to determine whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to obtain a syndrome value of the second data, the syndrome value being related to a bit error rate of the second data. The memory control circuit unit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
In an exemplary embodiment of the invention, before the first read command sequence is issued, the memory control circuit unit is further configured to issue a third read command sequence indicating that the first physical unit is to be read using a third read voltage level to obtain third data. The memory control circuit unit is also to decode the third data. The memory control circuit unit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level. One of the first read voltage level and the third read voltage level is used to define an upper boundary of the particular voltage range. The other of the first read voltage level and the third read voltage level is used to define a lower boundary of the particular voltage range.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to update the boundary of the specific voltage range according to the second read voltage level.
In an exemplary embodiment of the present invention, the operation of the memory control circuit unit updating the boundary value of the specific voltage range according to the second read voltage level includes: determining whether to update the boundary of the specific voltage range according to a relative relationship between the second reading voltage level and the specific voltage range.
In an exemplary embodiment of the invention, if the second read voltage level meets the first condition or the second data meets the second condition, the memory control circuit unit is further configured to divide a plurality of voltage intervals according to the first read voltage level and the second read voltage level. The memory control circuit unit is further configured to determine the auxiliary information according to the divided voltage intervals.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a memory storage device. The memory storage device comprises a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit comprises a host interface, a memory interface, a decoding circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the decoding circuit. The memory management circuit is configured to send a first read command sequence instructing a first physical cell of the plurality of physical cells to be read using a first read voltage level to obtain first data. The decoding circuit is used for decoding the first data. If the decoding of the first data fails, the memory management circuit is further configured to send a second read instruction sequence indicating that the first entity unit is to be read using a second read voltage level to obtain second data. The second read voltage level is different from the first read voltage level. The decoding circuit is further configured to decode the second data using auxiliary information if the second read voltage level meets a first condition or the second data meets a second condition, wherein the auxiliary information is used to increase a decoding success rate of the second data. The decoding circuit is further configured to decode the second data without using the assist information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
In an exemplary embodiment of the invention, the memory management circuit is further configured to determine whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range.
In an exemplary embodiment of the invention, the memory management circuit is further configured to obtain a syndrome value of the second data. The syndrome value is related to a bit error rate of the second data. The memory management circuit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
In an example embodiment of the present invention, before the first read command sequence is issued, the memory management circuit is further configured to issue a third read command sequence indicating that the first physical unit is to be read using a third read voltage level to obtain third data. The decoding circuit is also to decode the third data. The memory management circuit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level. One of the first read voltage level and the third read voltage level is used to define an upper boundary of the particular voltage range. The other of the first read voltage level and the third read voltage level is used to define a lower boundary of the particular voltage range.
In an exemplary embodiment of the invention, the memory management circuit is further configured to update the boundary of the specific voltage range according to the second read voltage level.
In an exemplary embodiment of the present invention, the operation of the memory management circuit updating the boundary value of the specific voltage range according to the second read voltage level includes: and determining whether to update the boundary of the specific voltage range according to the relative relation between the second reading voltage level and the specific voltage range.
In an exemplary embodiment of the invention, the memory management circuit is further configured to divide a plurality of voltage intervals according to the first read voltage level and the second read voltage level if the second read voltage level meets the first condition or the second data meets the second condition. The memory management circuit is further configured to determine the auxiliary information according to the divided voltage intervals.
Based on the above, after at least one reading of the first entity unit and at least one decoding failure, the auxiliary information capable of improving the decoding success rate of the data is only used when a specific condition is satisfied, rather than unconditionally used in each re-reading and decoding. Therefore, the decoding success rate can be prevented from being reduced due to excessive use or adjustment of auxiliary information on the premise of trying to improve the decoding success rate of data in hard bit mode decoding.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a graph illustrating a threshold voltage distribution of memory cells according to an exemplary embodiment of the present invention;
FIG. 8 is a diagram illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode according to an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating threshold voltage distributions and read voltage levels used in a soft bit decoding mode according to an exemplary embodiment of the present invention;
FIG. 10 is a diagram illustrating specific voltage ranges in accordance with an exemplary embodiment of the present invention;
FIG. 11 is a diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention;
FIG. 12 is a diagram illustrating a parity check operation according to an exemplary embodiment of the present invention;
FIG. 13 is a diagram illustrating updating the boundaries of a specific voltage range according to an exemplary embodiment of the present invention;
FIG. 14 is a diagram illustrating division of voltage intervals according to read voltage levels used in hard bit pattern decoding according to an exemplary embodiment of the present invention;
FIG. 15 is a diagram illustrating division of voltage intervals according to read voltage levels used in hard bit pattern decoding according to an exemplary embodiment of the present invention;
FIG. 16 is a graph illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode in accordance with an exemplary embodiment of the present invention;
FIG. 17 is a diagram illustrating specific voltage ranges and multiple read voltage levels according to an exemplary embodiment of the present invention;
FIG. 18 is a graph illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode in accordance with an exemplary embodiment of the present invention;
FIG. 19 is a diagram illustrating specific voltage ranges and multiple read voltage levels according to an exemplary embodiment of the present invention;
FIG. 20 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention;
FIG. 21 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention.
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a Near Field Communication (NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a low power Bluetooth memory storage (e.g., iBeacon) based memory storage based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi media card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) memory device 342, which directly connects the memory module to the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the memory stick (memory stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash memory (Flash Storage, CF) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid state type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate (control gate) and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating to write data, a read instruction sequence for indicating to read data, an erase instruction sequence for indicating to erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
An error checking and correcting circuit (also referred to as a decoding circuit) 508 is coupled to the memory management circuit 502 and is used to perform error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
It is noted that the error checking and correcting circuit 508 can support both hard bit mode decoding operations and soft bit mode decoding operations. The decoding speed per one time of the hard bit mode decoding operation is faster than that of the soft bit mode decoding operation. However, the decoding success rate per soft bit mode decoding operation is higher than that per hard bit mode decoding operation.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0) - (610 a) in the storage area 601 are used for storing data, and the physical units 610(a +1) - (610B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It is noted that if there are no physical erase units available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.
In the present exemplary embodiment, each physical unit refers to a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erase unit, or be composed of a plurality of consecutive or non-consecutive physical addresses. The memory management circuitry 502 configures the logic units 612(0) - (612 (C) to map the physical units 610(0) - (610A) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. In addition, each of logic cells 612(0) -612 (C) may be mapped to one or more physical cells.
The memory management circuit 502 can record a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical address mapping table.
FIG. 7 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention. Referring to fig. 7, in the case of a TLC NAND flash memory module, after a certain physical cell (also referred to as a first physical cell) is programmed, the threshold voltage of each programmed memory cell in the first physical cell may belong to one of states 701-708. For example, if a plurality of programmed memory cells are respectively used to store bits "111", "011", "001", "000", "010", "110", "100" and "101", the memory cells will respectively belong to states 701-708. When data stored in the memory cells is to be read, read voltage levels V1-V7 are applied to the first physical cell. According to the conducting state of each memory cell in the first entity unit responding to the reading voltage levels V1-V7, the state of each memory cell can be identified, and the data stored by each memory cell can be obtained.
It is noted that in another exemplary embodiment, if SLC NAND type flash memory module, MLC NAND type flash memory module or QLC NAND type flash memory module is taken as an example, the number of bits stored in each memory cell may be different. Therefore, the threshold voltage distribution of the memory cell may have more or less states, and the invention is not limited thereto.
FIG. 8 is a diagram illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode according to an exemplary embodiment of the present invention. Referring to fig. 8, states 801 and 802 can be any two adjacent states in fig. 7. Depending on the environment of use (e.g., ambient temperature) and/or the extent of use (e.g., time of use), there may be an overlap between states 801 and 802, such that subsequent data read from this overlap region has a high probability of containing erroneous bits.
In the hard bit decode mode, the memory management circuit 502 can send a read command sequence instructing the rewritable nonvolatile memory module 406 to use a read voltage level (e.g., the read voltage level V)R(1)) The first physical unit is read. Memory management circuitry 502 may obtain data reflecting the read result of this read voltage level. Error checking and correction circuitry 508 may decode this data. If the data is decoded successfully, the successfully decoded data can be output (e.g., transmitted to the host system). If the decoding of the data fails, the memory management circuit 502 can send another read command sequence indicating that the rewritable non-volatile memory module 406 uses another read voltage level (e.g., the read voltage level V)R(2)) The first physical unit is read. Memory management circuitry 502 may obtain data reflecting the read result of this read voltage level. Error checking and correction circuitry 508 may decode this data.
And so on, in the hard bit decoding mode, before the retry number exceeds a retry threshold, each time the decoding fails, a different read voltage level (e.g., read voltage level V)R(3)And/or read voltage level VR(4)) May be used again to read the first physical unit and the read data may be decoded. In addition, the information of the read voltage level used in the hard bit decoding mode can be recorded in a retry table. According to the retry table, multiple readsTaking a voltage level (e.g. read voltage level V)R(1)～VR(4)) Can be used sequentially in the hard bit decoding mode.
In an exemplary embodiment, if the number of retries of the hard bit decoding mode exceeds the retry threshold, it indicates that all errors in the read data cannot be corrected by the decoding capability of the hard bit decoding mode. Thus, the error checking and correcting circuit 508 may enter a soft bit decoding mode to improve the decoding capability for the data.
FIG. 9 is a diagram illustrating threshold voltage distributions and read voltage levels used in a soft bit decoding mode according to an exemplary embodiment of the present invention. Referring to FIG. 9, in the soft bit decoding mode, the memory management circuit 502 can send a plurality of read command sequences instructing the rewritable nonvolatile memory module 406 to use a plurality of read voltage levels (e.g., the read voltage level V)S(1)～VS(5)) The first physical unit is read. Memory management circuitry 502 may obtain data reflecting read results of such read voltage levels. According to the read results of the read voltage levels, the threshold voltage of each memory cell can be identified as belonging to one of a plurality of voltage intervals (e.g., voltage intervals 901-906) and assigned with corresponding reliability information. An example of the reliability information is Log Likelihood Ratio (LLR), and the reliability information corresponding to the voltage interval that is farther to the left has a smaller value.
After determining the reliability information corresponding to each voltage interval according to the read results of the read voltage levels, the error checking and correcting circuit 508 can use the corresponding reliability information to decode the data read from the memory cells using a specific read voltage level according to the voltage interval to which each memory cell belongs. For example, the specific read voltage level is also referred to as a sign read voltage level and is used to initially determine whether the bit read from each memory cell is "0" or "1". Taking FIG. 9 as an example, the specific read voltage level may be a read voltage level VS(1)。
On the other hand, in the hard bit decoding mode of fig. 8, data reflecting the read result of a read voltage level is decoded once every time a read voltage level is applied. However, in the soft bit decoding mode of fig. 9, data reflecting the read result of a specific read voltage level is decoded once after a plurality of read voltage levels are consecutively applied.
Conventionally, each decoding in the hard bit decoding mode merely decodes the data obtained by applying a read voltage level each time, unlike the soft bit decoding mode, which dynamically generates or updates the reliability information for improving the decoding success rate. Therefore, the decoding success rate of the hard bit decoding mode is generally low. In the case of a memory cell with a severe threshold voltage shift, the system may need to wait until all the read voltage levels in the hard bit decoding mode are used before entering the soft bit decoding mode, resulting in an extended decoding time.
In an example embodiment, in the hard bit decode mode, the memory management circuit 502 may send a read command sequence (also referred to as a first read command sequence) that indicates to read the first physical unit using a read voltage level (also referred to as a first read voltage level) to obtain a data (also referred to as a first data). The first data may reflect a result of reading each memory cell in the first physical cell by the first read voltage level. The error checking and correcting circuit 508 may decode the first data. If the decoding of the first data is successful, the successfully decoded first data can be output.
If the decoding of the first data fails, the memory management circuit 502 may send another read command sequence (also referred to as a second read command sequence) that indicates to read the first physical cell using another read voltage level (also referred to as a second read voltage level) to obtain another data (also referred to as a second data). The second data may reflect a result of reading each memory cell of the first physical cell by the second read voltage level. The second read voltage level is different from the first read voltage level. Taking FIG. 8 as an example, the first read voltage level and the second read voltage level can be the read voltage level VR(1)～VR(4)Any two of (1).
After obtaining the second data, the memory management circuit 502 may determine whether the second read voltage level meets a specific condition (also referred to as a first condition) and/or whether the second data meets a specific condition (also referred to as a second condition). If the second read voltage level meets the first condition or the second data meets the second condition, the error checking and correcting circuit 508 may decode the second data using the auxiliary information. This side information may be used to increase the decoding success rate of the second data. For example, the auxiliary information may include reliability information that is dynamically determined corresponding to a plurality of voltage intervals (similar to the reliability information that is dynamically determined in the example embodiment of fig. 9). After the side information is introduced to decode the second data, the decoding success rate of the second data can be significantly improved even in the hard bit decoding mode.
However, if the second read voltage level does not satisfy the first condition and the second data does not satisfy the second condition, the error checking and correcting circuit 508 may decode the second data without using the auxiliary information. For example, if the second read voltage level does not meet the first condition and the second data does not meet the second condition, the error checking and correcting circuit 508 may maintain the predetermined decoding operation in the hard bit decoding mode to decode the second data without additionally referring to the dynamically determined reliability information. In other words, by using the side information properly and correctly in the hard bit decoding mode, it is possible to prevent the decoding success rate of the data from being lowered due to excessive use or adjustment of the side information.
In an example embodiment, the memory management circuit 502 may determine whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range. In an example embodiment, the memory management circuit 502 may determine that the second read voltage level meets the first condition if the second read voltage level is within a specific voltage range. In an example embodiment, the memory management circuit 502 may determine that the second read voltage level does not meet the first condition if the second read voltage level is not within the specific voltage range.
FIG. 10 is a diagram illustrating specific voltage ranges according to an exemplary embodiment of the present invention. Please refer to fig. 8 andFIG. 10, in an exemplary embodiment, uses a read voltage level VR(1)And VR(2)After reading the first physical cell and unsuccessfully decoding the data, the memory management circuit 502 can read the data according to the read voltage level VR(1)And VR(2)A specific voltage range is determined 1010. For example, memory management circuit 502 may be based on a read voltage level VR(1)Determining the boundary 1011 of the specific voltage range 1010 according to the read voltage level VR(2)The boundary 1012 of the particular voltage range 1010 is determined. In other words, the particular voltage range 1010 includes the voltage range between boundaries 1011 and 1012.
FIG. 11 is a diagram illustrating specific voltage ranges and multiple read voltage levels according to an exemplary embodiment of the present invention. Referring to FIG. 11, in an exemplary embodiment, after determining the specific voltage range 1010, assume that the read voltage level V is usedR(3)To read the first physical unit (i.e. read the voltage level V)R(3)A second read voltage level). In response to a read voltage level VR(3)Rather than being within a particular voltage range 1010, memory management circuit 502 may determine a read voltage level VR(3)The first condition is not met. In response to a read voltage level VR(3)Not complying with the first condition, the memory management circuit 502 may instruct the error checking and correcting circuit 508 to decode the reflective read voltage level V without referring to additional auxiliary informationR(3)The data of the read result (i.e., the second data).
Alternatively, in another exemplary embodiment, after determining the specific voltage range 1010, assume that the read voltage level V is usedR(4)To read the first physical unit (i.e. read the voltage level V)R(4)A second read voltage level). In response to a read voltage level VR(4)Within a specific voltage range 1010, the memory management circuit 502 can determine a read voltage level VR(4)The first condition is met. In response to a read voltage level VR(4)In compliance with the first condition, the memory management circuit 502 may instruct the error checking and correcting circuit 508 to decode the reflective read voltage level V with reference to additional auxiliary informationR(4)The data of the read result (i.e., the second data).
In an example embodiment, the memory management circuit 502 may obtain a syndrome value of the second data. The syndrome value is related to a bit error rate of the second data. For example, the memory management circuitry 502 (or the error checking and correcting circuitry 508) may perform a parity check operation on the second data to obtain a syndrome value of the second data. The memory management circuit 502 determines whether the second data meets the second condition according to whether the syndrome value is smaller than a predetermined value. For example, if the syndrome value is less than the predetermined value, the memory management circuit 502 may determine that the second data satisfies the second condition. If the syndrome value is not less than the predetermined value, the memory management circuit 502 can determine that the second data does not satisfy the second condition.
FIG. 12 is a diagram illustrating a parity check operation according to an exemplary embodiment of the present invention. Referring to fig. 12, in an exemplary embodiment, it is assumed that the second data comprises a codeword 1202. The codeword 1202 comprises a plurality of bits V0～V8. Memory management circuitry 502 (or error checking and correction circuitry 508) may multiply a matrix (also referred to as a parity check matrix, labeled H)1201 by codeword 1202 to obtain syndrome vector 1203. Syndrome vector 1203 includes a plurality of syndromes S0～S7. If there are no error bits in codeword 1202, syndrome S is checked0～S7Should be both bits "0". Syndrome S0～S7The more bits "1" in (or syndrome S)0～S7The fewer bits "0" in) indicating that the more erroneous bits are likely in codeword 1202.
In an example embodiment, the memory management circuit 502 may be based on the syndrome S0～S7The sum of (a) determines a syndrome value of the second data. For example, the syndrome value of the second data may reflect syndrome S0～S7The sum of (a) and (b). For example, the syndrome value of the second data may positively correlate to syndrome S0～S7The sum of (a) and (b). If the syndrome S0～S7The more bits "1" in (or syndrome S)0～S7The fewer bits "0") in the second data, the second data is obtainedThe larger the syndrome value of (a).
In an example embodiment, the memory management circuit 502 may update the boundary of the specific voltage range according to the second read voltage level to expand the coverage of the specific voltage range. In an example embodiment, the memory management circuit 502 may determine whether to update the boundary of the specific voltage range according to whether the second read voltage level is within the specific voltage range or the relative relationship between the remaining second read voltage levels and the specific voltage range. Therefore, the probability that the used reading voltage level meets the first condition in the hard bit decoding mode can be improved.
FIG. 13 is a diagram illustrating updating the boundary of a specific voltage range according to an exemplary embodiment of the invention. Referring to FIG. 13, assume that the read voltage level V isR(3)Not within a particular voltage range 1010. In using the read voltage level VR(3)After reading the first physical cell, the memory management circuit 502 can shift the boundary of the specific voltage range 1010 from the original corresponding to the read voltage level VR(1)Boundary 1010 updated to correspond to the read voltage level VR(3)To extend the coverage of the particular voltage range 1010.
In an example embodiment, after determining that the second read voltage level meets the first condition or the second data meets the second condition, the memory management circuit 502 may divide the voltage intervals according to a plurality of read voltage levels, such as the first read voltage level and the second read voltage level, at least partially used in the hard bit mode decoding. Then, the memory management circuit 502 may determine the auxiliary information according to the divided voltage intervals.
FIG. 14 is a diagram illustrating division of voltage intervals according to read voltage levels used in hard bit pattern decoding according to an exemplary embodiment of the present invention. Referring to FIG. 14, in an example embodiment, in response to a read voltage level VR(4)In accordance with a first condition, memory management circuit 502 may decode the read voltage level V according to a hard bit patternR(1)、VR(2)And VR(4)To divide the voltage intervals 1401-1404.
According to the read voltage level VR(1)、VR(2)And VR(4)The threshold voltage of each memory cell in the first physical cell can be identified as belonging to one of the voltage intervals 1401-1404 and assigned with corresponding reliability information. The side information may include reliability information obtained at this time. Taking a log-likelihood ratio (LLR) as an example of the reliability information, the more left the voltage interval corresponds to the smaller the value of the reliability information. Then, the error checking and correcting circuit 508 can use the corresponding reliability information (i.e., the auxiliary information) to decode the read voltage level V according to the voltage interval to which each memory cell belongsR(4)Data read from such memory cells.
In an exemplary embodiment, assume that a read voltage level V is usedR(1)The read data being third data, using a read voltage level VR(2)The read data is the first data, and the read voltage level V is usedR(4)The read data is the second data. The memory management circuit 502 may be configured to read the voltage level V according to a difference between the syndrome value of the third data and the syndrome value of the second dataR(1)And a read voltage level VR(4)The difference between the two values determines the reliability information corresponding to the voltage interval 1402. For example, the memory management circuit 502 may determine the reliability information corresponding to the voltage interval 1402 according to the following equation (1.1).
LLR(1402)＝α×(DIF(A)/DIF(B))+β×DIF(A)+γ×DIF(B)+C
Wherein DIF (A) corresponds to the difference between the syndrome value of the third data and the syndrome value of the second data, DIF (B) corresponds to the read voltage level VR(1)And a read voltage level VR(4)The difference between α, β, γ, and C are all constants similarly, memory management circuit 502 can be based on the difference between the syndrome value of the second data and the syndrome value of the first data and the read voltage level VR(4)And a read voltage level VR(2)The difference between the two values determines the reliability information corresponding to the voltage interval 1403. For exampleIn an exemplary embodiment, the reliability information corresponding to the voltage intervals 1401-1404 can be determined as "-1", "-0.2", "0.4", and "1", respectively.
FIG. 15 is a diagram illustrating division of voltage intervals according to read voltage levels used in hard bit pattern decoding according to an exemplary embodiment of the present invention. Referring to FIG. 15, continuing with the example embodiment of FIG. 14, if for the read voltage level VR(4)The decoding of the read data still fails, then the read voltage level V isR(5)May be subsequently used to read the first physical unit.
In an example embodiment, in response to a read voltage level VR(5)In accordance with a first condition, memory management circuit 502 may decode the read voltage level V according to a hard bit patternR(1)、VR(2)、VR(4)And VR(5)To divide the voltage intervals 1501-1505.
According to the read voltage level VR(1)、VR(2)、VR(4)And VR(5)The threshold voltage of each memory cell in the first physical cell can be identified as belonging to one of the voltage intervals 1501-1505 and is assigned with corresponding reliability information. The side information may include reliability information obtained at this time. Then, the error checking and correcting circuit 508 can use the corresponding reliability information (i.e., the auxiliary information) to decode the read voltage level V according to the voltage interval to which each memory cell belongsR(5)Data read from such memory cells.
In an example embodiment, the memory management circuit 502 may determine whether to decode the second data using the side information considering both that the second read voltage level satisfies the first condition and that the second data satisfies the second condition. In an example embodiment, the memory management circuit 502 may also determine whether to decode the second data using the auxiliary information according to whether the second read voltage level meets the first condition only or according to whether the second data meets the second condition only, depending on the practical requirements.
In the foregoing exemplary embodiments, the data reading of a single read voltage level is taken as an example for explanation. However, in the following exemplary embodiments, data reading of a plurality of read voltage levels is exemplified.
FIG. 16 is a graph illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode according to an exemplary embodiment of the present invention. Referring to FIG. 16, it is assumed that the threshold voltage distribution of the programmed memory cell in the first physical cell includes states 1601-1604. States 1601 and 1602 are adjacent and states 1603 and 1604 are adjacent. In the hard bit decoding mode, the read voltage level VR(1)And VR(1)', read voltage level VR(2)And VR(2)' or read voltage level VR(3)And VR(3)' may be simultaneously applied to the first physical unit to read the corresponding data. For example, a read voltage level VR(1)And VR(1)', read voltage level VR(2)And VR(2)' or read voltage level VR(3)And VR(3)' may correspond to any two read voltage levels (e.g., read voltage levels V1 and V2) in FIG. 7 that may be applied simultaneously.
In an example embodiment, the memory management circuit 502 may issue a read command sequence indicating that the read voltage level V is usedR(1)And VR(1)' reading a first physical cell to obtain a reflected read voltage level VR(1)And VR(1)' data of the read result. Error checking and correction circuitry 508 may decode this data. Assuming that the decoding of the data fails, the memory management circuit 502 may send a read command sequence indicating that the read voltage level V is usedR(2)And VR(2)' reading a first physical cell to obtain a reflected read voltage level VR(2)And VR(2)' data of the read result. Error checking and correction circuitry 508 may decode this data. Assuming that the decoding of the data fails, the memory management circuit 502 may send a read command sequence indicating that the read voltage level V is usedR(3)And VR(3)' reading a first physical cell to obtain a reflected read voltage level VR(3)And VR(3)' data of the read result.
FIG. 17 is a diagram illustrating specific voltage ranges and multiple read voltage levels according to an exemplary embodiment of the present invention. Referring to FIGS. 16 and 17, in an example embodiment, the memory management circuit 502 may be based on the read voltage level VR(1)And VR(2)Determining a specific voltage range 1710 and according to the read voltage level VR(1)' and VR(2)' determine a specific voltage range 1720.
As shown in FIG. 17, the read voltage level VR(3)And VR(3)' not in the specific voltage ranges 1710 and 1720, the memory management circuit 502 can determine the read voltage level VR(3)And VR(3)' the first condition is not met. In response to a read voltage level VR(3)And VR(3)' not meeting the first condition, reflecting the read voltage level V in decodingR(3)And VR(3)When reading the resulting data, the error checking and correcting circuit 508 will not use the auxiliary information.
Alternatively, memory management circuit 502 may be based on read voltage level VR(3)And VR(3)' the relative relationship between specific voltage ranges 1710 and 1720 determines whether to update the boundaries of specific voltage ranges 1710 and 1720. In an example embodiment, the memory management circuit 502 may be based on the read voltage level VR(3)And VR(3)’Whether to update the boundaries of the specific voltage ranges 1710 and 1720 is determined within the specific voltage ranges 1710 and 1720, respectively. The related operations may refer to the exemplary embodiment of fig. 13, and are not repeated herein.
In an example embodiment, the memory management circuit 502 may obtain the read voltage level VR(1)And VR(2)Difference D (1) between and read voltage level VR(1)' and VR(2)'difference between D (1)'. The memory management circuit 502 may obtain the read voltage level VR(1)And VR(3)Difference D (2) between and read voltage level VR(1)' and VR(3)'difference between D (2)'. The memory management circuit 502 can determine whether the sum of the differences D (2) and D (2) 'is greater than the sum of the differences D (1) and D (1)'. If the difference D: (2) The sum of D (2) 'is greater than the sum of the differences D (1) and D (1)', and the memory management circuit 502 can be based on the read voltage level VR(3)Updating the boundary 1712 of the specific voltage range 1710 and according to the read voltage level VR(3)' update the boundary 1722 of the particular voltage range 1720.
The memory management circuit 502 may obtain the read voltage level VR(2)And VR(3)Difference D (3) between and read voltage level VR(2)' and VR(3)'difference between D (3)'. The memory management circuit 502 can determine whether the sum of the differences D (3) and D (3) 'is greater than the sum of the differences D (1) and D (1)'. If the sum of the differences D (3) and D (3) 'is greater than the sum of the differences D (1) and D (1)', the memory management circuit 502 can be configured to read the voltage level V according to the read voltage levelR(3)Updating the boundary 1711 of the specific voltage range 1710 and according to the read voltage level VR(3)' update the boundary 1721 of the particular voltage range 1720.
As shown in FIG. 17, the sum of the differences D (2) and D (2) 'is not greater than the sum of the differences D (1) and D (1)' and the sum of the differences D (3) and D (3) 'is greater than the sum of the differences D (1) and D (1)', so that the memory management circuit 502 can be operated according to the read voltage level VR(3)Updating the boundary 1711 of the specific voltage range 1710 and according to the read voltage level VR(3)' update the boundary 1721 of the particular voltage range 1720. For example, the memory management circuit 502 can move the left boundary of a particular voltage range 1710 from corresponding to the read voltage level VR(1)Is updated to correspond to the boundary read voltage level VR(3)To extend the coverage of the particular voltage range 1710. At the same time, the memory management circuit 502 can move the left boundary of a particular voltage range 1720 from corresponding to the read voltage level VR(1)' boundary 1721 is updated to correspond to the boundary read voltage level VR(3)' 1723 to extend the coverage of the specific voltage range 1710.
FIG. 18 is a graph illustrating threshold voltage distributions and read voltage levels used in a hard bit decode mode according to an exemplary embodiment of the present invention. FIG. 19 shows specific voltage ranges and multiple read voltage levels according to an exemplary embodiment of the present inventionSchematic representation. Referring to fig. 18 and 19, the exemplary embodiment of fig. 18 and 19 is to read the voltage level V, compared to the exemplary embodiment of fig. 16 and 17R(4)And a read voltage level VR(4)Respectively replace the read voltage level VR(3)And a read voltage level VR(3)'. For example, a read voltage level VR(4)And VR(4)' may correspond to any two read voltage levels (e.g., read voltage levels V1 and V2) in FIG. 7 that may be applied simultaneously.
As shown in FIG. 19, the read voltage level VR(4)And VR(4)' in a specific voltage range 1910 and 1920, the memory management circuit 502 can determine the read voltage level VR(4)And VR(4)' the first condition is met. In response to a read voltage level VR(4)And VR(4)' in accordance with the first condition, the error checking and correcting circuit 508 can use the auxiliary information to decode the reflected read voltage level VR(3)And VR(3)' data of the read result. How to use the side information to perform the decoding operation in the hard bit pattern decoding is described in detail above, and is not repeated here.
Alternatively, memory management circuit 502 may be based on read voltage level VR(4)And VR(4)' relative relationship to the specific voltage ranges 1910 and 1920, whether the boundaries of the specific voltage ranges 1910 and 1920 are updated is determined. In an example embodiment, the memory management circuit 502 may be based on the read voltage level VR(4)And VR(4)' whether or not within the specific voltage ranges 1910 and 1920, respectively, it is determined whether or not to update the boundaries of the specific voltage ranges 1910 and 1920. The related operations may refer to the exemplary embodiment of fig. 13, and are not repeated herein.
In an example embodiment, the memory management circuit 502 may obtain the read voltage level VR(1)And VR(4)Difference D (4) between and read voltage level VR(1)' and VR(4)'difference between D (4)'. The memory management circuit 502 may determine whether the sum of the differences D (4) and D (4) 'is greater than the sum of the differences D (1) and D (1)'. If the sum of the differences D (4) and D (4) 'is greater than the sum of the differences D (1) and D (1)',the memory management circuit 502 may be based on a read voltage level VR(4)Updating the boundary 1912 of the particular voltage range 1910 and depending on the read voltage level VR(4)' update the boundary 1922 of the particular voltage range 1920.
The memory management circuit 502 may obtain the read voltage level VR(2)And VR(4)Difference D (5) between and read voltage level VR(2)' and VR(4)'difference between D (5)'. The memory management circuit 502 can determine whether the sum of the differences D (5) and D (5) 'is greater than the sum of the differences D (1) and D (1)'. If the sum of the differences D (5) and D (5) 'is greater than the sum of the differences D (1) and D (1)', the memory management circuit 502 can be configured to read the voltage level V according to the read voltage levelR(4)Updating the boundary 1911 of the specified voltage range 1910 and depending on the read voltage level VR(4)' update the boundary 1921 of the specific voltage range 1920.
As shown in fig. 19, the sum of the differences D (4) and D (4) 'is not greater than the sum of the differences D (1) and D (1)' and the sum of the differences D (5) and D (5) 'is not greater than the sum of the differences D (1) and D (1)', so that the memory management circuit 502 does not update the specific voltage ranges 1910 and 1920, thereby avoiding narrowing the coverage of the specific voltage ranges 1910 and 1920.
FIG. 20 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to FIG. 20, in step S2001, a first read command sequence is sent, which indicates to read a first physical cell using a first read voltage level to obtain first data. In step S2002, the first data is decoded. In step S2003, it is determined whether the decoding of the first data is successful. If the decoding of the first data is successful, in step S2004, the successfully decoded first data is output. If the decoding of the first data fails, in step S2005, a second read command sequence is sent, which indicates to read the first entity unit using the second read voltage level to obtain the second data. The second read voltage level is different from the first read voltage level.
In step S2006, it is determined whether the second read voltage level meets a first condition or whether the second data meets a second condition. If the second read voltage level meets the first condition or the second data meets the second condition, the second data is decoded using the auxiliary information in step S2007. The side information is used to improve a decoding success rate of the second data. If the second read voltage level does not meet the first condition and the second data does not meet the second condition, in step S2008, the second data is decoded without using the auxiliary information.
FIG. 21 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 21, in step S2101, hard bit mode decoding (also referred to as hard decoding mode) is initiated. In step S2102, a read instruction sequence is transmitted, which instructs to read the first entity unit to obtain data. This data may reflect the read result of the first physical cell using the read voltage. In step S2103, it is determined whether a preset condition is met or satisfied. For example, the predetermined condition may include whether the read voltage used satisfies a first condition and/or whether the read data satisfies a second condition. If the read voltage used meets the first condition and/or the read data meets the second condition, it can be determined that the predetermined condition is met or satisfied. If the used reading voltage does not meet the first condition and the read data does not meet the second condition, the preset condition can be judged to be not met or not met.
If the predetermined condition is met or satisfied, in step S2104, the read data is decoded using the auxiliary information. The side information is used to improve the decoding success rate of the data. If the predetermined condition is not met or not satisfied, in step S2105, the read data is decoded without using the auxiliary information. In step S2106, it is determined whether the decoding is successful. If the decoding is successful, in step S2107, the successfully decoded data is output. If the decoding is not successful, in step S2108, it is determined whether the number of decoding operations exceeds a retry threshold. If the number of decoding operations does not exceed the threshold, in step S2109, the next reading voltage level is adjusted and the process returns to step S2102, and the first physical unit is read again using the adjusted reading voltage level. If the number of decoding operations exceeds the retry threshold, step S2110 leaves the hard decoding mode and starts soft bit mode decoding (also called soft bit mode).
However, the steps in fig. 20 and 21 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 20 and fig. 21 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods shown in fig. 20 and fig. 21 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
As described above, in the hard bit pattern decoding, after at least one reading of the first physical unit and at least one decoding failure, the side information capable of improving the decoding success rate of the data is used only when a specific condition is satisfied, rather than unconditionally used in each re-reading and decoding. Therefore, the decoding success rate can be prevented from being reduced due to excessive use or adjustment of auxiliary information on the premise of trying to improve the decoding success rate of data in hard bit mode decoding.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A memory control method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, the memory control method comprising:
sending a first read command sequence instructing reading a first physical cell of the plurality of physical cells using a first read voltage level to obtain first data;
decoding the first data;
if the decoding of the first data fails, sending a second read command sequence indicating that a second read voltage level is used for reading the first entity unit to obtain second data, wherein the second read voltage level is different from the first read voltage level;
if the second read voltage level meets a first condition or the second data meets a second condition, decoding the second data by using auxiliary information, wherein the auxiliary information is used for improving the decoding success rate of the second data; and
decoding the second data without using the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
2. The memory control method of claim 1, further comprising:
and determining whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range.
3. The memory control method of claim 1, further comprising:
obtaining a syndrome value of the second data, wherein the syndrome value is related to a bit error rate of the second data; and
and determining whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
4. The memory control method of claim 1, further comprising:
prior to sending the first sequence of read instructions, sending a third sequence of read instructions that indicates to read the first physical unit using a third read voltage level to obtain third data;
decoding the third data; and
determining a specific voltage range according to the first read voltage level and the third read voltage level, wherein one of the first read voltage level and the third read voltage level is used for defining an upper boundary of the specific voltage range, and the other of the first read voltage level and the third read voltage level is used for defining a lower boundary of the specific voltage range.
5. The memory control method of claim 4, further comprising:
updating a boundary of the particular voltage range according to the second read voltage level.
6. The memory control method of claim 5, wherein the step of updating the boundary value of the particular voltage range according to the second read voltage level comprises:
and determining whether to update the boundary of the specific voltage range according to the relative relation between the second reading voltage level and the specific voltage range.
7. The memory control method of claim 1, further comprising:
if the second read voltage level meets the first condition or the second data meets the second condition, dividing a plurality of voltage intervals according to the first read voltage level and the second read voltage level; and
determining the auxiliary information according to the divided voltage intervals.
8. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity units; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is to send a first read command sequence instructing a first physical unit of the plurality of physical units to be read using a first read voltage level to obtain first data,
the memory control circuitry unit is also to decode the first data,
the memory control circuit unit is further configured to send a second read command sequence indicating to read the first physical unit using a second read voltage level to obtain second data if the decoding of the first data fails, wherein the second read voltage level is different from the first read voltage level,
the memory control circuit unit is further configured to decode the second data using auxiliary information if the second read voltage level meets a first condition or the second data meets a second condition, wherein the auxiliary information is configured to increase a decoding success rate of the second data, and
the memory control circuitry unit is further configured to decode the second data without using the assist information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
9. The memory storage device of claim 8, wherein the memory control circuitry unit is further configured to determine whether the second read voltage level meets the first condition based on whether the second read voltage level is within a particular voltage range.
10. The memory storage device of claim 8, wherein the memory control circuitry unit is further to obtain a syndrome value of the second data, the syndrome value being related to a bit error rate of the second data, and
the memory control circuit unit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
11. The memory storage device of claim 8, wherein prior to sending the first sequence of read instructions, the memory control circuitry unit is further to send a third sequence of read instructions that indicate to read the first physical unit using a third read voltage level to obtain third data,
the memory control circuit unit is further configured to decode the third data, an
The memory control circuit unit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level, wherein one of the first read voltage level and the third read voltage level is used to define an upper boundary of the specific voltage range, and the other of the first read voltage level and the third read voltage level is used to define a lower boundary of the specific voltage range.
12. The memory storage device of claim 11, wherein the memory control circuitry unit is also to update a boundary of the particular voltage range according to the second read voltage level.
13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit updating the boundary value of the particular voltage range according to the second read voltage level comprises:
and determining whether to update the boundary of the specific voltage range according to the relative relation between the second reading voltage level and the specific voltage range.
14. The memory storage device of claim 8, wherein the memory control circuitry unit is further configured to divide a plurality of voltage intervals according to the first read voltage level and the second read voltage level if the second read voltage level meets the first condition or the second data meets the second condition, and
the memory control circuit unit is further configured to determine the auxiliary information according to the divided voltage intervals.
15. A memory control circuit unit, configured to control a memory storage device, wherein the memory storage device includes a rewritable nonvolatile memory module, the rewritable nonvolatile memory module includes a plurality of physical units, and the memory control circuit unit includes:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module;
a decoding circuit; and
memory management circuitry connected to the host interface, the memory interface, and the decoding circuitry,
wherein the memory management circuit is to send a first read instruction sequence instructing a first physical cell of the plurality of physical cells to be read using a first read voltage level to obtain first data,
the decoding circuit is configured to decode the first data,
if the decoding of the first data fails, the memory management circuit is further configured to send a second read instruction sequence indicating that the first physical unit is read using a second read voltage level to obtain second data, wherein the second read voltage level is different from the first read voltage level,
the decoding circuit is further configured to decode the second data using auxiliary information if the second read voltage level meets a first condition or the second data meets a second condition, wherein the auxiliary information is used to increase a decoding success rate of the second data, and
the decoding circuit is further configured to decode the second data without using the assist information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
16. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to determine whether the second read voltage level meets the first condition based on whether the second read voltage level is within a certain voltage range.
17. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to obtain a syndrome value of the second data, the syndrome value being related to a bit error rate of the second data, and
the memory management circuit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is smaller than a preset value.
18. The memory control circuit unit of claim 15, wherein prior to sending the first sequence of read instructions, the memory management circuit is further to send a third sequence of read instructions that indicate to read the first physical unit using a third read voltage level to obtain third data,
the decoding circuit is further configured to decode the third data, an
The memory management circuit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level, wherein one of the first read voltage level and the third read voltage level is used to define an upper boundary of the specific voltage range, and the other of the first read voltage level and the third read voltage level is used to define a lower boundary of the specific voltage range.
19. The memory control circuitry unit of claim 18, wherein the memory management circuitry is also to update a boundary of the particular voltage range according to the second read voltage level.
20. The memory control circuit cell of claim 19, wherein the operation of the memory management circuit updating the boundary value of the particular voltage range according to the second read voltage level comprises:
and determining whether to update the boundary of the specific voltage range according to the relative relation between the second reading voltage level and the specific voltage range.
21. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to divide a plurality of voltage intervals according to the first read voltage level and the second read voltage level if the second read voltage level meets the first condition or the second data meets the second condition, and
the memory management circuit is further configured to determine the auxiliary information according to the divided voltage intervals.
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