CN111524876A - Semiconductor package with shielding structure and preparation method thereof - Google Patents
Semiconductor package with shielding structure and preparation method thereof Download PDFInfo
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- CN111524876A CN111524876A CN202010372693.2A CN202010372693A CN111524876A CN 111524876 A CN111524876 A CN 111524876A CN 202010372693 A CN202010372693 A CN 202010372693A CN 111524876 A CN111524876 A CN 111524876A
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- 238000002360 preparation method Methods 0.000 title abstract description 7
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- 239000011347 resin Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000002131 composite material Substances 0.000 claims abstract description 32
- 238000004806 packaging method and process Methods 0.000 claims abstract description 31
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- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 147
- 239000010949 copper Substances 0.000 claims description 126
- 229910052802 copper Inorganic materials 0.000 claims description 125
- 239000002070 nanowire Substances 0.000 claims description 125
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- 238000004528 spin coating Methods 0.000 claims description 82
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 71
- 229910021389 graphene Inorganic materials 0.000 claims description 71
- 239000007864 aqueous solution Substances 0.000 claims description 45
- 239000006185 dispersion Substances 0.000 claims description 45
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 claims description 42
- 238000010438 heat treatment Methods 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005507 spraying Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- 238000007788 roughening Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 77
- 229920000144 PEDOT:PSS Polymers 0.000 description 25
- 239000007788 liquid Substances 0.000 description 8
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
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Abstract
The invention relates to a semiconductor package with a shielding structure and a preparation method thereof, wherein the semiconductor package with the shielding structure comprises the following steps: the method comprises the steps of cutting a semiconductor wafer to form single semiconductor dies, arranging a plurality of semiconductor dies on a bearing substrate, depositing a dielectric material on the bearing substrate to form a dielectric layer, and sequentially forming a first composite shielding layer, a first resin packaging layer, a second composite shielding layer, a second resin packaging layer, a third composite shielding layer and a third resin packaging layer on the bearing substrate.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging with a shielding structure and a preparation method thereof.
Background
For the existing semiconductor package with the shielding structure, in the manufacturing process, a chip is usually disposed on a circuit substrate, and then the chip is wrapped by an encapsulant, and the shielding structure is disposed on the encapsulant; in another method, a chip is first disposed on a circuit substrate, then a metal filler is added to a resin material, and the circuit substrate and the chip are covered with the resin material having the metal filler to form an encapsulant, i.e., the encapsulant has an electromagnetic shielding effect. However, the conventional semiconductor package has the defects of poor electromagnetic shielding effect, peeling of the electromagnetic shielding layer and the like.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned shortcomings of the prior art and providing a semiconductor package having a shielding structure and a method for fabricating the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for manufacturing a semiconductor package with a shielding structure comprises the following steps:
1) providing a semiconductor wafer, cutting the semiconductor wafer to form single semiconductor dies, and forming inclined side faces on four sides of the semiconductor dies in the process of cutting the semiconductor wafer.
2) Providing a bearing substrate, and arranging a plurality of semiconductor dies on the bearing substrate.
3) The upper surfaces and the inclined side surfaces of the semiconductor dies are roughened, and then a dielectric material is deposited on the bearing substrate to form a dielectric layer, wherein the dielectric layer covers the upper surfaces and the inclined side surfaces of the chips.
4) And then spin-coating a first copper nanowire suspension on the bearing substrate, wherein the concentration of copper nanowires in the first copper nanowire suspension is 10-15mg/ml, then spin-coating a first graphene oxide dispersion on the bearing substrate, wherein the concentration of graphene oxide in the first graphene oxide dispersion is 3-6mg/ml, then spin-coating a first PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of PEDOT/PSS in the first PEDOT/PSS aqueous solution is 10-20mg/ml, and then performing first heat treatment to form a first composite shielding layer.
5) And then spraying a resin material on the bearing substrate to form a first resin packaging layer, wherein the thickness of the first resin packaging layer is 30-60 microns.
6) And then spin-coating a second copper nanowire suspension on the bearing substrate, wherein the concentration of the copper nanowires in the second copper nanowire suspension is 5-10mg/ml, then spin-coating a second graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the second graphene oxide dispersion is 2-4mg/ml, then spin-coating a second PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the second PEDOT: PSS aqueous solution is 5-15mg/ml, and then performing second heat treatment to form a second composite shielding layer.
7) And then spraying a resin material on the bearing substrate to form a second resin packaging layer, wherein the thickness of the second resin packaging layer is 50-100 microns.
8) And then spin-coating a third copper nanowire suspension on the bearing substrate, wherein the concentration of the copper nanowires in the third copper nanowire suspension is 20-30mg/ml, then spin-coating a third graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the third graphene oxide dispersion is 5-8mg/ml, then spin-coating a third PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the third PEDOT: PSS aqueous solution is 15-25mg/ml, and then carrying out third heat treatment to form a third composite shielding layer.
9) And then forming a third resin packaging layer on the bearing substrate.
Preferably, in the step 1), an included angle between the inclined side face of the semiconductor die and the bottom surface of the semiconductor die is 10-50 degrees.
Preferably, in the step 3), the dielectric material is one or more of zirconium oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the dielectric layer is formed by one or more of PECVD, thermal oxidation, ALD, or magnetron sputtering.
Preferably, in the step 4), the diameter of the copper nanowire in the first copper nanowire suspension is 50-100 nm, the length of the copper nanowire in the first copper nanowire suspension is 5-10 μm, the rotation speed of spin-coating the first copper nanowire suspension is 1500-.
Preferably, in the step 6), the diameter of the copper nanowire in the second copper nanowire suspension is 100-.
Preferably, in the step 8), the diameter of the copper nanowire in the third copper nanowire suspension is 30-80 nm, the length of the copper nanowire in the third copper nanowire suspension is 1-5 μm, the rotation speed of spin-coating the third copper nanowire suspension is 4000-.
The invention also provides a semiconductor package with the shielding structure, which is formed by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the existing semiconductor package, a single-layer electromagnetic shielding structure is usually arranged, on one hand, the single-layer electromagnetic shielding structure has a general electromagnetic shielding effect, and on the other hand, the electromagnetic shielding structure and the packaging layer are easy to delaminate and peel, so that the semiconductor package cannot be normally used. In the application, a composite shielding layer with copper nanowires, graphene oxide and PEDOT, PSS is formed, during the process of the composite shielding layer, a copper nanowire suspension is firstly spin-coated to form a copper nanowire layer on the upper surface and the side surface of a semiconductor tube core, then a graphene oxide dispersion liquid is spin-coated, during the spin-coating process, graphene oxide enters the copper nanowire layer, the copper nanowire layer is further enabled to be more tightly welded together under the action of the graphene oxide, then PEDOT, PSS aqueous solution is spin-coated on the bearing substrate, PEDOT, PSS polymer enters gaps between the copper nanowires and the graphene oxide, and an integrated composite shielding layer is further formed. The semiconductor package has excellent electromagnetic shielding effect by optimizing the number of layers of the composite shielding layers and arranging the resin packaging layers between the composite shielding layers and optimizing the preparation process of each functional layer, and the composite shielding layers and the resin packaging layers are well bonded together, so that the phenomena of layering and stripping are effectively inhibited.
Drawings
Fig. 1-2 are schematic structural diagrams of steps in the image sensor forming process of the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited to these terms. These terms are only used to distinguish the semiconductor chips from one another. For example, the first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, the second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of embodiments of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 2, the present embodiment provides a method for manufacturing a semiconductor package having a shielding structure, the method comprising the steps of:
as shown in fig. 1, step 1) is first performed to provide a semiconductor wafer, the semiconductor wafer is diced to form individual semiconductor dies, during the dicing of the semiconductor wafer, inclined side faces are formed on four sides of the semiconductor die 1, and in a specific embodiment, the semiconductor wafer is diced by a mechanical cutter or a laser to form the semiconductor die 1, wherein the semiconductor die 1 has an active surface therein, and the active surface contains analog or digital circuits of active devices, passive devices, conductive layers and dielectric layers which are electrically interconnected according to the actual required electrical design and function. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed in an active area of a semiconductor chip, and further, a pad, which is one or more layers of conductive material such as aluminum (Al), Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and is electrically connected to the circuit elements formed in the semiconductor chip, is also provided on the semiconductor die 1. In a specific embodiment, an included angle between the inclined side surface of the semiconductor die 1 and the lower surface of the semiconductor die is 10 to 50 degrees, and further preferably, an included angle between the inclined side surface of the semiconductor die 1 and the lower surface of the semiconductor die is 20 to 40 degrees, and specifically, an included angle between the inclined side surface of the semiconductor die 1 and the lower surface of the semiconductor die may be 30 degrees. The angle of the included angle is optimized to facilitate the subsequent attachment of functional layers to the semiconductor die 1.
Then, step 2) is performed, a carrier substrate 2 is provided, and a plurality of semiconductor dies 1 are disposed on the carrier substrate 2. The material of the bearing substrate 2 can include one of a PET plastic plate, toughened glass, a flexible resin plate, ceramics, sapphire and a semiconductor, and the semiconductor tube core is installed on the bearing substrate 2 in a mode that the active surface and the welding pad of the semiconductor tube core 1 face the bearing substrate 2. Then step 3) is carried out, roughening treatment is carried out on the upper surfaces and the inclined side surfaces of the plurality of semiconductor dies, so that the roughness of the side surfaces of the semiconductor dies 1 is larger than that of the upper surfaces of the semiconductor dies 1, and further, the adhesion of the inclined side surfaces of the semiconductor dies 1 during the formation of the dielectric layer can be increased, so that the thickness of the dielectric layer on the inclined side surfaces of the semiconductor dies 1 can be ensured to be consistent with that of the dielectric layer on the upper surfaces of the semiconductor dies 1, then, the dielectric material is deposited on the bearing substrate 2 to form the dielectric layer 3, the dielectric layer covers the upper surface and the inclined side surfaces of each chip, and in a specific embodiment, the dielectric layer can be formed by deposition of a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, a magnetron sputtering process, a thermal oxidation process or a, the dielectric layer is made of one or more of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide, and the thickness of the dielectric layer is 200-1000 nm, preferably 500-800 nm.
As shown in fig. 2, step 4) is then performed, a first copper nanowire suspension is spin-coated on the supporting substrate 2, wherein the concentration of copper nanowires in the first copper nanowire suspension is 10-15mg/ml, then a first graphene oxide dispersion is spin-coated on the supporting substrate, wherein the concentration of graphene oxide in the first graphene oxide dispersion is 3-6mg/ml, then a first PEDOT: PSS aqueous solution is spin-coated on the supporting substrate, wherein the concentration of PEDOT: PSS in the first PEDOT: PSS aqueous solution is 10-20mg/ml, then a first heat treatment is performed, so as to form the first composite shielding layer 4.
Wherein the diameter of the copper nanowire in the first copper nanowire suspension is 50-100 nanometers, the length of the copper nanowire in the first copper nanowire suspension is 5-10 micrometers, the rotation speed of spin-coating the first copper nanowire suspension is 1500-.
In a specific embodiment, a first copper nanowire suspension is spin-coated on the supporting substrate 2, wherein the concentration of the copper nanowire in the first copper nanowire suspension is preferably 12-15mg/ml, the diameter of the copper nanowire in the first copper nanowire suspension is 60-90 nm, the length of the copper nanowire in the first copper nanowire suspension is 6-9 μm, the rotation speed of the spin-coating of the first copper nanowire suspension is 1800-2200 rpm, the spin-coating time is 60-100 seconds, then a first graphene oxide dispersion is spin-coated on the supporting substrate, wherein the concentration of the graphene oxide in the first graphene oxide dispersion is 4-5mg/ml, the rotation speed of the spin-coating of the first graphene oxide dispersion is 2200-2800 rpm, and the spin-coating time is 80-120 seconds, and then spin-coating a first PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT/PSS in the first PEDOT/PSS aqueous solution is 12-18mg/ml, the rotation speed of the first PEDOT/PSS aqueous solution is 1800-2200 rpm, the spin-coating time is 60-100 seconds, and then performing first heat treatment, wherein the specific process of the first heat treatment is heat treatment at the temperature of 120-140 ℃ for 20-30 minutes to form a first composite shielding layer 4.
More specifically, a first copper nanowire suspension is spin-coated on the supporting substrate 2, wherein the concentration of the copper nanowires in the first copper nanowire suspension is preferably 13mg/ml, the diameter of the copper nanowires in the first copper nanowire suspension is 70-80 nm, the length of the copper nanowires in the first copper nanowire suspension is 6-9 μm, the rotation speed of the first copper nanowire suspension is 2000 rpm, the spin-coating time is 80 seconds, then a first graphene oxide dispersion is spin-coated on the supporting substrate, wherein the concentration of the graphene oxide in the first graphene oxide dispersion is 4.5mg/ml, the rotation speed of the first graphene oxide dispersion is 2500 rpm, the spin-coating time is 100 seconds, then a first PEDOT: PSS aqueous solution is spin-coated on the supporting substrate, the concentration of PEDOT and PSS in the first PEDOT and PSS aqueous solution is 15mg/ml, the rotating speed of the first PEDOT and PSS aqueous solution in a spin coating mode is 2000 r/min, the spin coating time is 100 seconds, and then first heat treatment is carried out, wherein the specific process of the first heat treatment is that heat treatment is carried out at 130 ℃ for 25 minutes, so that the first composite shielding layer 4 is formed.
And step 5) of spraying resin material on the bearing substrate 2 to form a first resin packaging layer 5, wherein the thickness of the first resin packaging layer 5 is 30-60 microns, and the first resin packaging layer 5 covers the first composite shielding layer 4.
In a specific embodiment, the sprayed resin material is one of epoxy resin, acrylic resin, silicone resin and polyester, and the thickness of the first resin encapsulation layer 5 is preferably 40-50 micrometers.
And then, performing step 6), spin-coating a second copper nanowire suspension on the bearing substrate 2, wherein the concentration of the copper nanowires in the second copper nanowire suspension is 5-10mg/ml, then spin-coating a second graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the second graphene oxide dispersion is 2-4mg/ml, then spin-coating a second PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the second PEDOT: PSS aqueous solution is 5-15mg/ml, and then performing second heat treatment to form a second composite shielding layer 6.
Wherein the diameter of the copper nanowire in the second copper nanowire suspension is 100-200 nm, the length of the copper nanowire in the second copper nanowire suspension is 10-15 microns, the rotation speed of the spin coating of the second copper nanowire suspension is 2500-3500 rpm, the rotation speed of the spin coating of the second graphene oxide dispersion is 3000-4000 rpm, the rotation speed of the spin coating of the second PEDOT, namely the rotation speed of the PSS aqueous solution is 2500-3500 rpm, and the specific process of the second heat treatment is heat treatment at 110-140 ℃ for 20-30 minutes.
In a specific embodiment, a second copper nanowire suspension is spin-coated on the supporting substrate 2, wherein the concentration of the copper nanowire in the second copper nanowire suspension is 6-8mg/ml, the diameter of the copper nanowire in the second copper nanowire suspension is 120-180 nm, the length of the copper nanowire in the second copper nanowire suspension is 12-15 μm, the rotation speed of the spin-coating of the second copper nanowire suspension is 2800-3200 rpm, and the spin-coating time is 80-120 seconds; then spin-coating a second graphene oxide dispersion liquid on the bearing substrate, wherein the concentration of graphene oxide in the second graphene oxide dispersion liquid is 3-4mg/ml, the rotation speed of the spin-coating of the second graphene oxide dispersion liquid is 3500-4000 rpm, and the spin-coating time is 100-200 seconds; and then spin-coating a second PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT/PSS in the second PEDOT/PSS aqueous solution is 7-12mg/ml, the rotation speed of the spin-coating of the second PEDOT/PSS aqueous solution is 2800-.
Specifically, a second copper nanowire suspension is spin-coated on the bearing substrate 2, wherein the concentration of the copper nanowire in the second copper nanowire suspension is 7mg/ml, the diameter of the copper nanowire in the second copper nanowire suspension is 150-180 nm, the length of the copper nanowire in the second copper nanowire suspension is 12-15 microns, the rotating speed of the spin-coating of the second copper nanowire suspension is 3000 r/min, and the spin-coating time is 100 seconds; then spin-coating a second graphene oxide dispersion liquid on the bearing substrate, wherein the concentration of graphene oxide in the second graphene oxide dispersion liquid is 3.5mg/ml, the rotation speed of the spin-coating of the second graphene oxide dispersion liquid is 3800 r/min, and the spin-coating time is 150 seconds; and then spin-coating a second PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT/PSS in the second PEDOT/PSS aqueous solution is 10mg/ml, the rotating speed of the spin-coating of the second PEDOT/PSS aqueous solution is 3000 r/min, the spin-coating time is 80 seconds, and then carrying out second heat treatment, wherein the specific process of the second heat treatment is heat treatment at 125 ℃ for 30 minutes to form a second composite shielding layer 6.
Then, step 7) is carried out, and then, a resin material is sprayed on the bearing substrate 2 to form a second resin packaging layer 7, wherein the thickness of the second resin packaging layer 7 is 50-100 microns.
In a specific embodiment, the sprayed resin material is one of epoxy resin, acrylic resin, silicone resin and polyester, and the thickness of the second resin encapsulation layer 7 is preferably 60-80 micrometers.
And then carrying out step 8), spin-coating a third copper nanowire suspension on the bearing substrate 2, wherein the concentration of the copper nanowires in the third copper nanowire suspension is 20-30mg/ml, then spin-coating a third graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the third graphene oxide dispersion is 5-8mg/ml, then spin-coating a third PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the third PEDOT: PSS aqueous solution is 15-25mg/ml, and then carrying out third heat treatment to form a third composite shielding layer 8.
Wherein the diameter of the copper nanowire in the third copper nanowire suspension is 30-80 nanometers, the length of the copper nanowire in the third copper nanowire suspension is 1-5 micrometers, the rotation speed of spin-coating the second copper nanowire suspension is 4000-.
In a specific embodiment, a third copper nanowire suspension is spin-coated on the supporting substrate 2, wherein the concentration of the copper nanowires in the third copper nanowire suspension is 24-28mg/ml, the diameter of the copper nanowires in the third copper nanowire suspension is 40-60 nm, the length of the copper nanowires in the third copper nanowire suspension is 2-3 μm, the rotation speed of the spin-coating of the third copper nanowire suspension is 4200 revolutions per minute and 4600 revolutions per minute, the spin-coating time is 1-2 minutes, then a third graphene oxide dispersion is spin-coated on the supporting substrate, wherein the concentration of the graphene oxide in the third graphene oxide dispersion is 6-7mg/ml, the rotation speed of the spin-coating of the third graphene oxide dispersion is 4200 revolutions per minute and 4800 revolutions per minute, the spin-coating time is 1-3 minutes, and then spin-coating a third PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT/PSS in the third PEDOT/PSS aqueous solution is 18-22mg/ml, the rotation speed of the spin-coating the third PEDOT/PSS aqueous solution is 3800-.
Specifically, a third copper nanowire suspension is spin-coated on the bearing substrate 2, wherein the concentration of the copper nanowire in the third copper nanowire suspension is 26mg/ml, the diameter of the copper nanowire in the third copper nanowire suspension is 50-60 nm, the length of the copper nanowire in the third copper nanowire suspension is 2-3 microns, the rotation speed of the third copper nanowire suspension is 4400 r/min, the spin-coating time is 2 minutes, then a third graphene oxide dispersion is spin-coated on the bearing substrate, wherein the concentration of the graphene oxide in the third graphene oxide dispersion is 6.5mg/ml, the rotation speed of the third graphene oxide dispersion is 4500 r/min, the spin-coating time is 2 minutes, then a third PEDOT: PSS aqueous solution is spin-coated on the bearing substrate, wherein the concentration of the PEDOT: PSS in the third PEDOT: PSS aqueous solution is 20mg/ml, and (3) spin-coating the third PEDOT, wherein the rotation speed of the PSS aqueous solution is 4000 revolutions per minute, the spin-coating time is 1 minute, and then, carrying out third heat treatment, wherein the specific process of the third heat treatment is that the third heat treatment is carried out for 20 minutes at 145 ℃ so as to form the third composite shielding layer 8.
Then, step 9) is performed, and a third resin encapsulation layer 9 is formed on the carrier substrate 1.
Specifically, the third resin encapsulation layer 9 may be formed by molding, printing, laminating, spin coating, or spray coating.
The invention also provides a semiconductor package with the shielding structure, which is formed by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the existing semiconductor package, a single-layer electromagnetic shielding structure is usually arranged, on one hand, the single-layer electromagnetic shielding structure has a general electromagnetic shielding effect, and on the other hand, the electromagnetic shielding structure and the packaging layer are easy to delaminate and peel, so that the semiconductor package cannot be normally used. In the application, a composite shielding layer with copper nanowires, graphene oxide and PEDOT, PSS is formed, during the process of the composite shielding layer, a copper nanowire suspension is firstly spin-coated to form a copper nanowire layer on the upper surface and the side surface of a semiconductor tube core, then a graphene oxide dispersion liquid is spin-coated, during the spin-coating process, graphene oxide enters the copper nanowire layer, the copper nanowire layer is further enabled to be more tightly welded together under the action of the graphene oxide, then PEDOT, PSS aqueous solution is spin-coated on the bearing substrate, PEDOT, PSS polymer enters gaps between the copper nanowires and the graphene oxide, and an integrated composite shielding layer is further formed. The semiconductor package has excellent electromagnetic shielding effect by optimizing the number of layers of the composite shielding layers and arranging the resin packaging layers between the composite shielding layers and optimizing the preparation process of each functional layer, and the composite shielding layers and the resin packaging layers are well bonded together, so that the phenomena of layering and stripping are effectively inhibited.
The invention also provides a preparation method of the semiconductor package with the shielding structure.
Item: a method for manufacturing a semiconductor package with a shielding structure comprises the following steps:
1) providing a semiconductor wafer, cutting the semiconductor wafer to form single semiconductor dies, and forming inclined side faces on four sides of the semiconductor dies in the process of cutting the semiconductor wafer.
2) Providing a bearing substrate, and arranging a plurality of semiconductor dies on the bearing substrate.
3) The upper surfaces and the inclined side surfaces of the semiconductor dies are roughened, and then a dielectric material is deposited on the bearing substrate to form a dielectric layer, wherein the dielectric layer covers the upper surfaces and the inclined side surfaces of the chips.
4) And then spin-coating a first copper nanowire suspension on the bearing substrate, wherein the concentration of copper nanowires in the first copper nanowire suspension is 10-15mg/ml, then spin-coating a first graphene oxide dispersion on the bearing substrate, wherein the concentration of graphene oxide in the first graphene oxide dispersion is 3-6mg/ml, then spin-coating a first PEDOT/PSS aqueous solution on the bearing substrate, wherein the concentration of PEDOT/PSS in the first PEDOT/PSS aqueous solution is 10-20mg/ml, and then performing first heat treatment to form a first composite shielding layer.
5) And then spraying a resin material on the bearing substrate to form a first resin packaging layer, wherein the thickness of the first resin packaging layer is 30-60 microns.
6) And then spin-coating a second copper nanowire suspension on the bearing substrate, wherein the concentration of the copper nanowires in the second copper nanowire suspension is 5-10mg/ml, then spin-coating a second graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the second graphene oxide dispersion is 2-4mg/ml, then spin-coating a second PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the second PEDOT: PSS aqueous solution is 5-15mg/ml, and then performing second heat treatment to form a second composite shielding layer.
7) And then spraying a resin material on the bearing substrate to form a second resin packaging layer, wherein the thickness of the second resin packaging layer is 50-100 microns.
8) And then spin-coating a third copper nanowire suspension on the bearing substrate, wherein the concentration of the copper nanowires in the third copper nanowire suspension is 20-30mg/ml, then spin-coating a third graphene oxide dispersion on the bearing substrate, wherein the concentration of the graphene oxide in the third graphene oxide dispersion is 5-8mg/ml, then spin-coating a third PEDOT: PSS aqueous solution on the bearing substrate, wherein the concentration of the PEDOT: PSS in the third PEDOT: PSS aqueous solution is 15-25mg/ml, and then carrying out third heat treatment to form a third composite shielding layer.
9) And then forming a third resin packaging layer on the bearing substrate.
Item 2: in the step 1), an included angle between the inclined side face of the semiconductor die and the bottom surface of the semiconductor die is 10-50 degrees.
Item 3: in the step 3), the dielectric material is one or more of zirconium oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the dielectric layer is formed by one or more of PECVD, thermal oxidation, ALD, or magnetron sputtering.
Item 4: in the step 4), the diameter of the copper nanowire in the first copper nanowire suspension is 50-100 nm, the length of the copper nanowire in the first copper nanowire suspension is 5-10 microns, the rotation speed of spin-coating the first copper nanowire suspension is 1500-.
Item 5: in the step 6), the diameter of the copper nanowire in the second copper nanowire suspension is 100-.
Item 6: in the step 8), the diameter of the copper nanowire in the third copper nanowire suspension is 30-80 nm, the length of the copper nanowire in the third copper nanowire suspension is 1-5 microns, the rotation speed of spin-coating the third copper nanowire suspension is 4000-.
Item 7: the invention also provides a semiconductor package with the shielding structure, which is formed by adopting the method.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (7)
1. A method for manufacturing a semiconductor package with a shielding structure is characterized in that: the method comprises the following steps:
1) providing a semiconductor wafer, cutting the semiconductor wafer to form single semiconductor dies, and forming inclined side faces on four sides of the semiconductor dies in the process of cutting the semiconductor wafer;
2) providing a bearing substrate, and arranging a plurality of semiconductor dies on the bearing substrate;
3) then carrying out roughening treatment on the upper surfaces and the inclined side faces of the semiconductor dies, and then depositing a dielectric material on the bearing substrate to form a dielectric layer, wherein the dielectric layer covers the upper surfaces and the inclined side faces of each chip;
4) then spin-coating a first copper nanowire suspension on the bearing substrate, wherein the concentration of copper nanowires in the first copper nanowire suspension is 10-15mg/ml, then spin-coating a first graphene oxide dispersion on the bearing substrate, wherein the concentration of graphene oxide in the first graphene oxide dispersion is 3-6mg/ml, then spin-coating a first PEDOT, PSS aqueous solution on the bearing substrate, wherein the concentration of PEDOT, PSS in the first PEDOT, PSS aqueous solution is 10-20mg/ml, and then performing first heat treatment to form a first composite shielding layer;
5) then spraying a resin material on the bearing substrate to form a first resin packaging layer, wherein the thickness of the first resin packaging layer is 30-60 microns;
6) then spin-coating a second copper nanowire suspension on the bearing substrate, wherein the concentration of copper nanowires in the second copper nanowire suspension is 5-10mg/ml, then spin-coating a second graphene oxide dispersion on the bearing substrate, wherein the concentration of graphene oxide in the second graphene oxide dispersion is 2-4mg/ml, then spin-coating a second PEDOT, PSS aqueous solution on the bearing substrate, wherein the concentration of PEDOT, PSS in the second PEDOT, PSS aqueous solution is 5-15mg/ml, and then performing second heat treatment to form a second composite shielding layer;
7) then spraying a resin material on the bearing substrate to form a second resin packaging layer, wherein the thickness of the second resin packaging layer is 50-100 microns;
8) then spin-coating a third copper nanowire suspension on the bearing substrate, wherein the concentration of copper nanowires in the third copper nanowire suspension is 20-30mg/ml, then spin-coating a third graphene oxide dispersion on the bearing substrate, wherein the concentration of graphene oxide in the third graphene oxide dispersion is 5-8mg/ml, then spin-coating a third PEDOT, PSS aqueous solution, wherein the concentration of PEDOT, PSS in the third PEDOT, PSS aqueous solution is 15-25mg/ml, and then performing third heat treatment to form a third composite shielding layer;
9) and then forming a third resin packaging layer on the bearing substrate.
2. The method for manufacturing a semiconductor package with a shielding structure according to claim 1, wherein: in the step 1), an included angle between the inclined side face of the semiconductor die and the bottom surface of the semiconductor die is 10-50 degrees.
3. The method for manufacturing a semiconductor package with a shielding structure according to claim 1, wherein: in the step 3), the dielectric material is one or more of zirconium oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the dielectric layer is formed by one or more of PECVD, thermal oxidation, ALD, or magnetron sputtering.
4. The method for manufacturing a semiconductor package with a shielding structure according to claim 1, wherein: in the step 4), the diameter of the copper nanowire in the first copper nanowire suspension is 50-100 nm, the length of the copper nanowire in the first copper nanowire suspension is 5-10 microns, the rotation speed of spin-coating the first copper nanowire suspension is 1500-.
5. The method for manufacturing a semiconductor package with a shielding structure according to claim 1, wherein: in the step 6), the diameter of the copper nanowire in the second copper nanowire suspension is 100-.
6. The method for manufacturing a semiconductor package with a shielding structure according to claim 1, wherein: in the step 8), the diameter of the copper nanowire in the third copper nanowire suspension is 30-80 nm, the length of the copper nanowire in the third copper nanowire suspension is 1-5 microns, the rotation speed of spin-coating the third copper nanowire suspension is 4000-.
7. A semiconductor package having a shielding structure, characterized by being formed by the method of any one of claims 1-6.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090256244A1 (en) * | 2008-02-05 | 2009-10-15 | Kuo-Hsien Liao | Semiconductor device packages with electromagnetic interference shielding |
| KR20160006313A (en) * | 2014-07-08 | 2016-01-19 | 백철균 | Electrical and electronic parts of the non-conductive electromagnetic shielding material composition and the manufacturing method of the composition |
| US20170179098A1 (en) * | 2015-12-18 | 2017-06-22 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor package |
| CN108034313A (en) * | 2017-12-08 | 2018-05-15 | 中车青岛四方机车车辆股份有限公司 | A kind of electromagnetic screen coating and its preparation method and application |
| CN108292645A (en) * | 2015-12-22 | 2018-07-17 | 英特尔公司 | Semiconductor packages with the electromagnetic interference shield moulded based on groove |
| CN109920779A (en) * | 2019-03-19 | 2019-06-21 | 吴静雯 | A kind of preparation method and encapsulating products of encapsulating products electro-magnetic screen layer |
| KR20190089246A (en) * | 2018-01-22 | 2019-07-31 | 신동혁 | Package EMI for Semiconductor |
| CN110246829A (en) * | 2018-03-09 | 2019-09-17 | 三星电子株式会社 | Semiconductor package part and semiconductor module |
-
2020
- 2020-05-06 CN CN202010372693.2A patent/CN111524876A/en not_active Withdrawn
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090256244A1 (en) * | 2008-02-05 | 2009-10-15 | Kuo-Hsien Liao | Semiconductor device packages with electromagnetic interference shielding |
| KR20160006313A (en) * | 2014-07-08 | 2016-01-19 | 백철균 | Electrical and electronic parts of the non-conductive electromagnetic shielding material composition and the manufacturing method of the composition |
| US20170179098A1 (en) * | 2015-12-18 | 2017-06-22 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor package |
| CN108292645A (en) * | 2015-12-22 | 2018-07-17 | 英特尔公司 | Semiconductor packages with the electromagnetic interference shield moulded based on groove |
| CN108034313A (en) * | 2017-12-08 | 2018-05-15 | 中车青岛四方机车车辆股份有限公司 | A kind of electromagnetic screen coating and its preparation method and application |
| KR20190089246A (en) * | 2018-01-22 | 2019-07-31 | 신동혁 | Package EMI for Semiconductor |
| CN110246829A (en) * | 2018-03-09 | 2019-09-17 | 三星电子株式会社 | Semiconductor package part and semiconductor module |
| CN109920779A (en) * | 2019-03-19 | 2019-06-21 | 吴静雯 | A kind of preparation method and encapsulating products of encapsulating products electro-magnetic screen layer |
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