CN111512291B - 基于服务质量底限调度存储器带宽 - Google Patents

基于服务质量底限调度存储器带宽 Download PDF

Info

Publication number
CN111512291B
CN111512291B CN201880082739.8A CN201880082739A CN111512291B CN 111512291 B CN111512291 B CN 111512291B CN 201880082739 A CN201880082739 A CN 201880082739A CN 111512291 B CN111512291 B CN 111512291B
Authority
CN
China
Prior art keywords
nls
scheduler
processor
memory bandwidth
latency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880082739.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN111512291A (zh
Inventor
道格拉斯·班森·亨特
杰伊·弗莱施曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN111512291A publication Critical patent/CN111512291A/zh
Application granted granted Critical
Publication of CN111512291B publication Critical patent/CN111512291B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88Monitoring involving counting
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/48Indexing scheme relating to G06F9/48
    • G06F2209/485Resource constraint
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62Details of cache specific to multiprocessor cache arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/08Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852Delays

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201880082739.8A 2017-12-20 2018-09-18 基于服务质量底限调度存储器带宽 Active CN111512291B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/849,266 US10700954B2 (en) 2017-12-20 2017-12-20 Scheduling memory bandwidth based on quality of service floorbackground
US15/849,266 2017-12-20
PCT/US2018/051593 WO2019125557A1 (en) 2017-12-20 2018-09-18 Scheduling memory bandwidth based on quality of service floorbackground

Publications (2)

Publication Number Publication Date
CN111512291A CN111512291A (zh) 2020-08-07
CN111512291B true CN111512291B (zh) 2024-06-18

Family

ID=66816568

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880082739.8A Active CN111512291B (zh) 2017-12-20 2018-09-18 基于服务质量底限调度存储器带宽

Country Status (6)

Country Link
US (1) US10700954B2 (enExample)
EP (1) EP3729282A4 (enExample)
JP (1) JP7109549B2 (enExample)
KR (1) KR102430934B1 (enExample)
CN (1) CN111512291B (enExample)
WO (1) WO2019125557A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11561834B2 (en) * 2019-01-16 2023-01-24 Rambus Inc. Methods and systems for adaptive memory-resource management
US11314558B2 (en) * 2019-07-23 2022-04-26 Netapp, Inc. Methods for dynamic throttling to satisfy minimum throughput service level objectives and devices thereof
US11169812B2 (en) 2019-09-26 2021-11-09 Advanced Micro Devices, Inc. Throttling while managing upstream resources
CN111444012B (zh) * 2020-03-03 2023-05-30 中国科学院计算技术研究所 一种保证延迟敏感应用延迟slo的动态调控资源方法及系统
JP2021170241A (ja) * 2020-04-16 2021-10-28 富士通株式会社 情報処理装置及び制御プログラム
US12112212B2 (en) * 2021-02-26 2024-10-08 Google Llc Controlling system load based on memory bandwidth
US12436586B2 (en) * 2023-08-04 2025-10-07 Apple Inc. Quality-of-service-based fabric power management
CN117216003B (zh) * 2023-09-27 2025-12-19 苏州元脑智能科技有限公司 为进程数据生成快照的方法、系统、终端及存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101896886A (zh) * 2007-10-31 2010-11-24 艾科立方公司 单个计算机系统上运行的多个内核之间的一致同步
CN102473137A (zh) * 2009-07-23 2012-05-23 英派尔科技开发有限公司 线程节流

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060004983A1 (en) * 2004-06-30 2006-01-05 Tsao Gary Y Method, system, and program for managing memory options for devices
US8230069B2 (en) * 2008-03-04 2012-07-24 International Business Machines Corporation Server and storage-aware method for selecting virtual machine migration targets
WO2010095182A1 (ja) 2009-02-17 2010-08-26 パナソニック株式会社 マルチスレッドプロセッサ及びデジタルテレビシステム
JP5803408B2 (ja) * 2011-08-11 2015-11-04 富士通株式会社 通信方法及び情報処理システム
US8705307B2 (en) * 2011-11-17 2014-04-22 International Business Machines Corporation Memory system with dynamic refreshing
WO2013101139A1 (en) * 2011-12-30 2013-07-04 Intel Corporation Providing an asymmetric multicore processor system transparently to an operating system
US8775762B2 (en) 2012-05-07 2014-07-08 Advanced Micro Devices, Inc. Method and apparatus for batching memory requests
US9021493B2 (en) 2012-09-14 2015-04-28 International Business Machines Corporation Management of resources within a computing environment
US9116738B2 (en) 2012-11-13 2015-08-25 International Business Machines Corporation Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system
US9535860B2 (en) 2013-01-17 2017-01-03 Intel Corporation Arbitrating memory accesses via a shared memory fabric
US9483423B2 (en) 2013-05-17 2016-11-01 Nvidia Corporation Techniques for assigning priorities to memory copies
US9489321B2 (en) 2013-06-13 2016-11-08 Advanced Micro Devices, Inc. Scheduling memory accesses using an efficient row burst value
WO2015130291A1 (en) 2014-02-27 2015-09-03 Empire Technology Development, Llc Thread and data assignment in multi-core processors
US9563369B2 (en) * 2014-04-14 2017-02-07 Microsoft Technology Licensing, Llc Fine-grained bandwidth provisioning in a memory controller
US9424092B2 (en) * 2014-09-26 2016-08-23 Microsoft Technology Licensing, Llc Heterogeneous thread scheduling
US9921866B2 (en) * 2014-12-22 2018-03-20 Intel Corporation CPU overprovisioning and cloud compute workload scheduling mechanism
US9645935B2 (en) 2015-01-13 2017-05-09 International Business Machines Corporation Intelligent bandwidth shifting mechanism
US10210023B2 (en) 2016-04-05 2019-02-19 Netapp, Inc. Methods and systems for managing service level objectives in a networked storage environment
US10387099B2 (en) * 2016-07-28 2019-08-20 Intelligent Waves Llc System, method and computer program product for generating remote views in a virtual mobile device platform using efficient color space conversion and frame encoding
US10185659B2 (en) * 2016-12-09 2019-01-22 Cray, Inc. Memory allocation system for multi-tier memory
US10776309B2 (en) * 2016-12-31 2020-09-15 Intel Corporation Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101896886A (zh) * 2007-10-31 2010-11-24 艾科立方公司 单个计算机系统上运行的多个内核之间的一致同步
CN102473137A (zh) * 2009-07-23 2012-05-23 英派尔科技开发有限公司 线程节流

Also Published As

Publication number Publication date
JP7109549B2 (ja) 2022-07-29
EP3729282A4 (en) 2021-05-05
US20190190805A1 (en) 2019-06-20
US10700954B2 (en) 2020-06-30
EP3729282A1 (en) 2020-10-28
WO2019125557A1 (en) 2019-06-27
CN111512291A (zh) 2020-08-07
KR102430934B1 (ko) 2022-08-08
KR20200090957A (ko) 2020-07-29
JP2021508108A (ja) 2021-02-25

Similar Documents

Publication Publication Date Title
CN111512291B (zh) 基于服务质量底限调度存储器带宽
Tavakkol et al. FLIN: Enabling fairness and enhancing performance in modern NVMe solid state drives
EP3447607B1 (en) Credit based command scheduling
JP6381956B2 (ja) 動的仮想マシンサイジング
JP5332065B2 (ja) クラスタ構成管理方法、管理装置及びプログラム
US10255217B2 (en) Two level QoS scheduling for latency and queue depth control
JP5075274B2 (ja) 電力認識スレッドスケジューリングおよびプロセッサーの動的使用
US8028286B2 (en) Methods and apparatus for scheduling threads on multicore processors under fair distribution of cache and other shared resources of the processors
CN111177984B (zh) 电子设计自动化中异构计算单元的资源利用
CN112513821B (zh) 用于scm应用的多实例2lm架构
EP3543852B1 (en) Systems and methods for variable rate limiting of shared resource access
KR102756802B1 (ko) 멀티-코어 시스템 및 그 동작 제어 방법
US20200065150A1 (en) Allocating Resources of a Memory Fabric
CN114564300A (zh) 用于动态分派内存带宽的方法
JP2012133630A (ja) ストレージリソース制御システムおよびストレージリソース制御プログラムならびにストレージリソース制御方法
CN115129465A (zh) 用于运行计算单元的方法
KR101924467B1 (ko) 가상 머신의 cpu 및 블록 i/o 작업에 성능 보장을 위한 자원 할당 시스템 및 방법
CN119522407A (zh) 任务调度装置、计算系统、任务调度方法以及程序
EP4621530A1 (en) Frequency scaling method and apparatus, and processor, chip and computer device
US9389919B2 (en) Managing workload distribution among computer systems based on intersection of throughput and latency models
Hua et al. RuYi: Optimizing Burst Buffer Through Automated, Fine-Grained Process-to-BB Mapping
Di et al. Optimization and stabilization of composite service processing in a cloud system
KR101743028B1 (ko) 가상화 환경에서 네트워크 성능 차등화를 위한 동적 자원 할당 장치 및 방법
CN119668792A (zh) 动态功率感知工作负载调度器
Mishra Temperature Aware Scheduling in Multicore Systems

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant