CN111509974A - Method and circuit for controlling stability of PWM loop and DC-DC converter - Google Patents

Method and circuit for controlling stability of PWM loop and DC-DC converter Download PDF

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Publication number
CN111509974A
CN111509974A CN201910098467.7A CN201910098467A CN111509974A CN 111509974 A CN111509974 A CN 111509974A CN 201910098467 A CN201910098467 A CN 201910098467A CN 111509974 A CN111509974 A CN 111509974A
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voltage
pwm
clamping
circuit
loop
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CN111509974B (en
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吴金
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Actions Zhuhai Technology Co ltd
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Actions Zhuhai Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0016—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters
    • H02M1/0022—Control circuits providing compensation of output voltage deviations using feedforward of disturbance parameters the disturbance parameters being input voltage fluctuations

Abstract

The invention relates to the technical field of direct current converters, and discloses a method and a circuit for controlling stability of a PWM loop and a DC-DC converter, wherein the method comprises the following steps: obtaining a stable working voltage of a PWM loop according to the input voltage and the output voltage of the DC-DC converter; clamping the output voltage of an error amplifier to the stable working voltage of the PWM loop, wherein the error amplifier belongs to the PWM loop; by the circuit for carrying out self-adaptive clamping on the output voltage of the error amplifier, the PFM/PWM mode is rapidly switched, the drop amplitude of the output voltage is effectively reduced, and the suppression performance of a system on the input and output voltage disturbance is improved.

Description

Method and circuit for controlling stability of PWM loop and DC-DC converter
Technical Field
The invention relates to the technical field of direct current converters, in particular to a method and a circuit for controlling stability of a PWM loop and a DC-DC converter.
Background
With the development of an Internet of Things platform, various electronic products based on an Internet of Things (IOT) technology have higher requirements on the performance of a power chip supplying power to the electronic products, wherein key performance includes extremely low static power consumption, low ripple, a wide voltage range, high conversion efficiency and the like.
In the prior art, a method for performing fixed voltage bias on the output voltage of an error amplifier is adopted, but the transient performance of a pulse width modulation (PFM) switching Pulse Width Modulation (PWM) mode cannot be effectively improved, and the influence of the input voltage on a PWM loop cannot be improved in the PWM mode; there is also a method of using input voltage feed-forward in the PWM loop, but the response speed of PFM/PWM mode switching and the droop of the output voltage cannot be effectively improved.
Disclosure of Invention
The invention mainly aims to provide a method and a circuit for controlling the stability of a PWM loop and a DC-DC converter, which realize the fast switching of a PFM/PWM mode and effectively reduce the drop amplitude of output voltage through a circuit for carrying out self-adaptive clamping on the output voltage of an error amplifier, and simultaneously improve the inhibition performance of a system on the disturbance of the input and output voltages.
In order to achieve the above object, the present invention provides a method for controlling PWM loop stability, including:
obtaining a stable working voltage of a PWM loop according to the input voltage and the output voltage of the DC-DC converter;
and clamping the output voltage of an error amplifier to the stable working voltage of the PWM loop, wherein the error amplifier belongs to the PWM loop.
Optionally, the method further comprises:
obtaining a voltage threshold interval according to the input voltage and the output voltage of the DC-DC converter,
and monitoring whether the output voltage of the error amplifier is in the voltage threshold interval, and judging whether clamping is carried out according to the monitoring result.
Optionally, the clamping the output voltage of the error amplifier to the PWM loop stable operating voltage comprises:
sampling the stable working voltage of the PWM loop, and obtaining a sampling holding voltage through sampling holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
Optionally, if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, receiving a pre-trigger signal when the DC-DC converter jumps from a light load to a heavy load;
and when the output voltage of the error amplifier is clamped to the stable PWM working voltage, a mode feedback signal is sent, and the working mode control module generates a first mode switching signal according to the mode feedback signal so as to switch from the PFM working mode to the PWM working mode.
Optionally, the DC-DC converter further includes, after switching from the PFM operation mode to the PWM operation mode:
when the DC-DC converter jumps from a heavy load to a light load, the working mode control module generates a second mode switching control signal to switch from a PWM working mode to a PFM working mode.
As still another aspect of the present invention, there is provided a circuit for controlling stability of a PWM loop, including:
an error amplifier and a clamp for clamping an output voltage of the error amplifier to a PWM loop stable operating voltage, the error amplifier belonging to a PWM loop, the clamp comprising: and the voltage generating circuit is used for generating the stable working voltage of the PWM loop according to the input voltage and the output voltage of the DC-DC converter.
Optionally, the clamp circuit further comprises: the sampling, holding and outputting module is used for sampling the stable working voltage of the PWM loop and obtaining a sampling and holding voltage through sampling and holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
Optionally, the voltage generation circuit is further configured to obtain a voltage threshold interval according to an input voltage and an output voltage of the DC-DC converter.
Optionally, the clamp circuit further comprises: the clamping precision control circuit comprises a clamping precision monitoring module and a clamping control module, wherein the clamping precision monitoring module is used for monitoring whether the output voltage of the error amplifier is within the voltage threshold range, and the clamping control module is used for generating a clamping control signal according to a monitoring result so as to determine whether to clamp or not.
Optionally, if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, the circuit for controlling stability of the PWM loop further includes: the working mode control module is used for generating a pre-trigger signal and receiving a mode feedback signal; and the clamping control module is used for generating the mode feedback signal and the clamping control signal according to the monitoring result and the pre-trigger signal.
Optionally, the sample-hold-and-output module comprises: the PWM stable working voltage detection circuit comprises a sample-hold switch, a sampling capacitor, a clamping switch and a voltage cache unit, wherein one end of the sample-hold switch is used for inputting the PWM stable working voltage, the sample-hold switch is controlled by the first clock signal, the other end of the sample-hold switch is connected with one end of the sampling capacitor and a positive input end of the voltage cache unit, the other end of the sampling capacitor is grounded, an output end of the voltage cache unit is connected with a negative input end of the voltage cache unit and one end of the clamping switch, and the other end of the clamping switch is connected with an output end of the error amplifier.
Optionally, the voltage generation circuit includes a voltage-to-current conversion circuit, a first current source, a second current source, a comparator, a first switch, a second switch, a first capacitor, a second capacitor, and a third switch, an input end of the voltage-to-current conversion circuit is used for inputting an input voltage of the DC-DC converter, an output end of the voltage-to-current conversion circuit is connected to the first current source, an output end of the first current source is connected to one end of the first capacitor, one end of the first switch, and a positive input end of the comparator, the other end of the first capacitor is grounded together with the other end of the first switch, a negative input end of the comparator is used for inputting β times of an output voltage of the DC-DC converter, a control end of the comparator is used for inputting a reverse clock signal, the first switch and the second switch are controlled by a clock signal, an output signal of the comparator is used for controlling the third switch, one end of the third switch is connected to one end of the second capacitor and one end of the second switch, the other end of the second capacitor is grounded together with the other end of the second switch, and the other end of the third switch is connected to an input end of the second switch, and the second switch is used for inputting an input voltage of.
Optionally, the voltage generation circuit further comprises: a voltage conversion circuit, the voltage conversion circuit comprising: the positive input end of the operational amplifier is connected with the output end of the second current source, the output end of the operational amplifier is connected with the grid electrode of the PMOS tube, the source electrode of the PMOS tube is used for inputting the input voltage of the DC-DC converter, the drain electrode of the PMOS tube is grounded after being connected with the first variable resistor string and the second variable resistor string in series, the voltage of the connection point of the first variable resistor string and the second variable resistor string is the PWM stable working voltage, the negative input end of the operational amplifier is connected with the connection point, the output end of the first variable resistor string is used for outputting the high voltage threshold value of the voltage threshold value interval, and the output end of the second variable resistor string is used for outputting the low voltage threshold value of the voltage threshold value interval.
Optionally, the clamping accuracy monitoring module includes: the positive input end of the first comparator is used for inputting a high voltage threshold value of the voltage threshold interval, the positive input end of the second comparator is used for inputting a low voltage threshold value of the voltage threshold interval, the negative input ends of the first comparator and the second comparator are both used for inputting the output voltage of the error amplifier, the output ends of the first comparator and the second comparator are respectively connected with two input ends of the exclusive-or gate, and the output end of the exclusive-or gate is connected with the clamping control module;
alternatively, the first and second electrodes may be,
the clamping accuracy monitoring module comprises: a third current source, a fourth current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, and a second resistor, wherein input terminals of the third current source and the fourth current source are used for inputting an input voltage of the DC-DC converter, an output terminal of the third current source is connected to source terminals of the first PMOS transistor and the second PMOS transistor, a gate of the first PMOS transistor is used for inputting a low voltage threshold of the voltage threshold interval, a drain of the first PMOS transistor and a drain of the third PMOS transistor are connected to one end of the first resistor and the clamp control module, the other end of the first resistor is grounded, a gate of the second PMOS transistor and a gate of the third PMOS transistor are used for inputting an output voltage of the error amplifier, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, the output end of the fourth current source is connected with the source electrodes of the third PMOS tube and the fourth PMOS tube respectively, and the grid electrode of the fourth PMOS tube is used for inputting the high voltage threshold value of the voltage threshold value interval.
Optionally, the clamping control module comprises: a NAND gate, a D trigger and a delay unit, wherein the first input end of the NAND gate is connected with the output end of the clamping precision monitoring module, the second input terminal of the nand gate is used for inputting high level when the PWM loop belongs to the PWM single-mode control loop, the second input end of the NAND gate is used for inputting the pre-trigger signal when the PWM loop belongs to a PFM/PWM dual-mode control loop, the output end of the NAND gate is connected with the reset end of the D flip-flop, the D end of the D flip-flop is used for inputting high level, the clock end of the D trigger is used for inputting a second clock signal, the Q end of the D trigger is connected with the input end of the delay unit, the output end of the delay unit is used for outputting the clamping switch control signal, when the PWM loop belongs to a PWM/PFM dual-mode control loop, the Q non-end of the D trigger is used for outputting the mode feedback signal.
Optionally, the operating mode control module is connected to the clamp circuit, and configured to send a pre-trigger signal to the clamp circuit when a system jumps from a light load to a heavy load, and receive a mode feedback signal sent by the clamp circuit when an output voltage of the error amplifier is clamped to a stable operating voltage of the PWM loop, and generate a corresponding mode switching control signal based on the mode feedback signal, and the operating mode control module is connected to the control logic and driving module of the DC-DC converter, and configured to transmit the mode switching control signal to the control logic and driving module, and the control logic and driving module is connected to the PWM/PFM dual-mode control loop, and configured to perform mode switching on the PWM/PFM dual-mode control loop after receiving the mode switching control signal.
As a further aspect of the present invention, a DC-DC converter is provided, which includes the above-mentioned circuit for controlling the stability of the PWM loop, and further includes a control logic and driving module, a first MOS transistor, a second MOS transistor, an off-chip filter inductor, and a capacitor.
The invention provides a method and a circuit for controlling stability of a PWM loop and a DC-DC converter, wherein the method comprises the following steps: obtaining a stable working voltage of a PWM loop according to the input voltage and the output voltage of the DC-DC converter; clamping the output voltage of an error amplifier to the stable working voltage of the PWM loop, wherein the error amplifier belongs to the PWM loop; by the circuit for carrying out self-adaptive clamping on the output voltage of the error amplifier, the suppression performance of a system on the input and output voltage disturbance is improved, and meanwhile, the PFM/PWM mode is facilitated to be rapidly switched, and the output voltage drop amplitude is effectively reduced.
Drawings
Fig. 1 is a flowchart of a method for controlling PWM loop stability according to an embodiment of the present invention;
fig. 2 is a flowchart of another method for controlling PWM loop stability according to a first embodiment of the present invention;
fig. 3 is a circuit diagram of an adaptive clamp circuit according to an embodiment of the present invention;
fig. 4 is a schematic system structure diagram of a PWM/PFM dual-mode modulation DC-DC converter based on an error amplifier output voltage clamp according to an embodiment of the present invention;
fig. 5 is a schematic functional structure diagram of a circuit for controlling PWM loop stability according to a second embodiment of the present invention;
fig. 6 is a circuit diagram of a clamp circuit according to a second embodiment of the present invention;
fig. 7 is a circuit diagram of a voltage generating circuit according to a second embodiment of the present invention;
fig. 8 is a circuit diagram of a clamping accuracy monitoring module according to a second embodiment of the present invention;
fig. 9 is a circuit diagram of another clamping accuracy monitoring module according to a second embodiment of the present invention;
fig. 10 is a circuit diagram of a clamp control module according to a second embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In the present application, the embodiments and features of the embodiments may be combined with each other in the embodiments one without conflict
As shown in fig. 1, in this embodiment, a method for controlling PWM loop stabilization includes:
s10, obtaining the stable working voltage of the PWM loop according to the input voltage and the output voltage of the DC-DC converter;
and S20, clamping the output voltage of the error amplifier to the stable working voltage of the PWM loop, wherein the error amplifier belongs to the PWM loop.
In the embodiment, the stable working voltage of the PWM loop is obtained in a self-adaptive manner according to the input voltage and the output voltage of the DC-DC converter, so that the output voltage of the error amplifier is clamped in a self-adaptive manner, the suppression performance of the system on the input and output voltage disturbance is improved, the PWM loop can be stabilized quickly, and the method can be applied to a PFM/PWM dual-mode control loop, realize the fast switching of the PFM/PWM mode and effectively reduce the output voltage drop, and has strong universality.
In practical applications, clamping the output voltage of the error amplifier to the stable operating voltage of the PWM loop includes: the method comprises the steps that the output voltage of an error amplifier is clamped to a certain precision range of stable working voltage of a PWM loop, the PWM loop can work stably within the precision range, the method also belongs to the protection range of the application, and the specific precision range can be set according to the requirements of practical application.
In the present application, the PWM loop may be a PWM single-mode control loop, and may also belong to a PFM/PWM dual-mode control loop, or other circuits including a PWM loop.
As shown in fig. 2, in this embodiment, after step S20, the method further includes:
and S30, obtaining a voltage threshold interval according to the input voltage and the output voltage of the DC-DC converter, monitoring whether the output voltage of the error amplifier is in the voltage threshold interval, and judging whether clamping is carried out according to the monitoring result.
It should be noted that the clamping accuracy, that is, the accuracy range mentioned above, can be measured by setting the voltage threshold interval, and the voltage threshold interval can also be understood as being obtained by stabilizing the operating voltage of the PWM loop. The voltage threshold interval may be between two voltage thresholds, may be higher than a certain voltage threshold or lower than a certain voltage threshold, and the like, and is preferably set between two voltage thresholds. Of course, in other embodiments, the clamping accuracy of the output voltage of the error amplifier may be controlled by setting the clamping time, etc., so as to stabilize the PWM loop, and the above methods all belong to the protection scope of the present application.
As another embodiment, the step S30 may be started before the step S20. That is, before the first clamping operation, it may be determined whether the output voltage of the error amplifier falls within the voltage threshold range, and if not, the clamping operation is performed, otherwise, the clamping operation is not performed, and of course, the monitoring may be performed after the first clamping operation is directly performed.
Monitoring the output voltage of the error amplifier, and stopping clamping operation when the output voltage of the error amplifier falls into the voltage threshold interval; when the input voltage of the DC-DC converter fluctuates and the output voltage of the error amplifier deviates from the voltage threshold interval, the clamping operation is started again, so that the PWM loop is quickly stabilized. The above steps S10-S30 of the present embodiment can be implemented by a clamping circuit, and it is understood that the order of the steps is merely an example.
In this embodiment, the clamping the output voltage of the error amplifier to the stable operating voltage of the PWM loop includes:
sampling the stable working voltage of the PWM loop, and obtaining a sampling holding voltage through sampling holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
The output voltage of the error amplifier can be clamped to a relatively stable working voltage in each sampling period by adopting a sampling and holding mode, so that the PWM loop is clamped to the stable working voltage more stably. Similarly, the output voltage of the error amplifier is clamped to a certain precision range of the sample-and-hold voltage, which can also be measured in the manner of the above voltage threshold interval, and is sufficient for stable operation of the PWM loop.
In this embodiment, if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, when the DC-DC converter jumps from a light load to a heavy load, a pre-trigger signal is received;
and when the output voltage of the error amplifier is clamped to the stable PWM working voltage, a mode feedback signal is sent, and the working mode control module generates a first mode switching signal according to the mode feedback signal so as to switch from the PFM working mode to the PWM working mode.
It should be noted that, the clamping of the output voltage of the error amplifier to the PWM stable operating voltage includes clamping the output voltage of the error amplifier to a certain precision range of the PWM stable operating voltage, and the precision range may be the voltage threshold interval. It can be seen that the pre-trigger signal can enable the PWM loop to respond in advance through the clamp circuit, so that the PWM loop can quickly obtain a stable working voltage, and then the mode feedback signal can prompt the mode switching, so as to enter the PWM loop control mode in advance.
In this embodiment, after the DC-DC converter switches from the PFM operation mode to the PWM operation mode, the method further includes:
when the DC-DC converter jumps from a heavy load to a light load, the working mode control module generates a second mode switching control signal to switch from a PWM working mode to a PFM working mode.
In this embodiment, the step S20 is performed by a clamping circuit, as shown in fig. 3, which is a circuit diagram of the clamping circuit and mainly includes: an Adaptive EA Clamping Voltage Generation Block 301 and a Clamping Voltage sample hold and output Block (S/H & Voltage Buffer) 302; the adaptive clamping voltage circuit 301 further comprises a voltage generation circuit and a clamping precision control circuit, wherein the voltage generation circuit is used for generating a stable working voltage of a PWM loop; the clamping voltage sampling, holding and outputting module is used for clamping the output voltage of the error amplifier to the stable working voltage of the PWM loop; a PWM loop stable working voltage Vea _ cc is generated through a voltage generating circuit 301, the Vea _ cc is adaptively adjusted along with a power supply input voltage Vin and a DC-DC output voltage, then the output voltage of an error amplifier is clamped to the Vea _ cc through an S/H volt buffer module 302, the approach degree of the output voltage Vea of the error amplifier and the Vea _ cc is monitored through a clamping precision control circuit, and in a PFM/PWM dual-mode control loop, the time for starting PWM loop control is determined and whether a clamping channel is disconnected or not, so that the PWM loop is ensured to be stable when entering a PWM mode, and voltage drop caused by mode switching is reduced. When the PWM mode control is carried out, the output voltage Vea of the error amplifier is monitored in time, and if the fluctuation of the power supply voltage Vin causes the Vea to deviate from the set voltage Vea _ cc with certain precision, the clamping circuit is started again and clamps the Vea to be close to the set value, so that the output voltage jitter caused by the fluctuation of the power supply voltage is avoided.
In the present embodiment, as shown in fig. 4, a system structure of a PWM/PFM dual-mode modulation (i.e. PFM/PWM dual-mode control loop) DC-DC converter based on an error amplifier output voltage clamp is schematically illustrated, which mainly includes a switching transistor PMOS transistor 401, an NMOS transistor 402, an inductor L and a capacitor C403 and 404, a control logic and driving module 405, a PWM control loop 406, a PFM control loop 407, and a PWM/PFM operation mode control module 408, wherein the PWM control loop 406 mainly includes an error amplifier 4062, a compensation network 4061 thereof, a PWM comparator 4063, and a clamp circuit 4064, the PFM loop mainly includes a PFM comparator 4071 and a PFM control logic 4072, when the system is in a light load, the PWM/PFM operation mode control module generates a mode control signal Modch low, the system is immediately in a PFM loop modulation (control) state, when the system is suddenly switched from a light load to a heavy load, the PWM/PFM operation mode control module generates a PWM mode control signal Modch low, the system is immediately switched from a PWM/PFM operation mode control signal predriver-PRE-switch to a PWM mode control signal when the system suddenly jumps from a light load to a heavy load, the PWM/PFM operation mode control module immediately switches a PWM operation mode control signal PFM operation mode feedback signal PFM operation mode to a PWM control module generates a PWM control signal when the system is suddenly switched to a PWM control signal clamp mode, the PWM control module outputs a PWM control signal clamp mode, and the PWM control module switches a PWM control module starts a PWM control signal clamp mode when the PWM control module starts a PWM control module, and the PWM control module starts a PWM control signal PWM control module, the PWM control module starts a PWM.
Example two
As shown in fig. 5, in the present embodiment, a circuit for controlling the stability of a PWM loop includes:
an error amplifier 10 and a clamping circuit 20, the clamping circuit is used for clamping the output voltage of the error amplifier to a PWM loop stable working voltage, the error amplifier belongs to the PWM loop, and the clamping circuit comprises: and the voltage generating circuit is used for generating the stable working voltage of the PWM loop according to the input voltage and the output voltage of the DC-DC converter.
In this embodiment, the stable operating voltage of the PWM loop is adaptively generated according to the input voltage and the output voltage of the DC-DC converter, so that the clamping circuit can adaptively clamp the output voltage of the error amplifier, thereby improving the performance of the system in suppressing the input/output voltage disturbance. The clamping circuit can also be applied to a PFM/PWM dual-mode control loop, and is favorable for realizing the fast switching of PFM/PWM modes and effectively reducing the output voltage drop amplitude. The clamping circuit is used for clamping the output voltage of the error amplifier to a PWM loop stable working voltage and comprises: the output voltage of the error amplifier is clamped to a certain precision range of the stable working voltage of the PWM loop, and the PWM loop can work stably within the precision range.
In this embodiment, as shown in fig. 3, a circuit diagram of the adaptive clamp circuit mainly includes: an Adaptive EA Clamping Voltage Generation Block 301 and a Clamping Voltage sample hold and output Block (S/H & Voltage Buffer) 302; the adaptive clamping voltage circuit 301 further comprises a voltage generation circuit and a clamping precision control circuit, wherein the voltage generation circuit is used for generating a stable working voltage of a PWM loop; the clamping voltage sampling, holding and outputting module is used for clamping the output voltage of the error amplifier to the stable working voltage of the PWM loop; a PWM loop stable working Voltage Vea _ cc is generated through a Voltage generation circuit 301, the Vea _ cc is adaptively adjusted along with the influence of a power supply input Voltage Vin and a DC-DC output Voltage, then the output Voltage of an error amplifier is clamped to the Vea _ cc through an S/H Voltage Buffer module 302, and the approaching degree of the actual output Voltage Vea of the error amplifier and the Vea _ cc is monitored, so that the time for starting PWM loop control is determined and whether a clamping path is disconnected or not is determined in a PFM/PWM dual-mode control loop, and the PWM loop is ensured to be stabilized when entering a PWM mode, and the Voltage drop caused by mode switching is reduced. When the voltage is in the PWM mode, the output voltage Vea of the error amplifier is monitored in time, and if the fluctuation of the power supply voltage Vin causes the Vea to deviate from the set voltage Vea _ cc with certain precision, the clamping circuit is started again and clamps the Vea to be close to the set value, so that the output voltage jitter caused by the fluctuation of the power supply voltage is avoided.
In this embodiment, the clamp circuit further includes: the sampling, holding and outputting module is used for sampling the stable working voltage of the PWM loop and obtaining a sampling and holding voltage through sampling and holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
The sample-hold-and-output module can enable the output voltage of the error amplifier to be clamped to a relatively stable working voltage in each sampling period, so that the PWM loop is stably clamped to the stable working voltage. Similarly, the output voltage of the error amplifier is clamped to a certain precision range of the sample-and-hold voltage, which can be measured by a voltage threshold interval, and is sufficient for stable operation of the PWM loop.
As shown in fig. 6, in a possible embodiment, the sample-hold-and-output module includes a sample-hold switch 504, a sampling capacitor 505, a clamp switch 503, and a voltage buffer unit 502, wherein one end of the sample-hold switch 504 is used for inputting the PWM stable operating voltage Vea _ cc, the sample-hold switch 504 is controlled by the first clock signal C L KA, the other end of the sample-hold switch 504 is connected to one end of the sampling capacitor 505 and the positive input end of the voltage buffer unit 502, the other end of the sampling capacitor 505 is grounded, the output end of the voltage buffer unit 502 is connected to the negative input end thereof and one end of the clamp switch 503, and the other end of the clamp switch 503 is connected to the output end of the error amplifier.
In this embodiment, the voltage generation circuit is further configured to obtain a voltage threshold interval according to the input voltage and the output voltage of the DC-DC converter.
It should be noted that the clamping accuracy, that is, the accuracy range mentioned above, can be measured by setting the voltage threshold interval, and the voltage threshold interval can also be understood as being obtained by stabilizing the operating voltage of the PWM loop. The voltage threshold interval may be between two voltage thresholds, may be higher than a certain voltage threshold or lower than a certain voltage threshold, and the like, and is preferably set between two voltage thresholds. Of course, in other embodiments, the clamping accuracy of the output voltage of the error amplifier may be controlled by setting the clamping time, etc., so as to stabilize the PWM loop, and the above methods all belong to the protection scope of the present application.
In this embodiment, the clamp circuit further includes: the clamping precision control circuit comprises a clamping precision monitoring module and a clamping control module, wherein the clamping precision monitoring module is used for monitoring whether the output voltage of the error amplifier is within the voltage threshold range, and the clamping control module is used for generating a clamping control signal according to a monitoring result so as to determine whether to clamp or not.
For example, when the output voltage of the error amplifier is within the voltage threshold range, the clamping operation is not performed (including stopping clamping), otherwise, the clamping operation is performed, that is, the output voltage of the error amplifier is clamped within the voltage threshold range.
In this embodiment, if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, the circuit for controlling the stability of the PWM loop further includes: the working mode control module is used for generating a pre-trigger signal and receiving a mode feedback signal; and the clamping control module is used for generating the mode feedback signal and the clamping control signal according to the monitoring result and the pre-trigger signal.
As shown in fig. 4, in this embodiment, in the case of a PFM/PWM dual-mode control loop, the operating mode control module 408 is connected to the clamping circuit 4064, and is configured to send a PRE-trigger signal EN _ PWM _ PRE to the clamping circuit when the system jumps from a light load to a heavy load, and receive a mode feedback signal EN _ RED _ PWM sent by the clamping circuit when the output voltage of the error amplifier is clamped to the stable operating voltage of the PWM loop, and generate a corresponding mode switching control signal Modch based on the mode feedback signal, the operating mode control module 408 is connected to the control logic and driving module 405 of the DC-DC converter, and is configured to transmit the mode switching control signal Modch to the control logic and driving module 405, the control logic and driving module 405 is connected to the PWM/PFM dual-mode control loop (406 and 407), for mode switching the PWM/PFM dual-mode control loop (406 and 407) upon receiving the mode switching control signal Modch (first mode switching control signal). And switching from the PFM working mode to the PWM working mode.
When the DC-DC converter jumps from a heavy load to a light load, the working mode control module is used for generating a second mode switching control signal so as to switch from a PWM working mode to a PFM working mode.
The clamping of the output voltage of the error amplifier to the PWM loop stabilization operating voltage includes clamping the output voltage of the error amplifier to the voltage threshold interval generated based on the PWM loop stabilization operating voltage. The PWM/PFM dual-mode modulation DC-DC converter based on the error amplifier output voltage clamp has the advantages of simple structure, fast and quick PWM/PFM mode switching, small voltage drop, high universality and strong reliability, and is not only suitable for Buck type architectures, but also suitable for architectures such as Boost, Buck-Boost and the like; not only can realize accurate clamping on the output voltage of the error amplifier, but also can realize smooth switching from PFM to PWM by combining a PWM/PFM mode control module so as to reduce voltage drop.
As shown in fig. 7, in the present embodiment, the voltage generation circuit includes a voltage-current conversion circuit 506, a first current source 507, a second current source 511, a comparator 510, a first switch 509, a second switch 514, a first capacitor 508, a second capacitor 513, and a third switch 512, an input end of the voltage-current conversion circuit 506 is used for inputting an input voltage of the DC-DC converter, an output end of the voltage-current conversion circuit 506 is connected to the first current source 507, an output end of the first current source 507 is connected to one end of the first capacitor 508, one end of the first switch 509, and a positive input end of the comparator 510, the other end of the first capacitor 508 is grounded together with the other end of the first switch 509, a negative input end of the comparator 510 is used for inputting β times the output voltage of the DC-DC converter (where β is a constant), a control end of the comparator 510 is used for inputting an inverted clock signal, the first switch 509 and the second switch 514 are controlled by a clock signal C L K, an output signal of the comparator 510 is used for controlling an output end of the third switch 513 and the second switch 512, and the other end of the second switch 511 is connected to the second switch 511, and the second switch 512, and the second input end of the second switch 511 are connected to the second switch 511, and the second switch 512 of the second switch 512.
In this circuit, the negative input terminal of the comparator 510 inputs a voltage value related to the output voltage of the DC-DC converter, i.e. β times the output voltage of the DC-DC converter, β is selected according to the actual requirement, for example, it can be derived from the following specific formula.
As shown in fig. 7, in the present embodiment, the voltage generation circuit further includes: a voltage conversion circuit, the voltage conversion circuit comprising: an operational amplifier 515, a PMOS transistor 516, a first variable resistor string 517, a second variable resistor string 518, a positive input of the operational amplifier 515 is connected to an output of the second current source 511, the output terminal of the operational amplifier 515 is connected to the gate of the PMOS transistor 516, the source of the PMOS tube 516 is used for inputting the input voltage Vin of the DC-DC converter, the drain of the PMOS transistor 516 is connected in series with the first varistor string 517 and the second varistor string 518 and then grounded, the voltage at the connection point of the first variable resistor string 517 and the second variable resistor string 518 is the PWM stable operating voltage Vea _ cc, the negative input terminal of the operational amplifier 515 is connected to the connection point, the output terminal of the first variable resistor string 517 is used for outputting the high voltage threshold of the voltage threshold interval, the output terminal of the second variable resistor string 518 is used for outputting the low voltage threshold of the voltage threshold interval.
In this embodiment, referring to fig. 7, at low level of each clock cycle (C L K), two current sources
Figure BDA0001965050230000151
And 511(Ic) respectively charge the two capacitors 508 and 513, the charging time Tc is controlled by the comparator 510, and the voltage Vea _ C of the capacitor C2(513) during the charging time Tc is the required setting voltage. The set voltage passes through a voltage conversion circuit (mainly composed of an operational amplifier 515, Pmos)Tube 516 and variable resistor strings 517 and 518) produces two high and low voltages Vh and Vl that vary in proportion to the set voltage Vea _ c. The charging time Tc controlled by the comparator 510 is obtained based on the principle of charge conservation (Q ═ I · T ═ C · V), and the current source is used
Figure BDA0001965050230000152
The time taken for charging the capacitor C1 to β Vout is
Figure BDA0001965050230000153
The capacitor C2 gets a voltage of Tc
Figure BDA0001965050230000154
When the output voltage of the error amplifier is the set voltage Vea _ c (or falls within the set voltage accuracy range), the PWM loop is stable. The voltage conversion circuit can realize the setting of the clamping voltage precision, and the precision can be expressed as
Figure BDA0001965050230000155
In this embodiment, referring to fig. 7, the input terminals Vea _ c of the second current source have the same value as Vea _ cc, and can also be used as the PWM stable operating voltage, but it is not stable for Vea _ cc, so it is preferable that Vea _ cc and Vea _ cc are converted by the conversion circuit.
As shown in fig. 8, in the present embodiment, the clamping accuracy monitoring module includes: a first comparator 5201, a second comparator 5202 and an exclusive-or gate 5203, wherein a positive input terminal of the first comparator 5201 is used for inputting the high voltage threshold Vh of the voltage threshold interval, a positive input terminal of the second comparator 5202 is used for inputting the low voltage threshold Vl of the voltage threshold interval, negative input terminals of the first comparator 5201 and the second comparator 5202 are both used for inputting the output voltage Vea of the error amplifier, output terminals of the first comparator 5201 and the second comparator 5202 are respectively connected to two input terminals of the exclusive-or gate 5203, and an output terminal of the exclusive-or gate 5203 is connected to the clamping control module.
As another embodiment, as shown in fig. 9, the clamping accuracy monitoring module includes: a third current source 5204, a fourth current source 5205, a first PMOS transistor 5206, a second PMOS transistor 5207, a third PMOS transistor 5208, a fourth PMOS transistor 5209, a first resistor R1 and a second resistor R2, wherein the input terminals of the third current source 5204 and the fourth current source 5205 are used for inputting the input voltage Vin of the DC-DC converter, the output terminal of the third current source 5204 is connected to the sources of the first PMOS transistor 5206 and the second PMOS transistor 5207, the gate of the first PMOS transistor 5206 is used for inputting the low voltage threshold Vl of the voltage threshold interval, the drain of the first PMOS transistor 5206 is connected to the drain of the third PMOS transistor 5208, the end of the first resistor R1 is connected to the control module, the other end of the first resistor R1 is connected to ground, the gate of the second PMOS transistor 5207 and the gate of the third PMOS transistor 5208 are used for inputting the output voltage Vea of the error amplifier, the drain of the second PMOS transistor 5207 is connected to the drain of the fourth PMOS transistor R2, the other end of the second resistor R2 is grounded, the output end of the fourth current source 5205 is connected to the sources of the third PMOS transistor 5208 and the fourth PMOS transistor 5209, respectively, and the gate of the fourth PMOS transistor 5209 is used for inputting the high voltage threshold Vh of the voltage threshold interval.
As shown in fig. 10, in the present embodiment, the clamping control module includes a nand gate 519, a D flip-flop 521, and a delay unit 522, a first input end of the nand gate 519 is connected to the output end of the clamping precision monitoring module 520, a second input end of the nand gate 519 is used for inputting a high level when the PWM loop belongs to the PWM single-mode control loop, a second input end of the nand gate 519 is used for inputting the PRE-trigger signal EN _ PWM _ PRE when the PWM loop belongs to the PFM/PWM dual-mode control loop, an output end of the nand gate 519 is connected to a reset end of the D flip-flop 521, a D end of the D flip-flop 521 is used for inputting a high level, a clock end of the D flip-flop 521 is used for inputting a second clock signal C L KB, a Q end of the D flip-flop 521 is connected to the input end of the delay unit 522, and an output end of the delay unit 522 is used for outputting the clamping switch control signal EN _ Buffer.
Preferably, in this embodiment, the clock signal C L K, the first clock signal C L KA, and the second clock signal C L KB are clock signals with the same frequency and different timings.
It can be seen that the clamping accuracy control circuit shown in fig. 10 can be applied to a PWM single-mode control loop and a PFM/PWM dual-mode control loop only by adjusting signals through relevant ports without changing the circuit structure, and has stronger universality.
In this embodiment, the clamping circuit is adopted to clamp the output voltage of the error amplifier to the stable working voltage of the PWM loop quickly, when the clamping is within the precision range of the stable working voltage of the PWM loop, the clamping may be stopped if the PWM loop is stable, when the input voltage of the DC-DC converter fluctuates and the output voltage of the error amplifier deviates from the precision range, the clamping is started again until the clamping is performed again to the precision range, and the stable working voltage of the PWM loop changes with the input voltage and the output voltage of the DC-DC converter, so that the adaptive clamping may be realized and the PWM loop is controlled to be stable quickly. The clamping circuit can also be used in a PFM/PWM dual-mode control loop, a working mode control module is arranged, when a DC-DC converter system jumps from light load to heavy load, a pre-trigger signal is sent to the clamping circuit, when the PWM loop is stable, namely the output voltage of the error amplifier is in the precision range, the clamping circuit feeds back a mode feedback signal to the working mode control module, and the working mode control module generates a mode switching control signal according to the mode feedback signal, so that the DC-DC converter is switched from PFM mode control to PWM mode control. When the system jumps from heavy load to light load, the working mode control module generates a mode switching control signal, so that the DC-DC converter is switched from PWM mode control to PFM mode control. Therefore, the circuit for controlling the stability of the PWM loop has the advantages of strong universality, good stability and high response speed.
EXAMPLE III
As shown in fig. 4, in this embodiment, a DC-DC converter includes the above-mentioned circuit for controlling the stability of the PWM loop, and further includes a control logic and driving module, a first MOS transistor, a second MOS transistor, an off-chip filter inductor, and a capacitor.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (17)

1. A method of controlling PWM loop stability, comprising:
obtaining a stable working voltage of a PWM loop according to the input voltage and the output voltage of the DC-DC converter;
and clamping the output voltage of an error amplifier to the stable working voltage of the PWM loop, wherein the error amplifier belongs to the PWM loop.
2. The method of claim 1, further comprising:
obtaining a voltage threshold interval according to the input voltage and the output voltage of the DC-DC converter,
and monitoring whether the output voltage of the error amplifier is in the voltage threshold interval, and judging whether clamping is carried out according to the monitoring result.
3. The method of claim 1 or 2, wherein clamping the output voltage of the error amplifier to the PWM loop stabilization operating voltage comprises:
sampling the stable working voltage of the PWM loop, and obtaining a sampling holding voltage through sampling holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
4. Method for controlling PWM loop stabilization according to claim 1 or 2,
if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, receiving a pre-trigger signal when the DC-DC converter jumps from a light load to a heavy load;
and when the output voltage of the error amplifier is clamped to the stable PWM working voltage, a mode feedback signal is sent, and the working mode control module generates a first mode switching signal according to the mode feedback signal so as to switch from the PFM working mode to the PWM working mode.
5. The method of claim 4, wherein after the DC-DC converter switches from the PFM operating mode to the PWM operating mode, further comprising:
when the DC-DC converter jumps from a heavy load to a light load, the working mode control module generates a second mode switching control signal to switch from a PWM working mode to a PFM working mode.
6. A circuit for controlling PWM loop stabilization, comprising:
an error amplifier and a clamp for clamping an output voltage of the error amplifier to a PWM loop stable operating voltage, the error amplifier belonging to a PWM loop, the clamp comprising: and the voltage generating circuit is used for generating the stable working voltage of the PWM loop according to the input voltage and the output voltage of the DC-DC converter.
7. The circuit for controlling PWM loop stabilization according to claim 6,
the clamp circuit further includes: the sampling, holding and outputting module is used for sampling the stable working voltage of the PWM loop and obtaining a sampling and holding voltage through sampling and holding;
clamping an output voltage of the error amplifier to the sample and hold voltage for at least one sampling period.
8. The circuit for controlling PWM loop stabilization according to claim 6 or 7,
the voltage generation circuit is further configured to obtain a voltage threshold interval according to the input voltage and the output voltage of the DC-DC converter.
9. The circuit for controlling PWM loop stabilization according to claim 8,
the clamp circuit further includes: the clamping precision control circuit comprises a clamping precision monitoring module and a clamping control module, wherein the clamping precision monitoring module is used for monitoring whether the output voltage of the error amplifier is within the voltage threshold range, and the clamping control module is used for generating a clamping control signal according to a monitoring result so as to determine whether to clamp or not.
10. The circuit for controlling PWM loop stabilization according to claim 9,
if the error amplifier belongs to a PWM loop in a PWM/PFM dual-mode control loop, the circuit for controlling the stability of the PWM loop further comprises: the working mode control module is used for generating a pre-trigger signal and receiving a mode feedback signal; and the clamping control module is used for generating the mode feedback signal and the clamping control signal according to the monitoring result and the pre-trigger signal.
11. The circuit for controlling PWM loop stabilization according to claim 7,
the sample-and-hold and output module includes: the PWM stable working voltage detection circuit comprises a sample-hold switch, a sampling capacitor, a clamping switch and a voltage cache unit, wherein one end of the sample-hold switch is used for inputting the PWM stable working voltage, the sample-hold switch is controlled by the first clock signal, the other end of the sample-hold switch is connected with one end of the sampling capacitor and a positive input end of the voltage cache unit, the other end of the sampling capacitor is grounded, an output end of the voltage cache unit is connected with a negative input end of the voltage cache unit and one end of the clamping switch, and the other end of the clamping switch is connected with an output end of the error amplifier.
12. The circuit for controlling PWM loop stabilization according to claim 8,
the voltage generation circuit comprises a voltage-current conversion circuit, a first current source, a second current source, a comparator, a first switch, a second switch, a first capacitor, a second capacitor and a third switch, wherein the input end of the voltage-current conversion circuit is used for inputting the input voltage of the DC-DC converter, the output end of the voltage-current conversion circuit is connected with the first current source, the output end of the first current source is connected with one end of the first capacitor, one end of the first switch and the positive input end of the comparator, the other end of the first capacitor is grounded together with the other end of the first switch, the negative input end of the comparator is used for inputting β times of the output voltage of the DC-DC converter, the control end of the comparator is used for inputting a reverse clock signal, the first switch and the second switch are controlled by a clock signal, the output signal of the comparator is used for controlling the third switch, one end of the third switch is connected with one end of the second capacitor and one end of the second switch, the other end of the second capacitor is grounded together with the other end of the second switch, the other end of the third switch is connected with the output end of the second switch, and the second switch is used for inputting the DC-DC converter.
13. The circuit for controlling PWM loop stabilization according to claim 12, wherein the circuit is characterized by
The voltage generation circuit further includes: a voltage conversion circuit, the voltage conversion circuit comprising: the positive input end of the operational amplifier is connected with the output end of the second current source, the output end of the operational amplifier is connected with the grid electrode of the PMOS tube, the source electrode of the PMOS tube is used for inputting the input voltage of the DC-DC converter, the drain electrode of the PMOS tube is grounded after being connected with the first variable resistor string and the second variable resistor string in series, the voltage of the connection point of the first variable resistor string and the second variable resistor string is the PWM stable working voltage, the negative input end of the operational amplifier is connected with the connection point, the output end of the first variable resistor string is used for outputting the high voltage threshold value of the voltage threshold value interval, and the output end of the second variable resistor string is used for outputting the low voltage threshold value of the voltage threshold value interval.
14. The circuit for controlling PWM loop stabilization according to claim 9,
the clamping accuracy monitoring module comprises: the positive input end of the first comparator is used for inputting a high voltage threshold value of the voltage threshold interval, the positive input end of the second comparator is used for inputting a low voltage threshold value of the voltage threshold interval, the negative input ends of the first comparator and the second comparator are both used for inputting the output voltage of the error amplifier, the output ends of the first comparator and the second comparator are respectively connected with two input ends of the exclusive-or gate, and the output end of the exclusive-or gate is connected with the clamping control module;
alternatively, the first and second electrodes may be,
the clamping accuracy monitoring module comprises: a third current source, a fourth current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first resistor, and a second resistor, wherein input terminals of the third current source and the fourth current source are used for inputting an input voltage of the DC-DC converter, an output terminal of the third current source is connected to source terminals of the first PMOS transistor and the second PMOS transistor, a gate of the first PMOS transistor is used for inputting a low voltage threshold of the voltage threshold interval, a drain of the first PMOS transistor and a drain of the third PMOS transistor are connected to one end of the first resistor and the clamp control module, the other end of the first resistor is grounded, a gate of the second PMOS transistor and a gate of the third PMOS transistor are used for inputting an output voltage of the error amplifier, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, the output end of the fourth current source is connected with the source electrodes of the third PMOS tube and the fourth PMOS tube respectively, and the grid electrode of the fourth PMOS tube is used for inputting the high voltage threshold value of the voltage threshold value interval.
15. The circuit for controlling PWM loop stabilization according to claim 9 or 10,
the clamp control module includes: a NAND gate, a D trigger and a delay unit, wherein the first input end of the NAND gate is connected with the output end of the clamping precision monitoring module, the second input terminal of the nand gate is used for inputting high level when the PWM loop belongs to the PWM single-mode control loop, the second input end of the NAND gate is used for inputting the pre-trigger signal when the PWM loop belongs to a PFM/PWM dual-mode control loop, the output end of the NAND gate is connected with the reset end of the D flip-flop, the D end of the D flip-flop is used for inputting high level, the clock end of the D trigger is used for inputting a second clock signal, the Q end of the D trigger is connected with the input end of the delay unit, the output end of the delay unit is used for outputting the clamping switch control signal, when the PWM loop belongs to a PWM/PFM dual-mode control loop, the Q non-end of the D trigger is used for outputting the mode feedback signal.
16. The circuit for controlling PWM loop stabilization according to claim 10,
the working mode control module is connected with the clamping circuit and used for sending a pre-trigger signal to the clamping circuit when a system jumps from light load to heavy load, receiving a mode feedback signal sent by the clamping circuit when the output voltage of the error amplifier is clamped to the stable working voltage of the PWM loop, and generating a corresponding mode switching control signal based on the mode feedback signal, the working mode control module is connected with the control logic and driving module of the DC-DC converter and used for transmitting the mode switching control signal to the control logic and driving module, and the control logic and driving module is connected with the PWM/PFM dual-mode control loop and used for carrying out mode switching on the PWM/PFM dual-mode control loop after receiving the mode switching control signal.
17. A DC-DC converter comprising the circuit for controlling PWM loop stabilization according to any one of claims 6 to 16, further comprising a control logic and driving module, a first MOS transistor, a second MOS transistor, an off-chip filter inductor, and a capacitor.
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