CN111490681A - Quasi-resonance switch power supply controller based on valley bottom locking - Google Patents
Quasi-resonance switch power supply controller based on valley bottom locking Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/06—Circuits specially adapted for rendering non-conductive gas discharge tubes or equivalent semiconductor devices, e.g. thyratrons, thyristors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Abstract
The invention relates to a quasi-resonance switch power supply controller based on valley bottom locking, which comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) on judgment logic unit, a PWM off judgment logic unit, a PWM generation unit and a driver, wherein the valley bottom detection unit is used for detecting the valley bottom of a switch; aiming at different load conditions of the switching power supply, the controller adjusts the peak current signal to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application condition, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.
Description
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a quasi-resonant switching power supply controller based on valley bottom locking.
Background
Compared with a linear power supply, the switching power supply has the advantages of easiness in control, high efficiency, small volume, good reliability and easiness in protection, and is widely applied to equipment such as television power supplies, mobile phone chargers, L ED, industrial instruments, power adapters and the like.
In the prior art, the quasi-resonance control technology used for the switching power supply has the main disadvantages that the switching frequency is not fixed, especially when the switching frequency is high at high input voltage and light load, on one hand, the switching frequency is limited by a power switch device, and on the other hand, the high switching frequency means larger switching loss, so that the power supply conversion efficiency is reduced and the advantage of valley bottom switching-on is offset. Therefore, in practical application, the highest switching frequency, i.e. the shortest switching period, is set, and if the preset valley bottom occurs in the shortest switching period, the valley bottom conduction is delayed until the valley bottom is allowed to be turned on after the shortest switching period is reached. Under different load conditions, the valley bottom number of the power tube when being switched on is different, even if the same load is carried out, the power tube can be switched on back and forth by two adjacent valley bottoms due to real-time control of the feedback loop, the switching frequency is not fixed, and when the switching frequency is within the hearing range of human ears, audio noise can appear.
Disclosure of Invention
The invention provides a quasi-resonant switching power supply controller based on valley bottom locking, and solves the problems that the valley bottom number of a power tube during the switching-on process cannot be changed in a self-adaptive manner and is difficult to keep stable under different load conditions of a switching power supply in the prior art, and the switching frequency is not fixed and audio noise occurs under the same load condition.
In order to solve the technical problem, the invention provides a quasi-resonant switching power supply controller based on valley bottom locking, which comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) switching-on judgment logic unit, a PWM switching-off judgment logic unit, a PWM generation unit and a driver, wherein the valley bottom detection unit is used for detecting the valley bottom of a switch; the valley bottom detection unit is connected to a first input end of an auxiliary winding of the switching power supply and used for inputting detection voltage signals of the auxiliary winding of the transformer and detecting valley bottoms, and the valley bottom counting unit counts the valley bottom detection signals from the valley bottom detection unit, outputs valley bottom counting signals and then respectively outputs the valley bottom counting signals to the valley bottom locking unit and the PWM switching-on judgment logic unit; the valley bottom locking unit is connected with a valley bottom detection signal from the valley bottom detection unit and a voltage detection signal output by a feedback loop of the switching power supply, and respectively outputs a valley bottom number locking signal and a minimum switching period signal to the PWM opening judgment logic unit, and the PWM opening judgment logic unit further outputs a PWM opening signal to the PWM generation unit; the valley bottom locking unit also outputs a peak current signal to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit also accesses a current sampling signal flowing through a power switch tube in the switch power supply, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal to the PWM generating unit; the PWM generating unit correspondingly generates a low-level or high-level control signal according to the PWM turn-off signal or the PWM turn-on signal and outputs the low-level or high-level control signal to the driver; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.
Preferably, the valley bottom locking unit includes a limit frequency generator, a first latch, a valley bottom number latch adjuster and a peak current signal generator, wherein the limit frequency generator outputs a minimum switching cycle signal to the first latch, the first latch is configured to record a count value of a valley bottom count signal when a first valley bottom arrives after the minimum switching cycle signal arrives, the count value is defined as a first valley bottom count value, the first valley bottom count value is input to the valley bottom number latch adjuster, and the valley bottom number latch adjuster outputs the valley bottom number latch signal; the peak current signal generator detects the input feedback voltage detection signal and correspondingly outputs a peak current signal.
Preferably, the valley bottom locking unit further comprises an update timer, a filter timer, a time delay adjuster and a second latch; the updating timer generates an output updating time signal to the time delay regulator to serve as an updating time interval for generating the valley bottom latching signal; the filtering timer completes transient response to the valley bottom number latching signal, generates an output filtering time signal and inputs the output filtering time signal into the updating timer; the time delay regulator starts timing from the minimum switching period to prevent the lag time of valley bottom jumping, and outputs a lag time signal to the second latch; and the second latch is used for recording the count value of the corresponding valley bottom counting signal when the first valley bottom of the lag time is reached, defining the count value as a second valley bottom count value, and inputting the second valley bottom count value into the valley bottom number latch regulator.
Preferably, the valley bottom locking unit further includes a feedback signal interval judger for performing interval identification judgment on the input feedback signal and outputting an interval identification signal to the valley bottom number locking adjuster correspondingly.
Preferably, for the PWM on judgment logic unit, after the minimum switching period signal arrives, if the value of the valley bottom counting signal is greater than or equal to the value of the valley bottom number latching signal, i.e. Nv _ cur is greater than or equal to Nv _ lock, the PWM on signal is immediately generated to turn on PWM; and the PWM turn-off judgment logic unit comprises a comparator, and when the switching power supply detects that the current flowing through the sampling resistor is greater than the set value of the peak current signal, the PWM turn-off judgment logic unit generates a PWM turn-off signal to turn off the PWM.
Preferably, when the load of the switching power supply is reduced, the peak current signal is reduced, the primary charge-discharge cycle of the transformer excitation inductor is shortened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the left, and within the updating time interval, as long as one PWM cycle detects that the first valley bottom count value is greater than the value of the valley bottom latching signal, that is, Nv _ lim1> Nv _ lock, the value of the valley bottom latching signal is increased by 1 when the updating time interval arrives.
Preferably, when the load of the switching power supply is increased, the peak current signal is increased, the primary charge-discharge cycle of the transformer excitation inductor is lengthened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the right, and in the updating time interval, if all PWM cycles satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, the value of the valley bottom number latch signal is decreased by 1 when the updating time interval arrives.
Preferably, the system generates transient fluctuation every time the value of the valley bottom number latch signal is reduced by 1, at this time, a filtering timer is started to filter out the value change of the valley bottom number latch signal caused by the transient fluctuation, before the timing of the filtering timer is reached, the value of the valley bottom number latch signal is kept unchanged, the change condition of the valley bottom number latch signal cannot be detected, and after the filtering timer is ended, the updating timer is restarted to start the detection of the change condition of the valley bottom number latch signal.
Preferably, when the peak current signal is between the minimum value and the maximum value, in order to ensure that the value of the valley number latch signal is stable without generating a jump, the value of the valley number latch signal is determined to be decreased by 1, and the hysteresis time is used to keep the value of the valley number latch signal stable.
Preferably, in the updating time interval, if the first valley count value is greater than or equal to the value of the valley count latch signal plus 1 in all PWM periods, that is, Nv _ lim1 ≦ (Nv _ lock +1) is always satisfied, and one of the PWM periods satisfies that the first valley count value is equal to the value of the valley count latch signal plus 1, that is, Nv _ lim1 ≦ (Nv _ lock +1), which indicates that the time length of the current dead time is not sufficient, then when the updating time interval arrives, the dead time + resolution, that is, Tdv + t is performed, where t is the resolution at which the dead time is performed once each time.
The invention has the technical effects that: the invention relates to a quasi-resonance switch power supply controller based on valley bottom locking, which comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) on judgment logic unit, a PWM off judgment logic unit, a PWM generation unit and a driver, wherein the valley bottom detection unit is used for detecting the valley bottom of a switch; aiming at different load conditions of the switching power supply, the controller adjusts the peak current signal current to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application conditions, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.
Drawings
FIG. 1 is a circuit diagram of one embodiment of a quasi-resonant switching power supply based on valley locking;
FIG. 2 is a periodic waveform diagram based on the embodiment of FIG. 1;
FIG. 3 is a bottom-jump waveform without bottom-lock at constant load based on the embodiment of FIG. 1;
FIG. 4 is a schematic diagram of an embodiment of a controller for a quasi-resonant switching power supply of the present invention;
FIG. 5 is a circuit diagram of a valley lock unit of another embodiment of the controller for a quasi-resonant switching power supply of the present invention;
FIG. 6 is a graph of a peak current signal versus a feedback signal for another embodiment of a controller for a quasi-resonant switching power supply in accordance with the present invention;
FIG. 7 is a timing diagram of a PWM switching cycle operating waveform of another embodiment of the controller for a quasi-resonant switching power supply of the present invention;
FIG. 8 is a timing diagram of the operating waveforms of another embodiment of the controller for a quasi-resonant switching power supply of the present invention when the load is reduced;
fig. 9 is a timing diagram of an operation waveform of another embodiment of the controller for a quasi-resonant switching power supply according to the present invention when a load is increased.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It is noted that unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains, the terms used in the description of the present invention are for the purpose of describing particular embodiments only and are not intended to limit the present invention, the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items, fig. 1 is a schematic diagram of a preferred quasi-resonant switching power supply embodiment, the switching power supply includes a transformer T1, the transformer T1 includes a primary winding, an auxiliary winding, and a secondary winding, a transformer primary side excitation inductor L m between a first input terminal and a second input terminal of the primary winding, I L m is a current flowing through the transformer primary side excitation inductor L m, an input voltage Vin is connected to the first input terminal of the primary winding, a power switch K1 and a sampling resistor Rcs for detecting current flowing through the primary winding Rcs, a second input terminal of the primary winding is connected in series with a negative terminal of a sampling switch C, a second input terminal of the primary winding is connected in series with a rectifying output terminal of a rectifying diode for detecting a signal, a second output terminal of the transformer K is connected with a rectifying output terminal of a rectifying switch dc-dc converter, a rectifying switch dc output terminal dc-dc converter dc output terminal dc-dc converter is connected to a rectifying switch, a rectifying switch dc output terminal dc-dc output terminal dc-dc output terminal dc-dc converter, a dc converter dc-.
Further, based on the circuit shown in fig. 1, as shown in fig. 2, where Tlim is a voltage signal for setting a minimum switching period, and voltage signal OC is a voltage signal at the second input end of the primary winding, current I L m flowing through primary side excitation inductor L m is controlled by feedback signal FB according to the magnitude of load Rload, when load Rload is large, transformer primary side excitation inductor L m needs to store more energy, i.e., peak signal Ipk of current I L m is large, inductor L m has longer energy storage time (time when PWM is active high), and the discharge time of the transformer secondary winding is also longer, if the first valley of voltage signal OC occurs after the minimum switching period Tlim ends, PWM of the next period is conducted at the first valley, as shown in fig. 2, if the load is small, peak signal Ipk of I L m becomes small, the charge and discharge period of the transformer is shortened, if the first valley of voltage signal OC occurs before the minimum switching period Tlim ends, the next PWM period is started after the first valley of voltage signal OC 2 starts to be started, as shown in fig. 5.
Further, as shown in fig. 3, in the case of some constant loads, if the first valley bottom of the voltage signal OC occurs near the end of the minimum switching period Tlim period, including the first valley bottom occurring before the end of the minimum switching period Tlim, such as the first minimum switching period Tlim and the third minimum switching period Tlim in fig. 3, and the valley bottom occurring after the end of the minimum switching period Tlim, such as the second minimum switching period Tlim in fig. 3, the number of valley bottoms at the time of switching-on of the switching tube jumps between two adjacent minimum switching periods Tlim, which results in jumping of the PWM switching period. Since such a hopping frequency generates noise if it is within the audible range of human ears, it is necessary to add a valley-lock method to the controller of the quasi-resonant switching power supply to avoid the occurrence of the valley-hopping frequency.
Preferably, as shown in fig. 4, a preferred embodiment of a controller for a quasi-resonant switching power supply is provided. The controller comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) opening judgment logic unit, a PWM closing judgment logic unit, a PWM generation unit and a driver. Preferably, the Valley bottom detecting unit is connected to a first input end AUX of an auxiliary winding of the switching power supply in fig. 1, and is used for indirectly detecting a voltage signal OC at a common terminal of a second input end of a primary winding of the transformer and a power switch tube K1 through a transformer coupling relationship, so as to perform Valley bottom detection on the voltage signal OC, the Valley bottom counting unit counts Valley bottom detection signals Valley from the Valley bottom detecting unit, and outputs Valley bottom counting signals Nv _ cur to the Valley bottom locking unit and the PWM on judgment logic unit respectively; the Valley bottom locking unit is connected with a Valley bottom detection signal Valley from the Valley bottom detection unit and also connected with an output voltage detection signal, namely a feedback signal FB, from a feedback loop of a switching power supply in the figure 1, and respectively outputs a Valley bottom number latching signal Nv _ lock and a minimum switching period signal Tlim to the PWM opening judgment logic unit, and the PWM opening judgment logic unit outputs a PWM opening signal Pwm _ on to the PWM generating unit; the valley bottom locking unit also outputs a peak current signal Ipk to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit is also connected with a current sampling signal flowing through a power switch tube in the switching power supply in the figure 1, namely, the PWM turn-off judgment logic unit is connected with an electric connection part CS of the power switch tube K1 and a sampling resistor Rcs and is used for sampling and inputting current IRcs flowing through the sampling resistor Rcs, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal Pwm _ off to the PWM generating unit; the PWM generating unit correspondingly generates and outputs a low-level or high-level control signal Pwmd to the driver according to the PWM turn-off signal or the PWM turn-on signal; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.
Further, as shown in fig. 5, a preferred embodiment of the valley bottom locking unit is given. The valley bottom locking unit is the core of the controller and mainly comprises two functions, namely outputting a peak current signal Ipk according to a feedback signal FB and generating a valley bottom latching signal Nv _ lock.
Preferably, the valley bottom locking unit includes a limit frequency generator, a first latch, a valley bottom number latch regulator, and a peak current signal generator. The limiting frequency generator generates and outputs a minimum switching period signal Tlim to a first latch, namely an Nv _ lim1 latch, is used for recording the count value of a valley bottom count signal Nv _ cur when the first valley bottom after the minimum switching period signal Tlim reaches, is defined as a first valley bottom count value Nv _ lim1, is input to a valley bottom number latch regulator, namely an Nv _ lock regulator, and generates and outputs a valley bottom number latch signal Nv _ lock; the peak current signal generator detects the input voltage detection signal FB and outputs a peak current signal Ipk in response thereto.
Further, the valley bottom locking unit further comprises an update timer, a filter timer, a time delay adjuster and a second latch. Wherein, the refresh timer, i.e. Twin timer, generates an output refresh time interval signal Twin to the time delay adjuster as the refresh time interval for generating the valley bottom number latch signal Nv _ lock; the filtering timer, namely a Tlt timer, finishes the transient response to the valley bottom number latch signal Nv _ lock, generates an output filtering time signal Tlt and inputs the output filtering time signal Tlt to the Twin timer; the time delay regulator, i.e., the Tdv regulator, is clocked from the minimum switching period Tlim to a lag time that prevents valley jump, which is adaptively adjusted by a correlation algorithm, as described in further detail below. The time delay regulator outputs a dead time signal Tdv to the second latch; the second latch, i.e., Nv _ lim2 latch, is used for recording the count value of the valley bottom count signal Nv _ cur when the first valley bottom arrives after the dead time signal Tdv arrives, which is defined as the second valley bottom count value, and is input to the valley bottom count latch regulator, i.e., Nv _ lock regulator.
Preferably, fig. 5 further includes a feedback signal FB interval determiner for performing interval identification determination on the input feedback signal FB, and outputting an interval identification signal to the valley number locking regulator, i.e., the Nv _ lock regulator, for example, in conjunction with fig. 6, the interval identification signal includes an FB _ GT _ H identification signal greater than the FB _ H signal, an FB _ L T _ L identification signal less than the FB _ L signal, and an FB _ GT _ MAX identification signal greater than the FB _ MAX signal.
Further preferably, with reference to fig. 4 and 5, for the PWM on judgment logic unit, after the minimum switching period signal Tlim arrives, if Nv _ cur is greater than or equal to Nv _ lock, the PWM on signal PWM _ on is immediately generated; for the PWM off judgment logic unit, which includes a comparator, when the Rcs current detected by the CS terminal in fig. 4 is greater than Ipk, a PWM off signal PWM _ off is generated for turning off the PWM.
Preferably, for the peak current signal generator in fig. 5, the linear proportional conversion between the peak current signal Ipk and the feedback signal FB is mainly accomplished, as shown in fig. 6, the peak current signal Ipk and the feedback signal FB are in a linear proportional relationship in the interval of [ FB _ min, FB _ max ], corresponding to the operating interval of the peak current signal Ipk [ Ipk _ min, Ipk _ max ], and in practical applications, it needs to be mentioned that there are two feedback loops of the switching power supply, one is the larger the load, the larger the feedback signal FB, the larger the load, the smaller the feedback FB, here, only the first feedback loop is used for explaining, and if the second feedback loop is encountered, the condition that changes with the FB is changed at once, the FB _ max in fig. 6 is an internal signal of the valley bottom locking unit in fig. 5, corresponding to the maximum on-peak current Ipk _ max on the primary side, the FB _ min is an internal signal of the valley locking unit in fig. 5, corresponding to the minimum on-peak current signal Ipk _ max on the primary side, the valley locking unit is corresponding to the internal signal Ipk 35k _ H84, and the peak value of the valley locking unit is equal to the internal peak H _ H.
Fig. 7, in conjunction with fig. 4 and 5, further illustrates one embodiment of the PWM switching cycle duty waveform of the controller. Resonance is generated after demagnetization of the transformer is finished, a Valley bottom detection unit outputs a Valley bottom detection signal Valley signal after detecting the Valley bottom of the voltage signal OC, and a narrow pulse signal is output when a primary Valley bottom of the voltage signal OC is detected as shown in FIG. 7; the Valley bottom counting unit starts to count the number of the Valley bottoms according to the Valley bottom detection signal Valley and outputs a Valley bottom counting signal Nv _ cur, and the counting is recovered to 0 again after counting from 0 to 5. The first latch Nv _ lim1 records a corresponding valley bottom count signal Nv _ cur when the first valley bottom appears after the minimum switching period Tlim ends, i.e., a first valley bottom count value, which is shown as 3 in fig. 7, and the second latch Nv _ lim2 records a corresponding valley bottom count signal Nv _ cur when the first valley bottom appears after the delay time Tdv arrives, i.e., a second valley bottom count value, which is shown as 4 in fig. 7; meanwhile, after the minimum switching period Tlim is reached, if the valley bottom count signal Nv _ cur corresponding to the first latch is not less than the valley bottom number latch value Nv _ lock, when the corresponding valley bottom count signal Nv _ cur in fig. 7 is 5, the valley bottom count signal Nv _ cur is equal to the valley bottom number latch value Nv _ lock, and a Pwm _ on signal is output for turning on Pwm, and it is shown in fig. 7 that the Pwm signal is changed from a low level to a high level; after the PWM is turned on, the current CS flowing through the Rcs is detected, and when the CS reaches the peak current signal Ipk, the PWM is immediately turned off, and the PWM signal is changed from high level to low level.
Further preferably, as shown in fig. 8, when the load of the switching power supply is large, the peak current signal Ipk is between the minimum value Ipk _ L and the maximum value Ipk _ max, if the load is reduced, the peak current signal Ipk is reduced, the transformer excitation inductance one charge-discharge cycle is shortened, the position where the valley bottom of the voltage signal OC starts to appear is shifted to the left, and within the update time interval Twin, as long as one PWM cycle detects that the first valley bottom count value is greater than the value of the valley bottom number latch signal, that is, Nv _ lim1> Nv _ lock, as shown in fig. 8 corresponding to the second minimum switching cycle Tlim, the first valley bottom count value Nv _ lim1 is 3, and the valley number latch value Nv _ lock is 2, when the update time interval Twin arrives, the value Nv _ lock +1 of the valley number latch signal is equal to 3, and at this time, the next PWM _ on is satisfied.
Further, as shown in fig. 9, if the load is increased, the peak current signal Ipk is increased, the primary charge-discharge period of the transformer exciting inductor is lengthened, the position of the valley bottom where the voltage signal OC starts to appear is shifted to the right, and if all PWM periods satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, within the time of the update time interval Twin, the value Nv _ lock of the valley bottom number latch signal is decreased by 1 when the update time interval Twin arrives, as shown in fig. 9.
Further, the system will generate transient fluctuation every time the value Nv _ lock of the valley number latch signal is reduced by 1, and at this time, a filter timer, i.e., a Tflt timer, is started to filter out the change of the value Nv _ lock of the valley number latch signal caused by the transient fluctuation. Before the Tflt timer reaches the timing, the value of the valley number latch signal Nv _ lock is kept unchanged, the change condition of Nv _ lock is not enabled to be detected, and after the Tflt timer is finished, the updating timer, namely the Twin timer, is restarted, and the detection of the change condition of Nv _ lock is started.
Meanwhile, when the peak current signal Ipk is between the minimum value Ipk _ L and the maximum value Ipk _ max, in order to ensure that the value Nv _ lock of the valley bottom number latch signal can be stable and does not generate a jump, when the value Nv _ lock is determined to be reduced by 1, the hysteresis time Tdv is used, Tdv plays a key role in keeping the value Nv _ lock of the valley bottom number latch signal stable, and due to different system application conditions, the resonance period is different, and if the hysteresis time Tdv is too short, the valley bottom can still not be locked when the valley bottom is switched, so that the method for adaptively adjusting the hysteresis time is invented, and specifically comprises the following steps:
during the time of the update time interval Twin, if it is always true that Nv _ lim1 ≦ (Nv _ lock +1) is satisfied in all PWM periods, and one of the PWM periods satisfies Nv _ lim1 ≦ (Nv _ lock +1), indicating that the time length of the current hysteresis time Tdv is not sufficient, Tdv + t is executed when the update time interval Twin arrives, where t is the resolution of one time increment executed each time by Tdv.
When the load of the switching power supply is reduced and the peak current signal Ipk current is reduced below Ipk _ L, if the feedback signal FB is smaller than the minimum value FB _ L of the working interval of the feedback signal, i.e., FB < FB _ L, during the update time interval Twin, the value of the valley number latch signal Nv _ lock is increased by 1 when the update time interval Twin is reached, if the peak current signal Ipk current is increased above Ipk _ H, the load is increased, and when the feedback signal FB is greater than the maximum value FB _ H of the working interval of the feedback signal, i.e., FB > FB _ H, during the update time interval Twin, the value of the valley number latch signal Nv _ lock is decreased by 1 when the update time interval Twin is reached, so that the peak current signal Ipk current is stabilized within the small interval of Ipk _ L and Ipk _ H, and the dynamic adjustment of the valley number latch signal Ipk current is adjusted to maintain the peak value of the valley number latch signal ipv _ lock within the range of the valley number ipv _ 36k, and the peak number latch signal ipv is maintained within the range of the valley number latch frequency range of the valley number of Ipk is not increased, when the peak current signal ipv _ 36k is maintained, and the valley number of the valley number latch signal ipv _ lock is not increased, i.e., the valley number of the valley number latch signal ipv _ n _ lock signal ipv _ L is maintained within the valley number of the.
Further preferably, in order to cope with the situation that a quick response is required for a sudden load change, the number of locking valleys may be changed quickly according to the following rule:
(1) if it is detected that the first valley count value is less than the value of the valley count latch signal minus 3, i.e., Nv _ lim1< (Nv _ lock-3), then the value of the valley count latch signal Nv _ lock minus 1 is performed immediately.
(2) If it is detected that the feedback signal is greater than the feedback maximum value, i.e., FB > FB _ max, then the value of the execution valley number latch signal Nv _ lock is immediately updated to the first valley count value Nv _ lim 1.
Therefore, the invention relates to a quasi-resonance switch power supply controller based on valley bottom locking, which comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) switching-on judgment logic unit, a PWM switching-off judgment logic unit, a PWM generation unit and a driver, wherein the valley bottom detection unit is used for detecting the valley bottom of a switch; aiming at different load conditions of the switching power supply, the controller adjusts the peak signal current to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application condition, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A quasi-resonance switch power supply controller based on valley bottom locking is characterized in that the power supply controller comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) opening judgment logic unit, a PWM closing judgment logic unit, a PWM generation unit and a driver; the valley bottom detection unit is connected to a first input end of an auxiliary winding of the switching power supply and used for inputting detection voltage signals of the auxiliary winding of the transformer and detecting valley bottoms, and the valley bottom counting unit counts the valley bottom detection signals from the valley bottom detection unit, outputs valley bottom counting signals and then respectively outputs the valley bottom counting signals to the valley bottom locking unit and the PWM switching-on judgment logic unit; the valley bottom locking unit is connected with a valley bottom detection signal from the valley bottom detection unit and a voltage detection signal output by a feedback loop of the switching power supply, and respectively outputs a valley bottom number locking signal and a minimum switching period signal to the PWM opening judgment logic unit, and the PWM opening judgment logic unit further outputs a PWM opening signal to the PWM generation unit; the valley bottom locking unit also outputs a peak current signal to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit also accesses a current sampling signal flowing through a power switch tube in the switch power supply, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal to the PWM generating unit; the PWM generating unit correspondingly generates a low-level or high-level control signal according to the PWM turn-off signal or the PWM turn-on signal and outputs the low-level or high-level control signal to the driver; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.
2. The quasi-resonant switching power supply controller based on valley bottom locking according to claim 1, wherein the valley bottom locking unit comprises a limit frequency generator, a first latch, a valley bottom number latch regulator and a peak current signal generator, wherein the limit frequency generator outputs a minimum switching cycle signal to the first latch, the first latch is used for recording a count value of a valley bottom count signal when a first valley bottom after the minimum switching cycle signal arrives, the count value is defined as a first valley bottom count value and is input to the valley bottom number latch regulator, and the valley bottom number latch regulator outputs a valley bottom number latch signal; the peak current signal generator detects the input feedback voltage detection signal and correspondingly outputs a peak current signal.
3. The valley-lock based quasi-resonant switching power supply controller of claim 2, wherein the valley-lock unit further comprises an update timer, a filter timer, a time delay adjuster, and a second latch; the updating timer generates an output updating time signal to the time delay regulator to serve as an updating time interval for generating the valley bottom latching signal; the filtering timer completes transient response to the valley bottom number latching signal, generates an output filtering time signal and inputs the output filtering time signal into the updating timer; the time delay regulator starts timing from the minimum switching period to prevent the lag time of valley bottom jumping, and outputs a lag time signal to the second latch; and the second latch is used for recording the count value of the corresponding valley bottom counting signal when the first valley bottom of the lag time is reached, defining the count value as a second valley bottom count value, and inputting the second valley bottom count value into the valley bottom number latch regulator.
4. The bottom-locking based quasi-resonant switching power supply controller of claim 3, wherein the bottom-locking unit further comprises a feedback signal interval determiner for performing interval identification determination on the input feedback signal, and outputting an interval identification signal to the bottom-number locking adjuster correspondingly.
5. The quasi-resonant switching power supply controller based on valley bottom locking according to claim 4, characterized in that for the PWM turn-on judging logic unit, after the minimum switching period signal arrives, if the value of the valley bottom counting signal is greater than or equal to the value of the valley bottom number locking signal, i.e. Nv _ cur is greater than or equal to Nv _ lock, the PWM turn-on signal is immediately generated to turn on PWM; and the PWM turn-off judgment logic unit comprises a comparator, and when the switching power supply detects that the current flowing through the sampling resistor is greater than the set value of the peak current signal, the PWM turn-off judgment logic unit generates a PWM turn-off signal to turn off the PWM.
6. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 5, wherein when the load of the switching power supply is reduced, the peak current signal is reduced, the primary charge-discharge cycle of the transformer exciting inductance is shortened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the left, and within the updating time interval, as long as one PWM cycle detects that the first valley bottom count value is larger than the value of the valley bottom number latch signal, i.e. Nv _ lim1> Nv _ lock, when the updating time interval arrives, the value of the valley bottom number latch signal is added by 1.
7. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 6, wherein when the load of the switching power supply is increased, the peak current signal is increased, the one-time charge-discharge cycle of the transformer exciting inductor is lengthened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the right, and in the updating time interval, if all PWM cycles satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, the value of the valley bottom number latch signal is decreased by 1 when the updating time interval arrives.
8. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 7, wherein the system generates transient fluctuation every time the value of the valley bottom number latch signal is decreased by 1, at this time, the filter timer is started to filter out the value change of the valley bottom number latch signal caused by the transient fluctuation, before the timing of the filter timer is reached, the value of the valley bottom number latch signal is kept unchanged and the change condition of the valley bottom number latch signal is not enabled to be detected, after the filter timer is finished, the update timer is restarted to start the detection of the change condition of the valley bottom number latch signal.
9. The bottom-of-valley locking based quasi-resonant switching power supply controller of claim 8, wherein when the peak current signal is between the minimum and maximum values, to ensure the value of the bottom-of-valley number latch signal is stable without generating a jump, the value of the bottom-of-valley number latch signal is determined to be decreased by 1, using a dead time to keep the value of the bottom-of-valley number latch signal stable.
10. The bottom-locking based quasi-resonant switching power supply controller of claim 9, characterized in that in the time of the update time interval, if the first bottom count value is satisfied in all PWM periods with the value of the bottom number latch signal being greater than or equal to 1 plus the value of the bottom number latch signal, i.e., Nv _ lim1 ≦ n (Nv _ lock +1) is always true, and wherein in one PWM period, the first bottom count value is satisfied with the value of the bottom number latch signal plus 1, i.e., Nv _ lim1 ═ n (Nv _ lock +1), which indicates that the time length of the current dead time is not sufficient, then when the update time interval arrives, dead time + resolution, i.e., Tdv + t, is performed, where t is the resolution of one time increment per dead time of dead time.
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