CN211981752U - Quasi-resonance switch power supply controller based on valley bottom locking - Google Patents

Abstract

The utility model relates to a quasi-resonance switch power supply controller based on bottom of a valley locking, including bottom of a valley detecting element, bottom of a valley counting element, bottom of a valley locking element, PWM opens and judges logical unit, PWM turn-off and judges logical unit, PWM production unit and driver; aiming at different load conditions of the switching power supply, the controller adjusts the peak current signal to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application condition, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.

Description

Quasi-resonance switch power supply controller based on valley bottom locking

Technical Field

The utility model belongs to the technical field of the power, concretely relates to accurate resonance switch power supply controller based on locking of millet bottom.

Background

Compared with a linear power supply, the switching power supply has the advantages of easiness in control, high efficiency, small size, good reliability and easiness in protection, and is widely applied to equipment such as television power supplies, mobile phone chargers, LEDs, industrial instruments, power adapters and the like. Increasing the switching frequency is an important direction in the development of switching power supply technology. The volume and the weight of the switching converter can be reduced by improving the working frequency of the switch, and the power density of the unit volume of the switching converter is improved. In addition, increasing the switching frequency also reduces the audio noise of the switching power supply and improves the dynamic response. However, higher switching frequencies result in greater switching losses. Therefore, in order to realize higher working frequency, the quasi-resonance control technology can be adopted to realize high-frequency soft switching, namely zero-voltage switching-off and low-voltage switching-on of the power tube, so as to reduce the switching loss.

In the prior art, the quasi-resonance control technology used for the switching power supply has the main disadvantages that the switching frequency is not fixed, especially when the switching frequency is high at high input voltage and light load, on one hand, the switching frequency is limited by a power switch device, and on the other hand, the high switching frequency means larger switching loss, so that the power supply conversion efficiency is reduced and the advantage of valley bottom switching-on is offset. Therefore, in practical application, the highest switching frequency, i.e. the shortest switching period, is set, and if the preset valley bottom occurs in the shortest switching period, the valley bottom conduction is delayed until the valley bottom is allowed to be turned on after the shortest switching period is reached. Under different load conditions, the valley bottom number of the power tube when being switched on is different, even if the same load is carried out, the power tube can be switched on back and forth by two adjacent valley bottoms due to real-time control of the feedback loop, the switching frequency is not fixed, and when the switching frequency is within the hearing range of human ears, audio noise can appear.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem provide a quasi-resonance switch power supply controller based on locking of millet end, under the different load condition that switch power supply exists among the solution prior art, the millet end number when the power tube is opened can not self-adaptation change and be difficult to the problem of remain stable to and there is switching frequency unfixed under the same load condition, the problem of audio noise appears.

In order to solve the technical problem of the utility model, a quasi-resonance switch power supply controller based on valley bottom locking is provided, which comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) switching-on judgment logic unit, a PWM switching-off judgment logic unit, a PWM generation unit and a driver; the valley bottom detection unit is connected to a first input end of an auxiliary winding of the switching power supply and used for inputting detection voltage signals of the auxiliary winding of the transformer and detecting valley bottoms, and the valley bottom counting unit counts the valley bottom detection signals from the valley bottom detection unit, outputs valley bottom counting signals and then respectively outputs the valley bottom counting signals to the valley bottom locking unit and the PWM switching-on judgment logic unit; the valley bottom locking unit is connected with a valley bottom detection signal from the valley bottom detection unit and a voltage detection signal output by a feedback loop of the switching power supply, and respectively outputs a valley bottom number locking signal and a minimum switching period signal to the PWM opening judgment logic unit, and the PWM opening judgment logic unit further outputs a PWM opening signal to the PWM generation unit; the valley bottom locking unit also outputs a peak current signal to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit also accesses a current sampling signal flowing through a power switch tube in the switch power supply, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal to the PWM generating unit; the PWM generating unit correspondingly generates a low-level or high-level control signal according to the PWM turn-off signal or the PWM turn-on signal and outputs the low-level or high-level control signal to the driver; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.

Preferably, the valley bottom locking unit includes a limit frequency generator, a first latch, a valley bottom number latch adjuster and a peak current signal generator, wherein the limit frequency generator outputs a minimum switching cycle signal to the first latch, the first latch is configured to record a count value of a valley bottom count signal when a first valley bottom arrives after the minimum switching cycle signal arrives, the count value is defined as a first valley bottom count value, the first valley bottom count value is input to the valley bottom number latch adjuster, and the valley bottom number latch adjuster outputs the valley bottom number latch signal; the peak current signal generator detects the input feedback voltage detection signal and correspondingly outputs a peak current signal.

Preferably, the valley bottom locking unit further comprises an update timer, a filter timer, a time delay adjuster and a second latch; the updating timer generates an output updating time signal to the time delay regulator to serve as an updating time interval for generating the valley bottom latching signal; the filtering timer completes transient response to the valley bottom number latching signal, generates an output filtering time signal and inputs the output filtering time signal into the updating timer; the time delay regulator starts timing from the minimum switching period to prevent the lag time of valley bottom jumping, and outputs a lag time signal to the second latch; and the second latch is used for recording the count value of the corresponding valley bottom counting signal when the first valley bottom of the lag time is reached, defining the count value as a second valley bottom count value, and inputting the second valley bottom count value into the valley bottom number latch regulator.

Preferably, the valley bottom locking unit further includes a feedback signal interval judger for performing interval identification judgment on the input feedback signal and outputting an interval identification signal to the valley bottom number locking adjuster correspondingly.

Preferably, for the PWM on judgment logic unit, after the minimum switching period signal arrives, if the value of the valley bottom counting signal is greater than or equal to the value of the valley bottom number latching signal, i.e. Nv _ cur is greater than or equal to Nv _ lock, the PWM on signal is immediately generated to turn on PWM; and the PWM turn-off judgment logic unit comprises a comparator, and when the switching power supply detects that the current flowing through the sampling resistor is greater than the set value of the peak current signal, the PWM turn-off judgment logic unit generates a PWM turn-off signal to turn off the PWM.

Preferably, when the load of the switching power supply is reduced, the peak current signal is reduced, the primary charge-discharge cycle of the transformer excitation inductor is shortened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the left, and within the updating time interval, as long as one PWM cycle detects that the first valley bottom count value is greater than the value of the valley bottom latching signal, that is, Nv _ lim1> Nv _ lock, the value of the valley bottom latching signal is increased by 1 when the updating time interval arrives.

Preferably, when the load of the switching power supply is increased, the peak current signal is increased, the primary charge-discharge cycle of the transformer excitation inductor is lengthened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the right, and in the updating time interval, if all PWM cycles satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, the value of the valley bottom number latch signal is decreased by 1 when the updating time interval arrives.

Preferably, the system generates transient fluctuation every time the value of the valley bottom number latch signal is reduced by 1, at this time, a filtering timer is started to filter out the value change of the valley bottom number latch signal caused by the transient fluctuation, before the timing of the filtering timer is reached, the value of the valley bottom number latch signal is kept unchanged, the change condition of the valley bottom number latch signal cannot be detected, and after the filtering timer is ended, the updating timer is restarted to start the detection of the change condition of the valley bottom number latch signal.

Preferably, when the peak current signal is between the minimum value and the maximum value, in order to ensure that the value of the valley number latch signal is stable without generating a jump, the value of the valley number latch signal is determined to be decreased by 1, and the hysteresis time is used to keep the value of the valley number latch signal stable.

Preferably, in the updating time interval, if the first valley count value is greater than or equal to the value of the valley count latch signal plus 1 in all PWM periods, that is, Nv _ lim1 ≦ (Nv _ lock +1) is always satisfied, and one of the PWM periods satisfies that the first valley count value is equal to the value of the valley count latch signal plus 1, that is, Nv _ lim1 ≦ (Nv _ lock +1), which indicates that the time length of the current dead time is not sufficient, then when the updating time interval arrives, the dead time + resolution, that is, Tdv + t is performed, where t is the resolution at which the dead time is performed once each time.

The technical effects of the utility model are that: the utility model relates to a quasi-resonance switch power supply controller based on bottom of a valley locking, including bottom of a valley detecting element, bottom of a valley counting element, bottom of a valley locking element, PWM opens and judges logical unit, PWM turn-off and judges logical unit, PWM production unit and driver; aiming at different load conditions of the switching power supply, the controller adjusts the peak current signal current to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application conditions, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.

Drawings

FIG. 1 is a circuit diagram of one embodiment of a quasi-resonant switching power supply based on valley locking;

FIG. 2 is a periodic waveform diagram based on the embodiment of FIG. 1;

FIG. 3 is a bottom-jump waveform without bottom-lock at constant load based on the embodiment of FIG. 1;

fig. 4 is a schematic diagram of an embodiment of a controller for a quasi-resonant switching power supply according to the present invention;

fig. 5 is a circuit diagram of a valley locking unit of another embodiment of the controller for a quasi-resonant switching power supply of the present invention;

fig. 6 is a graph of a peak current signal versus a feedback signal for another embodiment of a controller for a quasi-resonant switching power supply of the present invention;

fig. 7 is a timing diagram of a PWM switching cycle waveform for another embodiment of a controller for a quasi-resonant switching power supply of the present invention;

fig. 8 is a timing diagram of an operation waveform of another embodiment of the controller for a quasi-resonant switching power supply according to the present invention when the load is reduced;

fig. 9 is a timing diagram of an operation waveform of another embodiment of the controller for the quasi-resonant switching power supply according to the present invention when the load is increased.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described in more detail with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It is to be noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Fig. 1 is a schematic diagram of a preferred embodiment of a quasi-resonant switching power supply. The switching power supply comprises a transformer T1, wherein the transformer T1 comprises a primary winding, an auxiliary winding and a secondary winding, a primary side excitation inductor Lm of the transformer is arranged between a first input end and a second input end of the primary winding, ILm is current flowing through the primary side excitation inductor Lm of the transformer, an input voltage Vin is connected to the first input end of the primary winding, a power switch tube K1 and a sampling resistor Rcs for detecting current flowing through the primary winding are connected in series between the second input end and a grounding end of the primary winding, and an equivalent capacitance between the second input end and the grounding end of the primary winding is C1 (fig. 1 is correspondingly modified); the first output end of the secondary winding is connected with the positive end of a rectifier diode D, the negative end of the rectifier diode D outputs voltage Vout corresponding to output current Iout, an energy storage capacitor C2 and a load Rload are connected in parallel between the negative end of the rectifier diode D and the second output end of the secondary winding, and the second output end of the secondary winding is grounded GND; the negative end of the rectifier diode D is also connected with a feedback loop, and the feedback loop detects the output voltage Vout and outputs a feedback signal FB to the controller; the controller is also electrically connected with a first input end AUX of the auxiliary winding, and is used for indirectly detecting a second input end of the primary winding of the transformer and a common terminal voltage signal OC of the power switch tube K1 through a transformer coupling relation; and an electric connection part CS electrically connected with the power switch tube K1 and the sampling resistor Rcs and used for sampling current IRcs flowing through the sampling resistor Rcs, and the controller outputs a PWM signal and is used for controlling the power switch tube K1 to be switched on and off.

Further, based on the circuit shown in fig. 1, as shown in fig. 2, where Tlim is a set minimum switching period, the voltage signal OC is a voltage signal of the second input terminal of the primary winding, and the current ILm flowing through the primary side excitation inductor Lm is controlled by the feedback signal FB according to the magnitude of the load Rload. When the load Rload is large, the transformer primary side excitation inductor Lm needs to store more energy, that is, the peak signal Ipk of the current ILm is large, the inductor Lm has a longer energy storage time (the time when the PWM is at the active high level), and the discharge time of the transformer secondary winding is also long, and if the first valley bottom of the voltage signal OC occurs after the end of the minimum switching period Tlim, the PWM of the next period is turned on at the first valley bottom, as shown in the 1 st PWM period in fig. 2. If the load becomes smaller, the peak signal Ipk of ILm becomes smaller, and one charge-discharge cycle of the transformer is shortened, and if the first valley of the voltage signal OC occurs before the end of the minimum switching period Tlim, the PWM of the next cycle needs to wait for the first valley to be turned on after the end of the minimum switching period Tlim, as shown in fig. 2 from the 2 nd to the 5 th PWM periods.

Further, as shown in fig. 3, in the case of some constant loads, if the first valley bottom of the voltage signal OC occurs near the end of the minimum switching period Tlim period, including the first valley bottom occurring before the end of the minimum switching period Tlim, such as the first minimum switching period Tlim and the third minimum switching period Tlim in fig. 3, and the valley bottom occurring after the end of the minimum switching period Tlim, such as the second minimum switching period Tlim in fig. 3, the number of valley bottoms at the time of switching-on of the switching tube jumps between two adjacent minimum switching periods Tlim, which results in jumping of the PWM switching period. Since such a hopping frequency generates noise if it is within the audible range of human ears, it is necessary to add a valley-lock method to the controller of the quasi-resonant switching power supply to avoid the occurrence of the valley-hopping frequency.

Preferably, as shown in fig. 4, a preferred embodiment of a controller for a quasi-resonant switching power supply is provided. The controller comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) opening judgment logic unit, a PWM closing judgment logic unit, a PWM generation unit and a driver. Preferably, the Valley bottom detecting unit is connected to a first input end AUX of an auxiliary winding of the switching power supply in fig. 1, and is used for indirectly detecting a voltage signal OC at a common terminal of a second input end of a primary winding of the transformer and a power switch tube K1 through a transformer coupling relationship, so as to perform Valley bottom detection on the voltage signal OC, the Valley bottom counting unit counts Valley bottom detection signals Valley from the Valley bottom detecting unit, and outputs Valley bottom counting signals Nv _ cur to the Valley bottom locking unit and the PWM on judgment logic unit respectively; the Valley bottom locking unit is connected with a Valley bottom detection signal Valley from the Valley bottom detection unit and also connected with an output voltage detection signal, namely a feedback signal FB, from a feedback loop of a switching power supply in the figure 1, and respectively outputs a Valley bottom number latching signal Nv _ lock and a minimum switching period signal Tlim to the PWM opening judgment logic unit, and the PWM opening judgment logic unit outputs a PWM opening signal Pwm _ on to the PWM generating unit; the valley bottom locking unit also outputs a peak current signal Ipk to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit is also connected with a current sampling signal flowing through a power switch tube in the switching power supply in the figure 1, namely, the PWM turn-off judgment logic unit is connected with an electric connection part CS of the power switch tube K1 and a sampling resistor Rcs and is used for sampling and inputting current IRcs flowing through the sampling resistor Rcs, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal Pwm _ off to the PWM generating unit; the PWM generating unit correspondingly generates and outputs a low-level or high-level control signal Pwmd to the driver according to the PWM turn-off signal or the PWM turn-on signal; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.

Further, as shown in fig. 5, a preferred embodiment of the valley bottom locking unit is given. The valley bottom locking unit is the core of the controller and mainly comprises two functions, namely outputting a peak current signal Ipk according to a feedback signal FB and generating a valley bottom latching signal Nv _ lock.

Preferably, the valley bottom locking unit includes a limit frequency generator, a first latch, a valley bottom number latch regulator, and a peak current signal generator. The limiting frequency generator generates and outputs a minimum switching period signal Tlim to a first latch, namely an Nv _ lim1 latch, is used for recording the count value of a valley bottom count signal Nv _ cur when the first valley bottom after the minimum switching period signal Tlim reaches, is defined as a first valley bottom count value Nv _ lim1, is input to a valley bottom number latch regulator, namely an Nv _ lock regulator, and generates and outputs a valley bottom number latch signal Nv _ lock; the peak current signal generator detects the input voltage detection signal FB and outputs a peak current signal Ipk in response thereto.

Further, the valley bottom locking unit further comprises an update timer, a filter timer, a time delay adjuster and a second latch. Wherein, the refresh timer, i.e. Twin timer, generates an output refresh time interval signal Twin to the time delay adjuster as the refresh time interval for generating the valley bottom number latch signal Nv _ lock; the filtering timer, namely a Tlt timer, finishes the transient response to the valley bottom number latch signal Nv _ lock, generates an output filtering time signal Tlt and inputs the output filtering time signal Tlt to the Twin timer; the time delay regulator, i.e., the Tdv regulator, is clocked from the minimum switching period Tlim to a lag time that prevents valley jump, which is adaptively adjusted by a correlation algorithm, as described in further detail below. The time delay regulator outputs a dead time signal Tdv to the second latch; the second latch, i.e., Nv _ lim2 latch, is used for recording the count value of the valley bottom count signal Nv _ cur when the first valley bottom arrives after the dead time signal Tdv arrives, which is defined as the second valley bottom count value, and is input to the valley bottom count latch regulator, i.e., Nv _ lock regulator.

Preferably, fig. 5 further includes a feedback signal FB interval determiner, configured to perform interval identification determination on the input feedback signal FB, and output an interval identification signal to the valley number locking regulator, i.e., the Nv _ lock regulator. For example, in conjunction with fig. 6, the section identification signal includes an FB _ GT _ H identification signal greater than the FB _ H signal, an FB _ LT _ L identification signal less than the FB _ L signal, and an FB _ GT _ MAX identification signal greater than the FB _ MAX signal.

Further preferably, with reference to fig. 4 and 5, for the PWM on judgment logic unit, after the minimum switching period signal Tlim arrives, if Nv _ cur is greater than or equal to Nv _ lock, the PWM on signal PWM _ on is immediately generated; for the PWM off judgment logic unit, which includes a comparator, when the Rcs current detected by the CS terminal in fig. 4 is greater than Ipk, a PWM off signal PWM _ off is generated for turning off the PWM.

Preferably, the peak current signal generator in fig. 5 mainly performs a linear proportional conversion between the peak current signal Ipk and the feedback signal FB, as shown in fig. 6, the peak current signal Ipk and the feedback signal FB have a linear proportional relationship in the interval [ FB _ min, FB _ max ], which corresponds to the working interval [ Ipk _ min, Ipk _ max ] of the peak current signal Ipk. In addition, in practical applications, it should be noted that there are two feedback loops of the switching power supply, one is that the larger the load is, the larger the feedback signal FB is, and the other is that the larger the load is, the smaller the feedback FB is, and here, only the first feedback loop is used for illustration, and if the second feedback loop is encountered, it is only necessary to change the condition that varies with FB. FB _ max in fig. 6 is the internal signal of the valley-locked cell in fig. 5, corresponding to the primary side maximum on-peak current Ipk _ max; FB _ min is the internal signal of the valley-locked cell in fig. 5, corresponding to the primary side minimum on-peak current Ipk _ min; FB _ L is an internal signal of the valley bottom locking unit and corresponds to a primary side peak current Ipk _ L; FB _ H is an internal signal of the valley-locked cell, corresponding to the primary side peak current Ipk _ H.

Fig. 7, in conjunction with fig. 4 and 5, further illustrates one embodiment of the PWM switching cycle duty waveform of the controller. Resonance is generated after demagnetization of the transformer is finished, a Valley bottom detection unit outputs a Valley bottom detection signal Valley signal after detecting the Valley bottom of the voltage signal OC, and a narrow pulse signal is output when a primary Valley bottom of the voltage signal OC is detected as shown in FIG. 7; the Valley bottom counting unit starts to count the number of the Valley bottoms according to the Valley bottom detection signal Valley and outputs a Valley bottom counting signal Nv _ cur, and the counting is recovered to 0 again after counting from 0 to 5. The first latch Nv _ lim1 records a corresponding valley bottom count signal Nv _ cur when the first valley bottom appears after the minimum switching period Tlim ends, i.e., a first valley bottom count value, which is shown as 3 in fig. 7, and the second latch Nv _ lim2 records a corresponding valley bottom count signal Nv _ cur when the first valley bottom appears after the delay time Tdv arrives, i.e., a second valley bottom count value, which is shown as 4 in fig. 7; meanwhile, after the minimum switching period Tlim is reached, if the valley bottom count signal Nv _ cur corresponding to the first latch is not less than the valley bottom number latch value Nv _ lock, when the corresponding valley bottom count signal Nv _ cur in fig. 7 is 5, the valley bottom count signal Nv _ cur is equal to the valley bottom number latch value Nv _ lock, and a Pwm _ on signal is output for turning on Pwm, and it is shown in fig. 7 that the Pwm signal is changed from a low level to a high level; after the PWM is turned on, the current CS flowing through the Rcs is detected, and when the CS reaches the peak current signal Ipk, the PWM is immediately turned off, and the PWM signal is changed from high level to low level.

Further preferably, as shown in fig. 8, when the load of the switching power supply is large, the peak current signal Ipk is between the minimum value Ipk _ L and the maximum value Ipk _ max, if the load is reduced, the peak current signal Ipk is reduced, the transformer exciting inductance one charge-discharge cycle is shortened, the position of the valley bottom where the voltage signal OC starts to appear is shifted to the left, and as long as one PWM cycle detects that the first valley bottom count value is larger than the value of the valley bottom number latch signal, i.e. Nv _ lim1> Nv _ lock, as shown in fig. 8 corresponding to the second minimum switching cycle Tlim, the first valley bottom count value Nv _ lim1 is 3, and the valley bottom number latch value Nv _ lock is 2, when the update time interval Twin arrives, the value Nv _ lock +1 of the valley bottom number latch signal, therefore, when the valley bottom count signal Nv _ cur is 3, the value Nv _ lock is satisfied, the value Nv _ cur _ lock is equal to 3, because the Pwm _ on signal is output as long as Nv _ cur ≧ Nv _ lock is satisfied, the next PWM is turned on.

Further, as shown in fig. 9, if the load is increased, the peak current signal Ipk is increased, the primary charge-discharge period of the transformer exciting inductor is lengthened, the position of the valley bottom where the voltage signal OC starts to appear is shifted to the right, and if all PWM periods satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, within the time of the update time interval Twin, the value Nv _ lock of the valley bottom number latch signal is decreased by 1 when the update time interval Twin arrives, as shown in fig. 9.

Further, the system will generate transient fluctuation every time the value Nv _ lock of the valley number latch signal is reduced by 1, and at this time, a filter timer, i.e., a Tflt timer, is started to filter out the change of the value Nv _ lock of the valley number latch signal caused by the transient fluctuation. Before the Tflt timer reaches the timing, the value of the valley number latch signal Nv _ lock is kept unchanged, the change condition of Nv _ lock is not enabled to be detected, and after the Tflt timer is finished, the updating timer, namely the Twin timer, is restarted, and the detection of the change condition of Nv _ lock is started.

Meanwhile, when the peak current signal Ipk is between the minimum value Ipk _ L and the maximum value Ipk _ max, in order to ensure that the value Nv _ lock of the valley bottom number latch signal can be stable and does not generate a jump, when the value Nv _ lock is judged to be reduced by 1, the dead time Tdv is used, Tdv plays a key role in keeping the value Nv _ lock of the valley bottom number latch signal stable, due to different system application conditions, the resonance period is different, if the dead time Tdv is too short, the valley bottom can still not be locked when being switched, so the utility model discloses a dead time adaptive adjustment method, specifically as follows:

during the time of the update time interval Twin, if it is always true that Nv _ lim1 ≦ (Nv _ lock +1) is satisfied in all PWM periods, and one of the PWM periods satisfies Nv _ lim1 ≦ (Nv _ lock +1), indicating that the time length of the current hysteresis time Tdv is not sufficient, Tdv + t is executed when the update time interval Twin arrives, where t is the resolution of one time increment executed each time by Tdv.

When the load of the switching power supply is reduced and the current of the peak current signal Ipk is reduced to be lower than Ipk _ L, if all PWM periods meet the condition that the feedback signal FB is smaller than the minimum value FB _ L of the working interval of the feedback signal within the time of the updating time interval Twin, namely FB < FB _ L, when the updating time interval Twin arrives, the value of the valley number latch signal Nv _ lock is added with 1; if the peak current signal Ipk current rises above Ipk _ H, which indicates that the load is increased, all PWM cycles satisfy that the feedback signal FB is larger than the maximum value FB _ H of the working interval of the feedback signal, i.e. FB > FB _ H, within the time of the update time interval Twin, then the value of the valley number latch signal Nv _ lock is decreased by 1 when the update time interval Twin arrives, so that the peak current signal Ipk current can be stabilized within the small interval of Ipk _ L and Ipk _ H, and the valley number latch signal Nv _ lock can be dynamically adjusted according to the load change, the PWM working frequency can be indirectly adjusted, and the locking of the valley number latch signal Nv _ lock can be ensured. When the load continues to decrease and the valley count latch signal Nv _ lock has already been added to the maximum value Nv _ max, the peak current signal Ipk will not be maintained in the interval from Ipk _ L to Ipk _ H, and Ipk will stabilize in a range lower than Ipk _ L, at which time the valley count latch signal Nv _ lock is latched at the maximum value Nv _ max.

Further preferably, in order to cope with the situation that a quick response is required for a sudden load change, the number of locking valleys may be changed quickly according to the following rule:

(1) if it is detected that the first valley count value is less than the value of the valley count latch signal minus 3, i.e., Nv _ lim1< (Nv _ lock-3), then the value of the valley count latch signal Nv _ lock minus 1 is performed immediately.

(2) If it is detected that the feedback signal is greater than the feedback maximum value, i.e., FB > FB _ max, then the value of the execution valley number latch signal Nv _ lock is immediately updated to the first valley count value Nv _ lim 1.

Therefore, the utility model relates to a quasi-resonance switch power supply controller based on bottom of a valley locking, including bottom of a valley detecting element, bottom of a valley counting element, bottom of a valley locking element, PWM turn-on judge logic unit, PWM turn-off judge logic unit, PWM produce unit and driver; aiming at different load conditions of the switching power supply, the controller adjusts the peak signal current to adaptively adjust the valley bottom opening number by detecting voltage feedback, so as to realize the stability of the valley bottom locking value, and can also adaptively adjust the lag time and lock the valley bottom number according to the application condition, thereby ensuring that the valley bottom number required by the conduction of the switching power tube is rapidly changed along with the load, improving the dynamic performance of the switching power supply and avoiding the occurrence of audible noise of human ears.

The above only is the embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the same principle as the present invention.

Claims (10)

1. A quasi-resonance switch power supply controller based on valley bottom locking is characterized in that the power supply controller comprises a valley bottom detection unit, a valley bottom counting unit, a valley bottom locking unit, a PWM (pulse width modulation) opening judgment logic unit, a PWM closing judgment logic unit, a PWM generation unit and a driver; the valley bottom detection unit is connected to a first input end of an auxiliary winding of the switching power supply and used for inputting detection voltage signals of the auxiliary winding of the transformer and detecting valley bottoms, and the valley bottom counting unit counts the valley bottom detection signals from the valley bottom detection unit, outputs valley bottom counting signals and then respectively outputs the valley bottom counting signals to the valley bottom locking unit and the PWM switching-on judgment logic unit; the valley bottom locking unit is connected with a valley bottom detection signal from the valley bottom detection unit and a voltage detection signal output by a feedback loop of the switching power supply, and respectively outputs a valley bottom number locking signal and a minimum switching period signal to the PWM opening judgment logic unit, and the PWM opening judgment logic unit further outputs a PWM opening signal to the PWM generation unit; the valley bottom locking unit also outputs a peak current signal to the PWM turn-off judgment logic unit, the PWM turn-off judgment logic unit also accesses a current sampling signal flowing through a power switch tube in the switch power supply, and the PWM turn-off judgment logic unit outputs a PWM turn-off signal to the PWM generating unit; the PWM generating unit correspondingly generates a low-level or high-level control signal according to the PWM turn-off signal or the PWM turn-on signal and outputs the low-level or high-level control signal to the driver; the driver generates a PWM signal for directly connecting the power switch tube to the input control signal.

2. The quasi-resonant switching power supply controller based on valley bottom locking according to claim 1, wherein the valley bottom locking unit comprises a limit frequency generator, a first latch, a valley bottom number latch regulator and a peak current signal generator, wherein the limit frequency generator outputs a minimum switching cycle signal to the first latch, the first latch is used for recording a count value of a valley bottom count signal when a first valley bottom after the minimum switching cycle signal arrives, the count value is defined as a first valley bottom count value and is input to the valley bottom number latch regulator, and the valley bottom number latch regulator outputs a valley bottom number latch signal; the peak current signal generator detects the input feedback voltage detection signal and correspondingly outputs a peak current signal.

3. The valley-lock based quasi-resonant switching power supply controller of claim 2, wherein the valley-lock unit further comprises an update timer, a filter timer, a time delay adjuster, and a second latch; the updating timer generates an output updating time signal to the time delay regulator to serve as an updating time interval for generating the valley bottom latching signal; the filtering timer completes transient response to the valley bottom number latching signal, generates an output filtering time signal and inputs the output filtering time signal into the updating timer; the time delay regulator starts timing from the minimum switching period to prevent the lag time of valley bottom jumping, and outputs a lag time signal to the second latch; and the second latch is used for recording the count value of the corresponding valley bottom counting signal when the first valley bottom of the lag time is reached, defining the count value as a second valley bottom count value, and inputting the second valley bottom count value into the valley bottom number latch regulator.

4. The bottom-locking based quasi-resonant switching power supply controller of claim 3, wherein the bottom-locking unit further comprises a feedback signal interval determiner for performing interval identification determination on the input feedback signal, and outputting an interval identification signal to the bottom-number locking adjuster correspondingly.

5. The quasi-resonant switching power supply controller based on valley bottom locking according to claim 4, characterized in that for the PWM turn-on judging logic unit, after the minimum switching period signal arrives, if the value of the valley bottom counting signal is greater than or equal to the value of the valley bottom number locking signal, i.e. Nv _ cur is greater than or equal to Nv _ lock, the PWM turn-on signal is immediately generated to turn on PWM; and the PWM turn-off judgment logic unit comprises a comparator, and when the switching power supply detects that the current flowing through the sampling resistor is greater than the set value of the peak current signal, the PWM turn-off judgment logic unit generates a PWM turn-off signal to turn off the PWM.

6. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 5, wherein when the load of the switching power supply is reduced, the peak current signal is reduced, the primary charge-discharge cycle of the transformer exciting inductance is shortened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the left, and within the updating time interval, as long as one PWM cycle detects that the first valley bottom count value is larger than the value of the valley bottom number latch signal, i.e. Nv _ lim1> Nv _ lock, when the updating time interval arrives, the value of the valley bottom number latch signal is added by 1.

7. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 6, wherein when the load of the switching power supply is increased, the peak current signal is increased, the one-time charge-discharge cycle of the transformer exciting inductor is lengthened, the position of the valley bottom where the detection voltage signal starts to appear is shifted to the right, and in the updating time interval, if all PWM cycles satisfy that the second valley bottom count value is smaller than the value of the valley bottom number latch signal, that is, Nv _ lim2< Nv _ lock, the value of the valley bottom number latch signal is decreased by 1 when the updating time interval arrives.

8. The quasi-resonant switching power supply controller based on valley bottom locking as claimed in claim 7, wherein the system generates transient fluctuation every time the value of the valley bottom number latch signal is decreased by 1, at this time, the filter timer is started to filter out the value change of the valley bottom number latch signal caused by the transient fluctuation, before the timing of the filter timer is reached, the value of the valley bottom number latch signal is kept unchanged and the change condition of the valley bottom number latch signal is not enabled to be detected, after the filter timer is finished, the update timer is restarted to start the detection of the change condition of the valley bottom number latch signal.

9. The bottom-of-valley locking based quasi-resonant switching power supply controller of claim 8, wherein when the peak current signal is between the minimum and maximum values, to ensure the value of the bottom-of-valley number latch signal is stable without generating a jump, the value of the bottom-of-valley number latch signal is determined to be decreased by 1, using a dead time to keep the value of the bottom-of-valley number latch signal stable.

10. The bottom-locking based quasi-resonant switching power supply controller of claim 9, characterized in that in the time of the update time interval, if the first bottom count value is satisfied in all PWM periods with the value of the bottom number latch signal being greater than or equal to 1 plus the value of the bottom number latch signal, i.e., Nv _ lim1 ≦ n (Nv _ lock +1) is always true, and wherein in one PWM period, the first bottom count value is satisfied with the value of the bottom number latch signal plus 1, i.e., Nv _ lim1 ═ n (Nv _ lock +1), which indicates that the time length of the current dead time is not sufficient, then when the update time interval arrives, dead time + resolution, i.e., Tdv + t, is performed, where t is the resolution of one time increment per dead time of dead time.

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