CN111488721A - Layout hotspot clustering method, device and equipment - Google Patents

Layout hotspot clustering method, device and equipment Download PDF

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CN111488721A
CN111488721A CN202010270524.8A CN202010270524A CN111488721A CN 111488721 A CN111488721 A CN 111488721A CN 202010270524 A CN202010270524 A CN 202010270524A CN 111488721 A CN111488721 A CN 111488721A
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block
region
area
edge
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CN111488721B (en
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贺旭
汪一沛
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Hunan University
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Abstract

The invention discloses a circuit layout hot spot clustering method, which comprises the following steps: s1, obtaining a circuit layout file; s2, obtaining layout region blocks to be classified from the circuit layout file; and S3, generating a layout area block association diagram G-C, E according to the layout area blocks to be classified. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en‑1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value; and S4, acquiring a complementary graph G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E; s5, calculating the maximum clique of the complement G' of the association graph G, and acquiring the number of layout areas in the maximum clique; s6; and clustering according to the number of the layout areas. Improves the heat of the circuit layoutEfficiency of point clustering.

Description

Layout hotspot clustering method, device and equipment
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a layout hot spot clustering method.
Background
In the manufacturing process of integrated circuits, there is an important step, lithography. The basic principle of photolithography is to etch the pattern on the mask plate to the surface to be processed by photo-chemical reaction after photo-exposure using photoresist. With the rapid development of the super-large scale integrated circuit technology, the feature size of the transistor becomes smaller and smaller, the circuit design layout is also more and more complex, and great challenges are brought to the circuit lithography technology.
Currently, the wavelength of light has reached the 193nm limit, which is much larger than the existing feature size of transistors. When a standard circuit design layout is etched onto a silicon wafer, the diffraction action of light causes the circuit patterns on the silicon wafer to change, creating defects, also known as hot spots. These hot spots are likely to cause open circuit or short circuit during the operation of the circuit, and burn out the circuit, resulting in a decrease in the yield of the chip and a huge economic loss. Therefore, it is necessary to predict and locate the possible hot spot regions before photolithography, and to perform design repair on the possible hot spot regions to avoid subsequent photolithography defects.
Typically the hot spots are predicted by lithographic simulation or machine learning detection methods. However, because the scale of the chip problem is huge, in order to reduce the scale of the problem, the layout hot spot images need to be classified, and a representative hot spot image is selected for each classification. In this way, the problem is reduced to processing for representative images of each class, rather than layout samples one by one. Therefore, the number of the domain image classifications becomes an optimization target of the classification.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
Aiming at the technical problems in the related art, the invention provides a layout hot spot clustering method which can acquire the number of the classified layout images and perform clustering according to the number.
In order to achieve the above technical object, an embodiment of the present invention provides a circuit layout hot spot clustering method, which includes the following steps:
s1, obtaining a circuit layout file;
s2, obtaining layout region blocks to be classified from the circuit layout file;
s3, generating according to the layout region blocks to be classifiedAnd (C, E) the domain forming area block association diagram G. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
and S4, acquiring a complementary graph G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E;
s5, calculating the maximum clique of the complement G' of the association graph G, and acquiring the number of layout areas in the maximum clique;
s6; and clustering according to the number of the layout areas.
Further, before step S3, the method further includes: and combining the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally turned, vertically turned and horizontally and vertically turned.
Further generating a layout area block association diagram G, comprising the following steps:
s31, acquiring a region block set C;
s32, judging any two area blocks C in the area block set Ci，cjWhether the distance between the two is less than a first preset value or not or whether a layout area block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j; if not, executing step S33;
s33, judging whether the representative region block can be generated artificially, if yes, executing step S34;
s34, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
Further, the second threshold is 2 times the first threshold.
In the first step, the distance between the region blocks may be the area similarity ACC or the edge similarity ECC.
In addition, the invention also provides a circuit layout hot spot clustering device, which comprises the following units:
the acquisition unit is used for acquiring a circuit layout file;
the layout region block acquisition unit is used for acquiring layout region blocks to be classified from the circuit layout file;
and the association diagram generating unit is used for generating a layout area block association diagram G-C, E according to the layout area block to be classified. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
and the complement generating unit is used for acquiring a complement G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E;
the layout area number calculating unit is used for calculating the maximum clique of the complement G' of the association graph G and acquiring the number of the layout areas in the maximum clique;
and the clustering unit is used for clustering according to the number of the layout areas.
Further, the device further comprises a merging processing unit for merging the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally turned, vertically turned, and horizontally and vertically turned.
Further, the correlation diagram generation unit further includes:
an area block set acquisition unit configured to acquire an area block set C;
a first edge generation unit for judging any two area blocks C in the area block set Ci，cjWhether the distance between the two is less than a first preset value or not or whether a layout area block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j;
a second edge generation unit for judging whether the representative region block can be artificially generated, if so, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
Further, the second threshold is 2 times the first threshold.
The invention also provides layout hotspot clustering equipment which comprises a processor, a memory and a computer program which is stored in the memory and can run on the processor, wherein the processor realizes the methods of the steps S1-S5 when executing the computer program.
According to the invention, the association diagram of the layout areas is obtained, the number of the layout areas which can be obtained by the association diagram is obtained according to the complement diagram of the association diagram, and clustering operation is carried out according to the number of the layout areas, so that the efficiency of a clustering algorithm is improved. Furthermore, the invention also provides a method for calculating the association graph of the layout region according to the judgment condition of the artificially generated representative region, which can effectively reduce the final clustering number, thereby being closer to the optimal clustering number and further improving the clustering efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flow chart of a circuit layout hot spot clustering method provided in an embodiment of the present invention;
FIG. 2 is a cut-away schematic of the hot spot marking on the GDSII layout of FIG. 2;
FIG. 3 is a schematic diagram of edge shift constraint distance calculation according to an embodiment of the invention;
FIG. 4 is a schematic diagram of circuit layout hot spot clustering provided in the embodiment of the present invention;
FIG. 5 is a schematic diagram of four flip states of the same layout area according to the present invention;
FIG. 6 is a schematic flow chart of another circuit layout hot spot clustering method according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a circuit layout hot spot clustering device according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another circuit layout hot spot clustering device according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a circuit layout hotspot clustering device provided by the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Example one
Referring to fig. 1, this embodiment implements a circuit layout hot spot clustering method, which includes the following steps:
s1, obtaining a circuit layout file;
the circuit layout is a layout file in a GDSII format. The layout information of each layer is the placement of a plurality of right-angle polygons on a plane, as shown in fig. 2. The layout region blocks Clip to be classified are marked in the GDSII file.
Each Clip sample size is (w)c,hc) Wherein w iscAnd hcRespectively showing the width and height of the Clip area frame. And inside the Clip, the intercepted layout is a right-angle polygon.
S2, obtaining layout region blocks to be classified from the circuit layout file;
and S3, generating a layout area block association diagram G-C, E according to the layout area blocks to be classified. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,nThe method comprises the steps that (1) all edges are collected, and whether region blocks in a layout region block are connected or not is recorded; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
the distance between clips is commonly measured in two ways:
1. area similarity definition (ACC) of Clip
For Clip c1And c2Where they are different from each other, they are denoted as exclusive OR Xor (c)1,c2). If the ratio of the area of the different regions to the whole Clip area is less than a threshold value D, wherein D is>A natural number of 0, then c1And c2The area constraint (ACC constraint) is satisfied as shown in equation (1).
Figure BDA0002442991360000071
Wherein, wcIndicates the width of the Clip area, hcRepresenting the height of the Clip Area, Xor () representing the exclusive-OR function between two clips, and Area () representing the Area function parameter D ∈ [0, 1]Specified by the user. When D is 0, it means that the two clips are identical.
2. Edge similarity of Clip (ECC)
Each natural edge in the Clip can be translated inward or outward. For Clip c1And c2By translating the respective natural edge inwardly or outwardly over a distance diThe clips may be identical as shown in FIG. 3. If the maximum translation distance is less than or equal to D, wherein D is a positive integer, as shown in formula (2), C1And C2Satisfying the edge similarity constraint (ECC constraint). Where D is specified by the user, and when D is 0, the constraint requires that the two clips are identical.
Distance(c1，c2)＝max(d1，d2，…，dn)≤D (2)
Obtaining a territory region block set C ═ { C ═ C1,c2,…,cnAnd accordingly taking a layout area block from the set, e.g. c1And thus determine c2,…cnEach of (a) and c1If the distance of (d) is less than or equal to a threshold value, if so, a side e is generated.
The pseudo code is:
establishing a layout region block array C
FOR i＝1,…n
FOR j＝i+1,…n
IF Distance(ci,cj)<＝D
YES generates an edge;
referring to FIG. 4, FIG. 4(a) 8 Clip instances in Case1 from ICCAD 2016 interest; and (b) obtaining a Clip correlation diagram G after performing correlation diagram calculation on the graph 4, wherein each node number in the diagram represents a layout region block, the region block 1 is connected with the region blocks 8 and 5 in an edge mode, and the region block 6 is connected with any region block in a non-edge mode.
And S4, acquiring a complementary graph G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E;
referring to FIG. 4(c), the generated correlation diagram G is subjected to a complementary graph G' of the generated correlation diagram G, and any one edge e in the Clip correlation diagram Gi,jDenotes ciAnd cjPossibly assigned to the same cluster, so that in the patch G', any one edge ev,uDenotes cvAnd cuIt is not possible to assign to the same cluster.
S5, calculating the maximum clique of the complement G' of the association graph G, and acquiring the number of layout areas in the maximum clique;
referring to fig. 4(d), the maximum clique result for the complement G' is 3. And (4) obtaining a maximum group (namely a maximum complete subgraph) for G', wherein the clips cannot be allocated to the same cluster in pairs within the maximum group, namely, the clips are definitely allocated to different clusters. The number of clips within the clique is thus maximized, i.e., can be used as a reference to an array of clusters.
S6; and clustering according to the number of the layout areas.
The number of clusters can be initialized according to the number of the acquired layout areas, for example, when a K-means clustering algorithm is used, the initial number of clusters can be set to be 3, or when the K-means clustering algorithm is used, the initial number is not set, the K-means clustering algorithm automatically carries out clustering, whether the final possessed data of the K-means is larger than the number of the layout areas obtained in the step S5 or not is judged, and if not, the possessed number of the K-means is considered to be incorrect, and clustering needs to be carried out again. In this embodiment, only K-meas is used for example, and other clustering methods are all possible, which is not described in detail in this embodiment.
In the embodiment, the association map of the layout area is obtained, the number of the layout areas which can be obtained by the association map is obtained according to the complement of the association map, and the clustering operation is performed according to the number of the layout areas, so that the efficiency of the clustering algorithm is improved.
Further, before step S3, the method further includes: and combining the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally turned, vertically turned and horizontally and vertically turned.
Referring to FIG. 5, the Clip can be flipped horizontally, flipped vertically, flipped horizontally plus vertically, so that there are 4 cases. The two clips are compared, and if they are consistent (including the flip case), the two clips are merged into one. Merging clips can greatly reduce the number of clips to be processed during the Clustering calculation. As shown in Table 1, the number of clips can be greatly reduced after redundant data is deleted by using the test case of ICCAD 2016 Contest.
Example two
Referring to fig. 6, the present embodiment provides a circuit layout hot spot clustering method, which includes:
s1, obtaining a circuit layout file;
s2, obtaining layout region blocks to be classified from the circuit layout file;
and S3, generating a layout area block association diagram G-C, E according to the layout area blocks to be classified. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,nThe method comprises the steps that (1) all edges are collected, and whether region blocks in a layout region block are connected or not is recorded; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
the specific step S3 includes:
s31, acquiring a region block set C;
s32, judging any two area blocks C in the area block set Ci，cjDistance (c) betweeni，cj) Whether the value is less than a first preset value or a layout region block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j; if not, executing step S33;
in order to reduce the scale of the number of processed clips, similar clips need to be clustered (Cluster). And selecting one Clip meeting the similarity requirement with other clips from each Cluster as a Representative region reproducible Clip of the Cluster.
The reproducible Clip may be derived from an existing Clip, i.e., "ChooseRC", or may be artificially generated, i.e., "GenerateRC".
"ChooseRC" case (i.e., restationic Clip can only be found from Clip): if Distance (c)i,cj) Satisfies any of 1) or 2) belowOne condition, then ci,cjThere may be e in one Clusteri,jConnection ci,cj。
1)Distance(ci,cj)<Threshold value D
2)
Figure BDA0002442991360000101
So that Distance (c)i,ck)<D and Distance (c)j,ck)<D
I.e. if ci,cjIs less than or equal to D, then ci,cjCan be in one Cluster;
if c isi,cjIs greater than D, but c is presentkAnd ci,cjRespectively, are less than or equal to D, then c can be setkFor a reproducible Clip, ci,cjDivide into one Cluster.
S33, judging whether the representative region block can be generated artificially, if yes, executing step S34;
s34, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
In the case of "generateRC" being allowed (i.e., reproducible Clip can be artificially generated): if Distance (c)i,cj) The following condition 3) is satisfied, then e existsi,jConnection ci,cj。
3)Distance(ci,cj)<2D
If c isi,cjIs less than 2D, a reproducible Clip rc can be artificially generated such that Distance (c)i,rc)<D and Distance (c)j,rc)<D. Generating rc method, and taking c from ACC constraint definition or ECC constraint definitioni,cjThe median distance of (2) is sufficient.
On the contrary, if ci,cjIs greater than 2D, no artificial generation is possiblerc, make Distance (c)i,rc)<D and Distance (c)j,rc)<D。
And S4, acquiring a complementary graph G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E;
s5, calculating the maximum clique of the complement G' of the association graph G, and acquiring the number of layout areas in the maximum clique;
s6; and clustering according to the number of the layout areas.
In this embodiment, by obtaining the association map of the layout region, specifically, whether the examination allows the artificial generation of the representative region during the association map calculation, and obtaining the number of the layout regions that can be obtained according to the complement of the association map, and performing the clustering operation according to the number of the layout regions, the final number of clusters can be effectively reduced, thereby being closer to the optimal number of clusters, and further improving the clustering efficiency.
EXAMPLE III
Referring to fig. 7, the present embodiment provides a circuit layout hot spot clustering device, which includes the following units:
the acquisition unit is used for acquiring a circuit layout file;
the layout region block acquisition unit is used for acquiring layout region blocks to be classified from the circuit layout file;
and the association diagram generating unit is used for generating a layout area block association diagram G-C, E according to the layout area block to be classified. Wherein C ═ { C ═ C1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
and the complement generating unit is used for acquiring a complement G '═ C, E' of the layout area block association graph G. Wherein the edge set E' is complementary to E;
the layout area number calculating unit is used for calculating the maximum clique of the complement G' of the association graph G and acquiring the number of the layout areas in the maximum clique;
and the clustering unit is used for clustering according to the number of the layout areas.
In the embodiment, the association map of the layout area is obtained, the number of the layout areas which can be obtained by the association map is obtained according to the complement of the association map, and the clustering operation is performed according to the number of the layout areas, so that the efficiency of the clustering algorithm is improved.
The system further comprises a merging processing unit for merging the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally turned, vertically turned and horizontally and vertically turned.
Example four
Referring to fig. 8, this embodiment provides a circuit layout hot spot clustering device, which includes an obtaining unit, a layout region block obtaining unit, an association diagram generating unit, a complement diagram generating unit, a layout region number calculating unit, and a clustering unit, as described in the third embodiment.
Further, the association map generation unit further includes:
an area block set acquisition unit configured to acquire an area block set C;
a first edge generation unit for judging any two area blocks C in the area block set Ci，cjDistance (c) betweeni，cj) Whether the value is less than a first preset value or a layout region block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j;
a second edge generation unit for judging whether the generation of the representative region block can be considered, if so, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
In this embodiment, by obtaining the association map of the layout region, specifically, whether the examination allows the artificial generation of the representative region during the association map calculation, and obtaining the number of the layout regions that can be obtained according to the complement of the association map, and performing the clustering operation according to the number of the layout regions, the final number of clusters can be effectively reduced, thereby being closer to the optimal number of clusters, and further improving the clustering efficiency.
EXAMPLE five
Referring to fig. 9, the present embodiment provides a schematic structural diagram of a circuit layout hotspot clustering device 20. The circuit layout hotspot clustering device 20 of the embodiment comprises a processor 21, a memory 22 and a computer program stored in the memory 22 and operable on the processor 21. When the processor 21 executes the computer program, the steps in the above-mentioned circuit layout hot spot clustering method embodiment are implemented, for example, step S1 shown in fig. 2. Alternatively, the processor 21, when executing the computer program, implements the functions of the modules/units in the above-mentioned device embodiments, such as the first obtaining module 11.
Illustratively, the computer program may be divided into one or more modules/units, which are stored in the memory 22 and executed by the processor 21 to accomplish the present invention. The one or more modules/units may be a series of instruction segments of a computer program capable of performing specific functions, and the instruction segments are used for describing the execution process of the computer program in the circuit layout hot spot clustering device 20.
The circuit layout hot spot clustering device 20 may include, but is not limited to, a processor 21 and a memory 22. Those skilled in the art will understand that the schematic diagram is merely an example of the circuit layout hot spot clustering device 20, and does not constitute a limitation on the circuit layout hot spot clustering device 20, and may include more or less components than those shown in the drawings, or combine some components, or different components, for example, the circuit layout hot spot clustering device 20 may further include an input-output device, a network access device, a bus, and the like.
The Processor 21 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, and the processor 21 is a control center of the circuit layout hot spot clustering device 20, and various interfaces and lines are used to connect various parts of the whole circuit layout hot spot clustering device 20.
The memory 22 may be configured to store the computer program and/or module, and the processor 21 implements various functions of the circuit layout hotspot clustering device 20 by operating or executing the computer program and/or module stored in the memory 22 and calling data stored in the memory 22. The memory 22 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory 22 may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
The module/unit integrated by the circuit layout hot spot clustering device 20 may be stored in a computer readable storage medium if it is implemented in the form of a software functional unit and sold or used as an independent product. Based on such understanding, all or part of the flow of the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by the processor 21 to implement the steps of the above embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A circuit layout hot spot clustering method comprises the following steps:
s1, obtaining a circuit layout file;
s2, obtaining layout region blocks to be classified from the circuit layout file;
s3, generating a layout area block association diagram G (C, E) according to the layout area block to be classified, wherein C (C) is { C }1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
s4, obtaining a complementary graph G ' ═ C, E ' of the layout region block association graph G, wherein an edge set E ' is complementary to E;
s5, calculating the maximum clique of the complement G' of the association graph G, and acquiring the number of layout areas in the maximum clique;
s6; and clustering according to the number of the layout areas.
2. The method of claim 1, wherein before step S3, further comprising: and combining the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally turned, vertically turned and horizontally and vertically turned.
3. The method according to claim 1, wherein generating a layout area block association map G comprises the following steps:
s31, acquiring a region block set C;
s32, judging any two area blocks C in the area block set Ci，cjWhether the distance between the two is less than a first preset value or not or whether a layout area block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j; if not, executing step S33;
s33, judging whether the representative region block can be generated artificially, if yes, executing step S34;
s34, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
4. The method of claim 4, wherein the second threshold is 2 times the first threshold.
5. The method of claim 1, wherein the distance of the region blocks may be an area similarity ACC or an edge similarity ECC.
6. A circuit layout hot spot clustering device comprises the following units:
the acquisition unit is used for acquiring a circuit layout file;
the layout region block acquisition unit is used for acquiring layout region blocks to be classified from the circuit layout file;
a correlation diagram generating unit for generating a layout area block correlation diagram G ═ (C, E) according to the layout area block to be classified, wherein C ═ { C { [ C ]1,c2,…,cnDenotes a set of territory region blocks, E ═ E1,2,e1,3,…,en-1,n-the set of all edges; generating the edge E, namely generating the edges of the two layout region blocks when the distance between any two layout region blocks is smaller than a preset value;
the complement generating unit is used for acquiring a complement G ' ═ C, E ' of the layout region block association graph G, wherein the edge set E ' is complementary with the edge set E;
the layout area number calculating unit is used for calculating the maximum clique of the complement G' of the association graph G and acquiring the number of the layout areas in the maximum clique;
and the clustering unit is used for clustering according to the number of the layout areas.
7. The device according to claim 6, further comprising a merging processing unit for merging the same layout region blocks to be classified to obtain a layout region block set C, wherein the same layout region blocks to be classified are horizontally flipped, vertically flipped, horizontally flipped and vertically flipped.
8. The apparatus according to claim 6, wherein the correlation diagram generating unit further comprises:
an area block set acquisition unit configured to acquire an area block set C;
a first edge generation unit for judging any two area blocks C in the area block set Ci，cjWhether the distance between the two is less than a first preset value or not or whether a layout area block c existskSo that the layout area ci，ckThe distance between the two is less than a first preset value and the layout area cj，ckThe distance between the two is less than a first preset value; if so, a block c corresponding to the region is generatedi，cjEdge e ofi,jWherein k is not equal to i is not equal to j;
a second edge generation unit for judging whether the representative region block can be artificially generated, if so, judging the layout region block ci，cjIf the distance between the two is less than a second threshold, if yes, a corresponding area block c is generatedi，cjEdge e ofi,j。
9. The apparatus of claim 8, wherein the second threshold is 2 times the first threshold.
10. A layout hotspot clustering device comprising a processor, a memory and a computer program stored in the memory and operable on the processor, the processor implementing the method of claims 1-5 when executing the computer program.
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