CN111477665B

CN111477665B - Display panel and display device

Info

Publication number: CN111477665B
Application number: CN202010357680.8A
Authority: CN
Inventors: 蔡翔; 蔡雨; 张国峰; 李晓
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2022-08-26
Anticipated expiration: 2040-04-29
Also published as: CN111477665A

Abstract

The invention discloses a display panel and a display device. The display panel includes first display interval, second display interval and is located the transition display interval between first display interval and the second display interval, and the display panel includes: a plurality of first light emitting elements positioned in the first display region; a plurality of second light emitting elements located in the second display region, the light emitting frequency of the second light emitting elements in the light emitting stage being lower than the light emitting frequency of the first light emitting elements in the light emitting stage; and a plurality of third light-emitting elements located in the transitional display region, wherein the light-emitting frequency of at least part of the third light-emitting elements in the light-emitting stage is lower than that of the first light-emitting elements in the light-emitting stage and higher than that of the second light-emitting elements in the light-emitting stage. According to the display panel and the display device, the defects of flicker or ripple waves between the first display area and the second display area under the display state of the display panel can be relieved or even avoided.

Description

Display panel and display device

Technical Field

The invention relates to the field of display, in particular to a display panel and a display device.

Background

Organic Light Emitting Diode (OLED) display panels are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, and the like, and become the mainstream of display panels, because they have the advantages of high image quality, power saving, thin body, and wide application range.

In an electronic device (e.g., a mobile phone) including an OLED display panel, a part of the area often displays a dynamic picture, and a part of the area often displays a static picture. Therefore, the light emission frequency of the light emitting elements in the region where the still picture is often displayed can be reduced, that is, the display panel has both a high light emission frequency region and a low light emission frequency region, so that the power consumption of the display panel can be reduced. However, in the conventional display panel, flicker and ripple are easily generated at the boundary between the high emission frequency region and the low emission frequency region.

Disclosure of Invention

The invention provides a display panel and a display device, which can alleviate the flicker or ripple defects of the display panel during display.

In one aspect, an embodiment of the present invention provides a display panel, where the display panel includes a first display area, a second display area, and a transition display area located between the first display area and the second display area, and the display panel includes: a plurality of first light emitting elements positioned in the first display region; a plurality of second light-emitting elements located in the second display region, wherein the light-emitting frequency of the second light-emitting elements in the light-emitting stage is lower than that of the first light-emitting elements in the light-emitting stage; and a plurality of third light-emitting elements located in the transitional display region, wherein the light-emitting frequency of at least part of the third light-emitting elements in the light-emitting stage is lower than that of the first light-emitting elements in the light-emitting stage and higher than that of the second light-emitting elements in the light-emitting stage.

In another aspect, an embodiment of the present invention provides a display device, which includes the display panel according to any one of the foregoing embodiments.

According to the display panel and the display device of the embodiment of the invention, the light emitting frequency of the second light emitting element in the second display area in the light emitting stage is lower than the light emitting frequency of the first light emitting element in the first display area in the light emitting stage, so that the power consumption of the second display area is lower when a still picture is displayed. The display panel also comprises a transition display area arranged between the first display area and the second display area, wherein the light emitting frequency of at least part of the third light emitting elements in the transition display area in the light emitting stage is between the light emitting frequency of the first light emitting elements in the light emitting stage and the light emitting frequency of the second light emitting elements in the light emitting stage, so that the display effect difference caused by the difference of the light emitting frequency between the first display area and the second display area is alleviated, and the flicker or ripple defect between the first display area and the second display area in the display state of the display panel is relieved or even avoided.

Drawings

Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a display panel provided in accordance with an embodiment of the present invention, partially enlarged in the area M of FIG. 1;

FIG. 3 is a schematic partial enlarged view of a display panel in an area M in FIG. 1 according to another embodiment of the present invention;

FIG. 4 is a schematic partial enlarged view of a display panel provided in accordance with another embodiment of the present invention in a region M of FIG. 1;

FIG. 5 is a schematic top view of a display panel according to another embodiment of the present invention;

FIG. 6 is a schematic partial enlarged view of a display panel provided in accordance with another embodiment of the present invention in a region M of FIG. 1;

FIG. 7 is a diagram illustrating a third pixel driving circuit of a display panel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a third pixel driving circuit in a display panel according to another embodiment of the present invention;

FIG. 9 is a circuit diagram of a third pixel driving circuit in a display panel according to another embodiment of the present invention;

FIG. 10 is a timing diagram provided in accordance with an embodiment of the present invention that is involved in using the third pixel driving circuit shown in FIG. 9;

FIG. 11 is a schematic partial enlarged view of a display panel in the area M in FIG. 1 according to another embodiment of the present invention;

FIG. 12 is a schematic partial enlarged view of a display panel provided in accordance with another embodiment of the present invention in a region M of FIG. 1;

FIG. 13 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the first sub-region of the display panel according to still another embodiment of the present invention;

FIG. 14 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the second sub-region of the display panel according to still another embodiment of the present invention;

FIG. 15 is a schematic partial enlarged view of a display panel provided in accordance with another embodiment of the present invention in a region M of FIG. 1;

FIG. 16 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the third sub-region of the display panel according to still another embodiment of the present invention;

FIG. 17 is a schematic cross-sectional view taken along line A-A of FIG. 16;

FIG. 18 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the fourth sub-area of the display panel according to still another embodiment of the present invention;

FIG. 19 is a schematic cross-sectional view taken along line B-B of FIG. 18;

FIG. 20 is a partially enlarged schematic view of a display panel provided in accordance with still another embodiment of the present invention in a region M of FIG. 1;

FIG. 21 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the fifth sub-area of the display panel according to still another embodiment of the present invention;

fig. 22 is a schematic cross-sectional structure diagram of each first transistor of the third pixel driving circuit in the sixth sub-area in the display panel according to still another embodiment of the present invention;

FIG. 23 is a schematic structural diagram of a transitional display area and a portion of a non-display area of a display panel according to an embodiment of the invention;

FIG. 24 is a schematic structural diagram of a transitional display area and a portion of a non-display area of a display panel according to yet another embodiment of the present invention;

fig. 25 is a schematic structural diagram of a transitional display area and a portion of a non-display area of a display panel according to yet another embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. It should be noted that the technical features of the embodiments provided in the present application may be combined with each other as needed.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

Embodiments of the present invention provide a display panel, which may be an Organic Light Emitting Diode (OLED) display panel, including an OLED Light Emitting element.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic partial enlarged view of the display panel in an area M in fig. 1 according to the embodiment of the present invention. The display panel 100 includes a first display area AA1, a second display area AA2, and a transition display area AA3 between the first display area AA1 and the second display area AA 2.

The display panel 100 includes a plurality of first light emitting elements 110, a plurality of second light emitting elements 120, and a plurality of second light emitting elements 120. Wherein, the plurality of first light emitting elements 110 are located in the first display area AA 1. The plurality of second light emitting elements 120 are positioned at the second display area AA 2. The light emitting frequency of the second light emitting element 120 in the light emitting phase is lower than that of the first light emitting element 110 in the light emitting phase, so that the second display area AA2 consumes less power when displaying a still picture.

A plurality of third light emitting elements 130 are located in the transitional display area AA 3. The light emitting frequency of at least a portion of the third light emitting elements 130 in the light emitting period is lower than the light emitting frequency of the first light emitting element 110 in the light emitting period and higher than the light emitting frequency of the second light emitting element 120 in the light emitting period.

According to the display panel 100 of the embodiment of the invention, the light emitting frequency of at least part of the third light emitting elements 130 in the transition display area AA3 in the light emitting stage is between the light emitting frequency of the first light emitting element 110 in the light emitting stage and the light emitting frequency of the second light emitting element 120 in the light emitting stage, so that the difference of the display effect caused by the difference of the light emitting frequency between the first display area AA1 and the second display area AA2 is alleviated, and even the flicker or ripple defect between the first display area AA1 and the second display area AA2 in the display state of the display panel 100 is alleviated or even avoided.

Fig. 3 is a partially enlarged schematic view of a display panel in an area M in fig. 1 according to another embodiment of the present invention. In some embodiments, the transition display area AA3 includes a plurality of sub-areas SA arranged along the first display area AA1 toward the second display area AA 2. Each sub-area SA is arranged with at least one row of third light emitting elements 130. For example, in the present embodiment, the transition display area AA3 includes 3 sub-areas SA, each of which is arranged with two rows of the third light emitting elements 130.

It should be noted that the number of the sub-regions SA included in the transition display region AA3 and the number of the rows of the third light-emitting elements 130 included in each sub-region SA are not limited to the above examples, and may be other cases in other embodiments. For example, fig. 4 is a partially enlarged schematic view of the display panel in the area M in fig. 1 according to another embodiment of the present invention, and in another embodiment, the transition display area AA3 includes 6 sub-areas SA, and each sub-area SA is arranged with a row of the third light emitting elements 130. In addition, the number of rows of the third light emitting elements 130 in the plurality of sub-regions SA may be equal to each other, or the sub-regions SA in which the number of rows of the third light emitting elements 130 is different from each other may be included.

In some embodiments, in the direction Q in which the first display area AA1 points to the second display area AA2, the light emitting frequency of the third light emitting elements 130 of the plurality of sub-areas SA in the light emitting phase decreases. In the embodiment shown in fig. 3 and 4, the first display area AA1, the transition display area AA3, and the second display area AA2 are sequentially arranged in the same straight line direction, so that the direction Q in which the first display area AA1 points to the second display area AA2 is a unidirectional straight line direction, and at this time, the light emitting frequency of the third light emitting elements 130 of the sub-areas SA in the light emitting phase decreases in the straight line direction. However, in other embodiments, the direction Q in which the first display area AA1 points to the second display area AA2 may not be limited to the straight-line pointing direction described above according to the layout of the first display area AA1, the transition display area AA3 and the second display area AA 2.

For example, fig. 5 is a schematic top view of a display panel according to another embodiment of the invention. In some embodiments, the transition display area AA3 is disposed around at least a portion of the periphery of the second display area AA2, and the first display area AA1 is disposed around at least a portion of the periphery of the transition display area AA 3. That is, the transition display area AA3 is disposed around or partially around the second display area AA2, and the first display area AA1 is disposed around or partially around the transition display area AA 3. At this time, the direction in which the first display area AA1 points to the second display area AA2 may include a plurality of linear directions, and the direction in which the first display area AA1 points to the second display area AA2 is substantially each direction from the periphery of the transition display area AA3 to the center of the second display area AA 2. In the embodiment shown in fig. 5, taking the example that the transition display area AA3 surrounds the entire periphery of the second display area AA2, and the first display area AA1 surrounds the entire periphery of the transition display area AA3, the directions Q1, Q2, Q3, and Q4 in which the first display area AA1 points to the second display area AA2 are directions from the periphery of the transition display area AA3 to the center of the second display area AA2, in this case, the plurality of sub-areas are approximately annular structures sleeved with each other, and the light emitting frequency of the third light emitting elements in the plurality of sub-areas in the light emitting stage decreases in the directions Q1, Q2, Q3, and Q4 in which the first display area AA1 points to the second display area AA 2.

Referring to fig. 3, in the embodiment shown in fig. 3, the light emitting frequency of the first light emitting element 110 in the first display area AA1 in the light emitting phase is 60 hertz (Hz), the light emitting frequency of the second light emitting element 120 in the second display area AA2 in the light emitting phase is 10Hz, and the light emitting frequencies of the third light emitting elements 130 in the 3 sub-areas SA of the transition display area AA3 in the direction Q from the first display area AA1 to the second display area AA2 in the light emitting phase are 50Hz, 30Hz, and 20Hz, respectively.

By further dividing the transitional display area AA3 into a plurality of sub-areas SA and arranging the light emitting frequencies of the third light emitting elements 130 of the plurality of sub-areas SA in the direction from the first display area AA1 to the second display area AA2 in a decreasing manner in the light emitting phase, the difference in display effect caused by the difference in light emitting frequency between the first display area AA1 and the second display area AA2 can be further alleviated in a gradient increasing manner, thereby further alleviating the flicker or ripple defect occurring between the first display area AA1 and the second display area AA2 in the display state of the display panel 100.

In some embodiments, in the sub-regions SA, the light emitting frequency of the third light emitting element 130 in the sub-region SA adjacent to the first display region AA1 in the light emitting period is equal to the light emitting frequency of the first light emitting element 110 in the first display region AA1 in the light emitting period, and the light emitting frequency of the third light emitting element 130 in the sub-region SA adjacent to the second display region AA2 in the light emitting period is equal to the light emitting frequency of the second light emitting element 120 in the second display region AA2 in the light emitting period. In some embodiments, the difference between the light emitting frequencies of the third light emitting elements 130 in each two adjacent sub-regions SA in the light emitting period is equal, so that the light emitting frequencies of the light emitting elements between the first display region AA1 and the second display region AA2 in the light emitting period are uniformly gradually changed, thereby improving the display effect of the display panel 100. For example, in the embodiment shown in fig. 4, the light emitting frequency of the first light emitting element 110 in the first display area AA1 in the light emitting phase is 60 hertz (Hz), the light emitting frequency of the second light emitting element 120 in the second display area AA2 in the light emitting phase is 10Hz, and the light emitting frequencies of the third light emitting elements 130 in the 6 sub-areas SA of the transition display area AA3 in the direction Q along the first display area AA1 toward the second display area AA2 in the light emitting phase are 60Hz, 50Hz, 40Hz, 30Hz, 20Hz, and 10Hz, respectively.

In some embodiments, the transitional display area AA3 includes an even number of sub-areas SA, and the number of rows in each sub-area SA that includes the third light-emitting element 130 is the same. In some embodiments, the transition display area AA3 includes at least 6 sub-areas SA, such as 8 sub-areas, 10 sub-areas, 6 sub-areas, etc., so as to match with corresponding driving chips. In some embodiments, the difference of the light emitting frequencies of the third light emitting elements 130 in each two adjacent sub-regions SA is equal, wherein the smaller the difference, the better the transition effect of the light emitting frequency of the transition display region AA3 of the display panel 100 is when displaying.

Fig. 6 is a partially enlarged schematic view of a display panel in an area M in fig. 1 according to still another embodiment of the present invention. In some embodiments, the display panel 100 includes a first pixel driving circuit 140, the first pixel driving circuit 140 is located in the first display area AA1, and the first pixel driving circuit 140 is electrically connected to the first light emitting element 110 for driving the first light emitting element 110 to emit light. The display panel 100 includes a second pixel driving circuit 150, the second pixel driving circuit 150 is located in the second display area AA2, and the second pixel driving circuit 150 is electrically connected to the second light emitting element 120 for driving the second light emitting element 120 to emit light.

In some embodiments, the display panel 100 further includes a third pixel driving circuit 160. The third pixel driving circuit 160 is located in the transitional display area AA3, and the third pixel driving circuit 160 is electrically connected to the third light emitting element 130 and is used for driving the third light emitting element 130 to emit light.

Fig. 7 is a schematic structural diagram of a third pixel driving circuit in a display panel according to an embodiment of the invention. The third pixel driving circuit 160 includes a data writing unit 161, a driving unit 162, a storage unit 163, and a first light emission controlling unit 164.

The data writing unit 161 is for transmitting a data signal. The driving unit 162 is configured to generate a driving current according to the data signal of the data writing unit 161. The storage unit 163 serves to store the data signal transferred to the driving unit 162. The first light emitting control unit 164 is connected between the first power terminal PVDD and the driving unit 162 or between the driving unit 162 and the third light emitting element 130. The first light emitting control unit 164 is configured to respond to the first light emitting signal in the light emitting phase so that the third light emitting element 130 receives the driving current that is periodically intermittently turned on in the light emitting phase.

The data writing unit 161 is coupled to the storage unit 163, and in the data writing phase, the data writing unit 161 is conducted with the storage unit 163, and the data writing unit 161 stores the data signal to the storage unit 163.

The driving unit 162 is coupled to the first power source terminal PVDD. The first light emitting control unit 164 can be coupled between the driving unit 162 and the third light emitting element 130, or coupled between the first power source terminal PVDD and the driving unit 162. In the light emitting period, the first light emitting control unit 164 responds to a first light emitting signal, which is a pulse signal with a predetermined frequency, so that the third light emitting element 130 receives the driving current that is periodically turned on intermittently in the light emitting period. By controlling the frequency of the first light emitting signal in response to the first light emitting control unit 164 in the third pixel driving circuit 160 during the light emitting period, the control of the light emitting frequency of the third light emitting element 130 in the transition display area AA3 during the light emitting period can be realized, so that the light emitting frequency of at least a part of the third light emitting element 130 during the light emitting period is between the light emitting frequency of the first light emitting element 110 during the light emitting period and the light emitting frequency of the second light emitting element 120 during the light emitting period.

In some embodiments, the first light emitting control unit 164 is connected between the driving unit 162 and the third light emitting element 130. In the light emitting period, the driving unit 162 may continuously supply the driving current, and the first light emitting control unit 164 transmits the driving current to the third light emitting element 130 in the form of periodic intermittent conduction. Therefore, the components of the driving unit 162 do not need to be repeatedly operated in the light emitting stage, and the demand for the components of the driving unit 162 is reduced.

Fig. 8 is a schematic structural diagram of a third pixel driving circuit in a display panel according to yet another embodiment of the invention. The third pixel driving circuit 160 includes a data writing unit 161, a driving unit 162, a storage unit 163, a first light emission control unit 164, and a second light emission control unit 165.

The data writing unit 161 is for transmitting a data signal. The driving unit 162 is configured to generate a driving current according to the data signal of the data writing unit 161. The storage unit 163 serves to store the data signal transferred to the driving unit 162. In the present embodiment, the first light emitting control unit 164 is connected between the driving unit 162 and the third light emitting element 130. The second light-emission control unit 165 is connected between the first power source terminal PVDD and the driving unit 162. Wherein the second light-emission control unit 165 is configured to respond to the continuously-turned-on second light-emission signal during the light-emission period to continuously turn on the first power terminal PVDD and the driving unit 162 during the light-emission period; the first light emitting control unit 164 is configured to respond to the first light emitting signal in the light emitting phase so that the third light emitting element 130 receives the driving current that is periodically intermittently turned on in the light emitting phase. In the light emitting stage, the first light emitting signal is a pulse signal with a predetermined frequency.

The first light-emitting signal and the second light-emitting signal are turned off when the third pixel driving circuit 160 is in the data writing stage, so that the third pixel driving circuit 160 can be configured to simply turn on the data writing unit 161 and the storage unit 163 in the data writing stage, thereby preventing the first power source terminal PVDD from being turned on with the storage unit 163 to generate interference on the data signal stored in the storage unit 163. When the third pixel driving circuit 160 is in the light-emitting writing phase, the second light-emitting signal is continuously turned on, and the first light-emitting signal is periodically turned on intermittently, so that the third light-emitting element 130 receives the periodically turned on driving current intermittently in the light-emitting phase. Since the second light-emitting signal is continuously turned on in the light-emitting stage, the components of the second light-emitting control unit 165 and the components of the driving unit 162 do not need to repeatedly operate in the light-emitting stage, so that the requirements on the components of the second light-emitting control unit 165 and the components of the driving unit 162 are reduced.

As shown in fig. 8, in some embodiments, the third pixel driving circuit 160 further includes a first reset unit 166. The first reset unit 166 is coupled to a node between the control terminal of the driving unit 162 and the memory unit 163, and the first reset unit 166 is configured to reset (i.e., initialize) the node during a reset phase.

Fig. 9 is a circuit diagram of a third pixel driving circuit in a display panel according to still another embodiment of the invention. In the present embodiment, the third pixel driving circuit 160 includes a data writing unit 161, a driving unit 162, a storage unit 163, a first light emission control unit 164, a second light emission control unit 165, a first reset unit 166, and a second reset unit 167.

The data writing unit 161 is coupled between the data signal terminal Vdate and the first node N1 for transmitting a data signal. The control terminal of the driving unit 162 is connected to the first node N1 for generating a driving current according to the data signal of the data writing unit 161. The storage unit 163 is also connected to the first node N1 for storing the data signal transmitted to the driving unit 162.

The first light emitting control unit 164 is connected between the driving unit 162 and the third light emitting element 130. The second light-emission control unit 165 is connected between the first power source terminal PVDD and the driving unit 162. Wherein the second light-emission control unit 165 is configured to respond to the continuously-turned-on second light-emission signal during the light-emission period, so that the first power terminal PVDD and the driving unit 162 are continuously turned on during the light-emission period; the first light emitting control unit 164 is configured to respond to the first light emitting signal in the light emitting phase so that the third light emitting element 130 receives the driving current that is periodically intermittently turned on in the light emitting phase. In the light emitting stage, the first light emitting signal is a pulse signal with a predetermined frequency.

The first reset unit 166 is connected to the first node N1, and the first reset unit 166 is configured to reset (i.e., initialize) the first node N1 during a reset phase.

The second resetting unit 167 is connected to one input terminal of the third light emitting element 130, and the second resetting unit 167 is configured to be able to reset the input terminal of the third light emitting element 130.

The third light emitting element 130 is an OLED light emitting element, and includes a first end and a second end opposite to each other, and in this embodiment, the first end of the third light emitting element 130 is taken as an anode end, and the second end is taken as a cathode end. A first end of the third light emitting element 130 is connected to the driving unit 162 via the first light emitting control unit 164, and a second end of the third light emitting element 130 is coupled to the second power source terminal PVEE.

In some embodiments, the second reset unit 167 is connected to the second node N2 between the first light emitting control unit 164 and the third light emitting element 130, so that the first end of the third light emitting element 130 can be reset.

The first light emitting control unit 164 may include a first transistor M1 having a gate connected to the first light emitting signal terminal E1 for receiving and responding to the first light emitting signal, a first pole of the first transistor M1 connected to the driving unit 162, and a second pole of the first transistor M1 connected to the third light emitting element 130.

The second light-emission control unit 165 may include a second transistor M2 having a gate connected to the second light-emission signal terminal E2 for receiving and responding to the second light-emission signal, a first pole of the second transistor M2 connected to the first power source terminal PVDD, and a second pole of the second transistor M2 connected to the driving unit 162.

The driving unit 162 may include a third transistor M3, a gate of the third transistor M3 is connected to the first node N1, a first pole of the third transistor M3 is connected to the second light emission control unit 165, i.e., to the second pole of the second transistor M2, and a second pole of the third transistor M3 is connected to the first light emission control unit 164, i.e., to the first pole of the first transistor M1.

The storage unit 163 includes a storage capacitor Cst having a first electrode connected to the first power terminal PVDD and a second electrode connected to the first node N1.

The first reset unit 166 may include a fourth transistor M4, a gate of the fourth transistor M4 is connected to the first scan signal terminal S1, a first pole of the fourth transistor M4 is connected to the reference voltage signal terminal Vref, and a second pole of the fourth transistor M4 is connected to the first node N1.

The data writing unit 161 may include a fifth transistor M5 and a sixth transistor M6, and a gate of the fifth transistor M5 and a gate of the sixth transistor M6 are connected to the second scan signal terminal S2. A first pole of the fifth transistor M5 is connected to the data signal terminal Vdate, a second pole of the fifth transistor M5 is connected to a third node N3 between the second light-emitting control unit 165 and the driving unit 162, and the third node N3 is located between the second transistor M2 and the third transistor M3. A first pole of the sixth transistor M6 is connected to a fourth node N4 between the first light emission control unit 164 and the driving unit 162, the fourth node N4 is located between the first transistor M1 and the third transistor M3, and a second pole of the sixth transistor M6 is connected to the first node N1.

The second reset unit 167 may include a seventh transistor M7, in this embodiment, a gate of the seventh transistor M7 is connected to the second scan signal terminal S2, a first terminal of the seventh transistor M7 is connected to the reference voltage signal terminal Vref, and a second terminal of the seventh transistor M7 is connected to the second node N2.

Fig. 10 is a timing diagram provided in accordance with an embodiment of the present invention, which is involved in using the third pixel driving circuit shown in fig. 9. In this embodiment, the case where each transistor is a P-type transistor is taken as an example, and each transistor is turned on at a low level. It is understood that in some other embodiments, each transistor may be an N-type transistor, that is, each transistor is turned on at a high level, and the timing diagram corresponding to the transistor is opposite to the timing diagram of the embodiment in terms of the high and low levels of each signal at each stage.

In this embodiment, the first Scan signal terminal S1 provides the first Scan signal Scan1, the second Scan signal terminal S2 provides the second Scan signal Scan2, the first light emitting signal terminal E1 provides the first light emitting signal Emit1, and the second light emitting signal terminal E2 provides the second light emitting signal Emit 2.

In the reset period T1, the first Scan signal Scan1 is a continuous on signal, the second Scan signal Scan2, the first emission signal Emit1 and the second emission signal Emit2 are turned off, and the fourth transistor M4 of the first reset unit 166 is turned on, so that the first node N1 is reset.

In the data writing phase T2, the second Scan signal Scan2 is a continuous on signal, and the first Scan signal Scan1, the first emission signal Emit1 and the second emission signal Emit2 are turned off. At this time, on the one hand, the fifth transistor M5 and the sixth transistor M6 are turned on, and the data signal of the data signal terminal Vdate is transmitted to the first node N1 through the fifth transistor M5, the third transistor M3 and the sixth transistor M6, and the data signal can be stored in the storage capacitor Cst. On the other hand, the second scan signal terminal S2 is a continuous on signal to turn on the seventh transistor M7 of the second reset unit 167, thereby resetting the second node N2.

In the light emitting period T3, the first Scan signal Scan1 and the second Scan signal Scan2 are turned off, and the second light emitting signal Emit2 is a continuous on signal, so that the second transistor M2 is continuously turned on, and the first power source terminal PVDD and the driving unit 162 are continuously turned on in the light emitting period. Meanwhile, the first light emitting signal Emit1 is a pulse signal with a predetermined frequency, that is, the first light emitting signal Emit1 is a periodically and intermittently conducted signal in the light emitting period T3, and at this time, the first transistor M1 is in a periodically and intermittently conducted state, so that the third light emitting element 130 receives a driving current that is periodically and intermittently conducted in the light emitting period. By controlling the frequency of the first light emitting signal Emit1 in the light emitting period T3, the control of the light emitting frequency of the third light emitting element 130 in the transition display area AA3 in the light emitting period T3 can be realized, so that the light emitting frequency of at least part of the third light emitting element 130 in the light emitting period T3 is between the light emitting frequency of the first light emitting element 110 in the light emitting period and the light emitting frequency of the second light emitting element 120 in the light emitting period, so as to improve the display effect of the display panel 100.

Fig. 11 is a partially enlarged schematic view of a display panel in an area M in fig. 1 according to still another embodiment of the present invention. In some embodiments, the transition display area AA3 includes a plurality of sub-areas SA arranged along the first display area AA1 toward the second display area AA2, each sub-area SA being arranged with at least one row of the third pixel driving circuits 160. In the direction Q from the first display area AA1 to the second display area AA2, the frequency of the first light-emitting signal, in response to the light-emitting phase, of the first light-emitting control units 164 of the third pixel driving circuits 160 arranged in the plurality of sub-areas SA decreases, so that the light-emitting frequency of the third light-emitting elements 130 corresponding to the third pixel driving circuits 160 in the light-emitting phase has a corresponding rule, and therefore, the difference in display effect caused by the difference in light-emitting frequency between the first display area AA1 and the second display area AA2 can be mitigated in a gradient progressive manner, and the display effect can be improved.

In some embodiments, the difference between the frequencies of the first light emitting signals to which the first light emitting control units 164 of the third pixel driving circuits 160 in every two adjacent sub-areas SA respond in the light emitting period is equal. For example, in the embodiment shown in fig. 11, in the direction Q from the first display area AA1 to the second display area AA2, the frequencies of the first light-emitting signals responded by the first light-emitting control unit 164 of the third pixel driving circuit 160 in the 6 sub-areas SA of the transition display area AA3 during the light-emitting phase are 60Hz, 50Hz, 40Hz, 30Hz, 20Hz, and 10Hz, respectively, that is, the difference between the frequencies of the first light-emitting signals responded by the first light-emitting control unit 164 of the third pixel driving circuit 160 in each two adjacent sub-areas SA during the light-emitting phase is 10Hz, so that the light-emitting frequencies of the light-emitting elements between the first display area AA1 and the second display area AA2 during the light-emitting phase are uniformly graded, and the display effect of the display panel 100 is further improved.

In some embodiments, the first transistor M1 of the first light emission control unit 164 includes an active layer and a gate insulating layer that insulates and spaces the gate electrode of the first transistor M1 from the active layer, and the gate electrode of the first transistor M1 includes at least one gate portion, each gate portion intersecting the active layer in projection on a plane in which the active layer lies. The active layer of the first transistor M1 includes at least one of a polysilicon (P-Si) layer and an oxide semiconductor layer. The polysilicon layer is, for example, a Low Temperature Polysilicon (LTPS) layer, and the Oxide semiconductor layer is, for example, an Indium Gallium Zinc Oxide (IGZO) layer. In one example, the active layers of the first transistors M1 in the plurality of sub-regions SA are all polysilicon layers. In another example, the active layers of the first transistors M1 in the plurality of sub-regions SA are all oxide semiconductor layers. In yet another example, the active layer of each first transistor M1 in at least part of the plurality of sub-regions SA includes an interconnected polysilicon layer and an oxide semiconductor layer.

Fig. 12 is a partially enlarged schematic view of a display panel provided according to still another embodiment of the present invention in an area M in fig. 1. In some embodiments, the plurality of sub-regions SA includes a first sub-region SA1 and a second sub-region SA2, wherein the second sub-region SA2 is located on a side of the first sub-region SA1 near the second display region AA 2. It should be noted that fig. 12 illustrates an example in which the first sub-area SA1 and the second sub-area SA2 are disposed adjacent to each other, but this is not essential, and for example, in some other embodiments, there may be another sub-area SA between the first sub-area SA1 and the second sub-area SA 2.

Fig. 13 is a schematic cross-sectional structure diagram of each first transistor of the third pixel driving circuit in the first sub-area of the display panel according to still another embodiment of the invention, and fig. 14 is a schematic cross-sectional structure diagram of each first transistor of the third pixel driving circuit in the second sub-area of the display panel according to still another embodiment of the invention.

As shown in fig. 13, each first transistor M1_1 of the third pixel driving circuit 160 in the first sub-area SA1 includes an active layer AL and a gate insulating layer GI that insulates and separates a gate GT of the first transistor M1_1 from the active layer AL, and the gate GT of the first transistor M1_1 in the first sub-area SA1 includes a gate portion GS that intersects the active layer AL in a projection on a plane where the active layer AL is located.

As shown in fig. 14, each first transistor M1_2 of the third pixel driving circuit 160 in the first sub-area SA2 includes an active layer AL and a gate insulating layer GI that insulates and spaces a gate GT of the first transistor M1_2 from the active layer AL, and the gate GT of the first transistor M1_2 in the first sub-area SA2 includes two gate portions GS, each of which intersects the active layer AL in a projection on a plane in which the active layer AL is located.

Each first transistor M1_2 of the third pixel drive circuit 160 within the second sub-area SA2 comprises a larger number of gate sections GS than each first transistor M1_1 of the third pixel drive circuit 160 within the first sub-area SA1, such that the first transistor M1_2 of the second sub-area SA2 is able to achieve a lower leakage current than the first transistor M1_1 of the first sub-area SA 1. In some embodiments, in the plurality of sub-areas SA, the number of gate portions GS included in each first transistor M1 in each sub-area SA increases as the frequency of the first light emitting signal to which each first transistor M1 in each sub-area SA responds in the light emitting phase decreases. For example, in the present embodiment, the frequencies of the first light-emitting signals to which the first transistor M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 responds in the light-emitting phase in the direction Q from the first display region AA1 to the second display region AA2 are 60Hz, 50Hz, 40Hz, 30Hz, 20Hz, and 10Hz, respectively, and correspondingly, the number of gate portions GS included in each first transistor M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 is 1, 2, 3, 4, 5, and 6 in the direction Q from the first display region AA1 to the second display region AA2, respectively. The lower the frequency of the response signal of each first transistor M1, the lower the leakage current thereof needs to be arranged, and by arranging the gate portion GS of the first transistor M1 in each sub-area SA as described above, each first transistor M1 can satisfy the requirement for the leakage current thereof, thereby facilitating the implementation of the gradual change type and uniform gradual change type driving of the light emission frequency of the third light emitting element 130 in the transition display area AA 3.

Fig. 15 is a partially enlarged schematic view of a display panel provided according to still another embodiment of the present invention in an area M in fig. 1. In some embodiments, the plurality of sub-regions SA includes a third sub-region SA3 and a fourth sub-region SA4, wherein the fourth sub-region SA4 is located on a side of the third sub-region SA3 near the second display region AA 2. In fig. 15, the third sub-region SA3 and the fourth sub-region SA4 are disposed adjacently, for example, this is not necessary, for example, in some other embodiments, there may be another sub-region SA between the third sub-region SA3 and the fourth sub-region SA 4.

Fig. 16 is a schematic cross-sectional view illustrating each first transistor of the third pixel driving circuit in the third sub-area of the display panel according to still another embodiment of the present invention, and fig. 17 is a schematic cross-sectional view along a-a direction in fig. 16. As shown in fig. 16 and 17, each first transistor M1_3 of the third pixel driving circuit 160 in the third sub-area SA3 includes an active layer AL and a gate insulating layer GI that insulates and spaces a gate GT of the first transistor M1_3 from the active layer AL, and the gate GT of the first transistor M1_3 of the first sub-area SA1 includes at least one gate portion GS (e.g., three), and a projection of each gate portion GS on a plane where the active layer AL is located intersects with the active layer AL.

In some embodiments, in the first transistor M1 of the third pixel driving circuit 160 at least in part of the sub region SA, the active layer AL includes a polysilicon layer and an oxide semiconductor layer which are interconnected. For example, the active layer AL of each first transistor M1_3 of the third pixel driving circuit 160 in the third sub-area SA3 includes the interconnected polysilicon layer PSI and oxide semiconductor layer OXD.

As shown in fig. 16, in each of the first transistors M1_3, the extension direction of the polysilicon layer PSI intersects with the extension direction of the oxide semiconductor layer OXD, the gate GT of the first transistor M1_3 includes a first gate section GS1 and a second gate section GS2, and the first gate section GS1 and the second gate section GS2 are interconnected. The projection of the first gate portion GS1 on the plane of the active layer AL perpendicularly intersects the polysilicon layer PSI, and the projection of the second gate portion GS2 on the plane of the active layer AL perpendicularly intersects the oxide semiconductor layer OXD.

In this embodiment, the polysilicon layer PSI of the active layer AL and the oxide semiconductor layer OXD are disposed in the same layer and are contact-connected to each other. In other embodiments, the polysilicon layer PSI and the oxide semiconductor layer OXD may be connected by a via or the like. And in some alternative embodiments, the polysilicon layer PSI and the oxide semiconductor layer OXD may be located on different film layers and connected through the via holes.

Fig. 18 is a schematic cross-sectional view of each first transistor of the third pixel driving circuit in the fourth sub-area of the display panel according to still another embodiment of the present invention, and fig. 19 is a schematic cross-sectional view taken along direction B-B in fig. 18. As shown in fig. 18 and 19, each of the first transistors M1_4 of the third pixel driving circuits 160 in the fourth sub-area SA4 includes an active layer AL and a gate insulating layer GI insulating and spacing the gate GT of the first transistor M1_4 from the active layer AL. The active layer AL of the first transistor M1_4 includes an interconnected polysilicon layer PSI and an oxide semiconductor layer OXD. The extension direction of the polysilicon layer PSI crosses the extension direction of the oxide semiconductor layer OXD, the gate GT of the first transistor M1_4 includes a first gate portion GS1 and a second gate portion GS2, and the first gate portion GS1 and the second gate portion GS2 are interconnected. The projection of the first gate portion GS1 on the plane of the active layer AL perpendicularly intersects the polysilicon layer PSI, and the projection of the second gate portion GS2 on the plane of the active layer AL perpendicularly intersects the oxide semiconductor layer OXD.

As previously described, the fourth sub-area SA4 is located at a side of the third sub-area SA3 close to the second display area AA 2. In the present embodiment, each first transistor M1_4 of the third pixel driving circuit 160 within the fourth sub-area SA4 includes a greater number of second gate portions GS2 than each first transistor M1_3 of the third pixel driving circuit 160 within the third sub-area SA3 includes a greater number of second gate portions GS 2. In the present embodiment, each first transistor M1_3 of the third sub-area SA3 includes one first gate portion GS1 and two second gate portions GS 2; each first transistor M1_4 of the fourth sub-area SA4 includes one first gate section GS1 and three second gate sections GS 2.

In some embodiments, in the plurality of sub-areas SA, the number of the second gate portions GS2 included in each first transistor M1 in each sub-area SA increases as the frequency of the first light emitting signal to which each first transistor M1 in each sub-area SA responds in the light emitting phase decreases. For example, in the present embodiment, the frequencies of the first light-emitting signals to which the first transistor M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 responds during the light-emitting phase in the direction Q from the first display region AA1 to the second display region AA2 are 60Hz, 50Hz, 40Hz, 30Hz, 20Hz, and 10Hz, respectively, and correspondingly, the number of the second gate portions 2 included in each of the first transistors M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 in the direction Q from the first display region AA1 to the second display region AA2 is GS, 1, 2, 3, 4, and 5, respectively. Wherein each first transistor M1 of the third pixel driving circuit 160 in the 6 sub-areas SA includes one first gate section GS 1. The lower the frequency of the response signal of each first transistor M1, the lower the leakage current thereof needs to be arranged, and by arranging the second gate portion GS2 of the first transistor M1 of each sub-area SA as described above, each first transistor M1 can satisfy the requirement for the leakage current thereof, which facilitates the implementation of the gradual change type and uniform gradual change type driving of the light emitting frequency of the third light emitting element 130 of the transition display area AA 3.

Fig. 20 is a partially enlarged schematic view of a display panel provided according to still another embodiment of the present invention in an area M in fig. 1. In some embodiments, the plurality of sub-regions SA includes a fifth sub-region SA5 and a sixth sub-region SA6, wherein the sixth sub-region SA6 is located at a side of the fifth sub-region SA5 close to the second display region AA 2. In fig. 20, the fifth sub-area SA5 and the sixth sub-area SA6 are disposed adjacently to each other for illustration, but this is not essential, and for example, in other embodiments, there may be other sub-areas SA between the fifth sub-area SA5 and the sixth sub-area SA 6.

Fig. 21 is a schematic cross-sectional structure diagram of each first transistor of the third pixel driving circuit in the fifth sub-area of the display panel according to still another embodiment of the present invention, and fig. 22 is a schematic cross-sectional structure diagram of each first transistor of the third pixel driving circuit in the sixth sub-area of the display panel according to still another embodiment of the present invention.

As shown in fig. 21, each first transistor M1_5 of the third pixel driving circuit 160 in the fifth sub-area SA5 includes an active layer AL and a gate insulating layer GI that insulates and spaces a gate GT of the first transistor M1_5 from the active layer AL, and the gate GT of the first transistor M1_5 in the fifth sub-area SA5 includes at least one gate portion GS (e.g., five), each gate portion GS intersecting the active layer AL in a projection on a plane where the active layer AL is located.

As shown in fig. 22, each first transistor M1_6 of the third pixel driving circuit 160 in the sixth sub-area SA6 includes an active layer AL and a gate insulating layer GI that insulates and spaces a gate GT of the first transistor M1_6 from the active layer, and the gate GT of the first transistor M1_6 in the sixth sub-area SA6 includes at least one (e.g., six) gate portions GS, each of which intersects the active layer AL in a projection on a plane where the active layer AL is located.

In some embodiments, in the first transistor M1 of the third pixel driving circuit 160 at least in part of the sub region SA, the active layer AL includes the interconnected polysilicon layer PSI and the oxide semiconductor layer OXD. As shown in fig. 21, for example, in the present embodiment, the active layer AL of the first transistor M1_5 of the third pixel driving circuit 160 in the fifth sub-area SA5 includes the polysilicon layer PSI and the oxide semiconductor layer OXD which are interconnected. Wherein the volume fraction of the oxide semiconductor layer OXD occupying the source layer AL in each first transistor M1_6 of the third pixel drive circuit 160 within the sixth sub-area SA6 is greater than the volume fraction of the oxide semiconductor layer OXD occupying the source layer AL in each first transistor M1_5 of the third pixel drive circuit 160 within the fifth sub-area SA5, such that the first transistor M1_6 of the sixth sub-area SA6 is able to achieve a lower leakage current than the first transistor M1_5 of the fifth sub-area SA 5.

In some embodiments, in the plurality of sub-regions SA, the volume fraction of the oxide semiconductor layer OXD occupying the active layer AL in each first transistor M1 in each sub-region SA increases as the frequency of the first light emitting signal to which each first transistor M1 responds in the light emitting phase in each sub-region SA decreases.

For example, in the plurality of sub-regions SA, the active layer AL in each first transistor M1 of the third pixel driving circuit 160 in the sub-region SA adjacent to the first display region AA1 is entirely the polysilicon layer PSI, i.e., the volume occupying ratio of the oxide semiconductor layer OXD occupying the active layer AL is 0. The active layer AL in each first transistor M1 of the third pixel driving circuit 160 in the sub-area SA adjacent to the second display area AA2 is entirely an oxide semiconductor layer OXD, i.e., the volume fraction of the oxide semiconductor layer OXD occupying the active layer AL is 100%.

The frequencies of the first light-emitting signals to which the first transistor M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 responds in the light-emitting phase are 60Hz, 50Hz, 40Hz, 30Hz, 20Hz, 10Hz in the direction Q along the first display region AA1 toward the second display region AA2, and correspondingly, the volume occupation ratio of the oxide semiconductor layer OXD in each first transistor M1 of the third pixel driving circuit 160 in the 6 sub-regions SA of the transition display region AA3 increases in the direction Q along the first display region AA1 toward the second display region AA 2. By configuring the active layer AL of the first transistor M1 in each sub-area SA, each first transistor M1 can satisfy the requirement of leakage current, which facilitates the implementation of the gradual and uniform gradual driving of the light emitting frequency of the third light emitting element 130 in the transitional display area AA 3.

Referring to fig. 1, in some embodiments, the display panel 100 further includes a non-display area NA surrounding the first display area AA1, the second display area AA2 and the transition display area AA 3.

Fig. 23 is a schematic structural diagram of a transition display area and a part of a non-display area of a display panel according to an embodiment of the invention. In the present embodiment, the transitional display area AA3 is described as including 6 sub-areas SA, and each sub-area SA has a row of the third light emitting elements 130 and a row of the third pixel driving circuits 160. In other embodiments, the transition display area AA3 includes the number of sub-areas SA, the number of rows of the third light emitting elements 130 in each sub-area SA, and the number of rows of the third pixel driving circuits 160.

In some embodiments, the non-display region is provided with a gate driving circuit 170, and the gate driving circuit 170 includes a plurality of gate driving units 171 connected in cascade. The gate driving unit 171 is connected to at least one end of the third pixel driving circuit 160 in the row direction, and the gate driving unit 171 can input the first light emission signal Emit1 to the connected third pixel driving circuit 160 in one row.

In some embodiments, in the direction Q from the first display area AA1 to the second display area AA2, the frequency of the first light-emitting signal Emit1 to which the first light-emitting control units 164 of the third pixel driving circuits 160 respectively arranged in the plurality of sub-areas SA respond in the light-emitting period decreases, and accordingly, in the direction Q from the first display area AA1 to the second display area AA2, the frequency of the first light-emitting signal Emit1 to which the gate driving units 171 respectively connected to the third pixel driving circuits 160 respectively arranged in the plurality of sub-areas SA decreases. For example, in the present embodiment, each sub-area SA is arranged with one row of the third pixel driving circuits 160, and the frequency of the first light emitting signal Emit1 of the gate driving unit 171 connected to the row-by-row third pixel driving circuits 160 decreases in the direction Q from the first display area AA1 to the second display area AA 2.

In fig. 23, the transmission direction of the first light emission signal Emit1 supplied from the gate driving unit 171 to the third pixel driving circuit 160 is shown by an arrow. In the embodiment shown in fig. 23, the gate driving units 171 are connected to two opposite ends of each row of the third pixel driving circuits 160 in the row direction, and the two gate driving units 171 connected to each row of the third pixel driving circuits 160 provide the first light-emitting signal Emit1 to the third pixel driving circuits 160, and the pixel driving method related to the first light-emitting signal Emit1 may be referred to as a double-edge driving method.

However, the pixel driving method related to the first emission signal Emit1 may not be limited to the above example, and may be other driving methods according to the design requirement of the display panel 100.

For example, fig. 24 is a schematic structural diagram of a transition display area and a partial non-display area of a display panel according to still another embodiment of the invention. In fig. 24, the transmission direction of the first light emission signal Emit1 supplied from the gate driving unit 171 to the third pixel driving circuit 160 is shown by an arrow. Unlike the previous embodiment, in the present embodiment, the gate driving units 171 are connected to the third pixel driving circuits 160 of each row at opposite ends in the row direction, one of the gate driving units 171 connected to the third pixel driving circuits 160 of each row supplies the first light-emitting signal Emit1 to the third pixel driving circuits 160, and the gate driving units 171 actually supplying the first light-emitting signals Emit1 corresponding to the third pixel driving circuits 160 of adjacent rows are respectively located at different sides in the row direction of the third pixel driving circuits 160. For example, the pixel driving method related to the first light-emitting signal Emit1 in this embodiment may be referred to as a serpentine driving method, in which the gate driving unit 171 connected to the left side of the third pixel driving circuit 160 in one row actually provides the first light-emitting signal Emit1, and the gate driving unit 171 connected to the right side of the third pixel driving circuit 160 in the adjacent row to the third pixel driving circuit 160 in this row actually provides the first light-emitting signal Emit 1.

For another example, fig. 25 is a schematic structural diagram of a transitional display area and a portion of a non-display area of a display panel according to another embodiment of the invention. In fig. 25, the transmission direction of the first light emission signal Emit1 supplied from the gate driving unit 171 to the third pixel driving circuit 160 is shown by an arrow. Unlike the previous embodiments, in the present embodiment, the gate driving unit 171 is connected to one end of the third pixel driving circuit 160 in the row direction, and the gate driving unit 171 is not connected to both ends of the third pixel driving circuit 160. Therefore, the third pixel driving circuit 160 supplies the first light emission signal Emit1 from one gate driving unit 171 to which it is connected per row. The pixel driving method according to the first emission signal Emit1 in the present embodiment may be referred to as a one-side driving method. In the present embodiment, the connected gate driving units 171 corresponding to the third pixel driving circuits 160 in the adjacent rows are respectively located at different sides of the third pixel driving circuits 160 in the row direction. For example, the left side of the row of the third pixel driving circuits 160 is connected to the gate driving unit 171 and provides the first light emitting signal Emit1 therefrom, and the third pixel driving circuits 160 of the rows adjacent to the row of the third pixel driving circuits 160 are connected to the right side of the gate driving unit 171 and actually provide the first light emitting signal Emit1 therefrom. In some other monolithic driving methods, the connected gate driving units 171 corresponding to the third pixel driving circuits 160 in each row may be located on the same side of the third pixel driving circuits 160 in the row direction.

The embodiment of the invention also provides a display device, and the display device is an electronic device with a display function, such as a mobile phone, a tablet computer and the like. The display device includes the display panel 100 of any of the foregoing embodiments. The display panel 100 includes a first display area AA1, a second display area AA2, and a transition display area AA3 between the first display area AA1 and the second display area AA 2. The display panel 100 includes a plurality of first light emitting elements 110, a plurality of second light emitting elements 120, and a plurality of second light emitting elements 120. Wherein, the plurality of first light emitting elements 110 are located in the first display area AA 1. The plurality of second light emitting elements 120 are positioned at the second display area AA 2. The light emitting frequency of the second light emitting element 120 in the light emitting stage is lower than that of the first light emitting element 110 in the light emitting stage, so that the second display area AA2 consumes less power when displaying a still picture.

According to the display device of the embodiment of the invention, in the display panel 100, the light emitting frequency of at least part of the third light emitting elements 130 in the transition display area AA3 in the light emitting stage is between the light emitting frequency of the first light emitting element 110 in the light emitting stage and the light emitting frequency of the second light emitting element 120 in the light emitting stage, so that the difference of the display effect caused by the difference of the light emitting frequency between the first display area AA1 and the second display area AA2 is alleviated, even avoided, the flicker or ripple defect occurring between the first display area AA1 and the second display area AA2 in the display state of the display panel 100 is alleviated, and the display effect of the display panel and the display device in the first display area AA1 and the second display area AA2 with different light emitting frequencies is improved.

In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel comprising a first display region, a second display region, and a transition display region between the first display region and the second display region, the display panel comprising:

a plurality of first light emitting elements positioned in the first display region;

a plurality of second light emitting elements located in the second display region, the light emitting frequency of the second light emitting elements in the light emitting stage being lower than the light emitting frequency of the first light emitting elements in the light emitting stage; and

and the plurality of third light-emitting elements are positioned in the transitional display area, and the light-emitting frequency of at least part of the third light-emitting elements in the light-emitting stage is lower than that of the first light-emitting elements in the light-emitting stage and higher than that of the second light-emitting elements in the light-emitting stage.

2. The display panel according to claim 1, wherein the transition display region comprises a plurality of sub-regions arranged in a direction from the first display region to the second display region, each of the sub-regions being arranged with at least one row of the third light-emitting elements, wherein a light-emitting frequency of the third light-emitting elements of the plurality of sub-regions in a light-emitting period decreases in a direction from the first display region to the second display region.

3. The display panel according to claim 1, characterized in that the display panel further comprises:

a third pixel driving circuit located in the transitional display area, the third pixel driving circuit being electrically connected to the third light emitting element for driving the third light emitting element to emit light,

wherein the third pixel driving circuit includes:

a data writing unit for transmitting a data signal;

the driving unit is used for generating a driving current according to the data signal of the data writing unit;

a storage unit for storing the data signal transmitted to the driving unit;

a first light emitting control unit connected between a power supply terminal and the driving unit or connected between the driving unit and the third light emitting element, the first light emitting control unit being configured to respond to a first light emitting signal in a light emitting phase so that the third light emitting element receives the driving current which is periodically and intermittently turned on in the light emitting phase.

4. The display panel according to claim 3, wherein the first light emission control unit is connected between the driving unit and the third light emitting element.

5. The display panel according to claim 4, wherein the first light emission control unit comprises:

a gate of the first transistor is connected to a first light-emitting signal terminal, a first pole of the first transistor is connected to the driving unit, and a second pole of the first transistor is connected to the third light-emitting element.

6. The display panel according to claim 4, the third pixel drive circuit further comprising:

a second light-emitting control unit connected between a power terminal and the driving unit, the second light-emitting control unit being configured to respond to a continuously-turned-on second light-emitting signal in a light-emitting period so as to continuously turn on between the power terminal and the driving unit in the light-emitting period.

7. The display panel according to claim 6, wherein the second light emission control unit comprises:

and the grid electrode of the second transistor is connected with a second light-emitting signal end, the first pole of the second transistor is connected with the power supply end, and the second pole of the second transistor is connected with the driving unit.

8. The display panel according to claim 3, wherein the transition display region includes a plurality of sub-regions arranged in a direction from the first display region to the second display region, each of the sub-regions being arranged with at least one row of the third pixel driving circuits, wherein a frequency of the first light emission signal to which the first light emission control units of the third pixel driving circuits respectively arranged in the plurality of sub-regions respond in a light emission phase decreases in a direction from the first display region to the second display region.

9. The display panel according to claim 8, wherein the difference between the frequencies of the first light emission signals to which the first light emission control units of the third pixel driving circuits in every two adjacent sub-regions respond in a light emission phase is equal.

10. The display panel according to claim 8, wherein the first light emission control unit comprises:

a first transistor, a gate of which is connected to a first light emitting signal terminal, a first pole of which is connected to the driving unit, and a second pole of which is connected to the third light emitting element,

the first transistor comprises an active layer and a gate insulating layer which insulates and separates a gate electrode of the first transistor from the active layer, the gate electrode of the first transistor comprises at least one gate electrode part, and projection of each gate electrode part on a plane where the active layer is located intersects with the active layer.

11. The display panel according to claim 10, wherein the plurality of sub-regions include a first sub-region and a second sub-region, wherein the second sub-region is located on a side of the first sub-region close to the second display region, and wherein each of the first transistors of the third pixel driving circuits in the second sub-region includes a larger number of the gate portions than each of the first transistors of the third pixel driving circuits in the first sub-region.

12. The display panel according to claim 10, wherein in the first transistor of the third pixel driver circuit in at least part of the sub-region, the active layer comprises an interconnected polysilicon layer and an oxide semiconductor layer,

the extension direction of the polycrystalline silicon layer is crossed with the extension direction of the oxide semiconductor layer, the grid electrode of the first transistor comprises a first grid electrode part and a second grid electrode part, the first grid electrode part is interconnected with the second grid electrode part, the projection of the first grid electrode part on the plane where the active layer is located is vertically crossed with the polycrystalline silicon layer, and the projection of the second grid electrode part on the plane where the active layer is located is vertically crossed with the oxide semiconductor layer.

13. The display panel according to claim 12, wherein the plurality of sub-regions comprises a third sub-region and a fourth sub-region, wherein the fourth sub-region is located on a side of the third sub-region close to the second display region, and wherein each of the first transistors of the third pixel driving circuit in the fourth sub-region comprises a larger number of the second gate portions than each of the first transistors of the third pixel driving circuit in the third sub-region.

14. The display panel according to claim 10, wherein in the first transistor of the third pixel driver circuit in at least part of the sub-region, the active layer comprises an interconnected polysilicon layer and an oxide semiconductor layer,

wherein the plurality of sub-regions includes a fifth sub-region and a sixth sub-region, wherein the sixth sub-region is located on a side of the fifth sub-region close to the second display region, and a volume ratio of the oxide semiconductor layer in each of the first transistors of the third pixel driving circuits in the sixth sub-region to the active layer is larger than a volume ratio of the oxide semiconductor layer in each of the first transistors of the third pixel driving circuits in the fifth sub-region to the active layer.

15. A display device characterized by comprising the display panel according to any one of claims 1 to 14.