CN111477499A - Driving circuit device capable of setting release delay time of safety relay - Google Patents
Driving circuit device capable of setting release delay time of safety relay Download PDFInfo
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- CN111477499A CN111477499A CN202010244301.4A CN202010244301A CN111477499A CN 111477499 A CN111477499 A CN 111477499A CN 202010244301 A CN202010244301 A CN 202010244301A CN 111477499 A CN111477499 A CN 111477499A
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- nand gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
- H01H47/18—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay for introducing delay in the operation of the relay
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
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Abstract
The invention relates to the technical field of safety relays, in particular to a driving circuit device with settable release delay time of a safety relay. The invention adopts the potentiometer and the regulating switch to realize the setting of the release delay time of the safety relay; the method is realized by pure hardware, the realization mode is stable and reliable, all devices are conventional universal devices, the actual batch production is convenient, the applicability is strong, the cost is low, and the result is controllable.
Description
Technical Field
The invention relates to the technical field of safety relays, in particular to a driving circuit device with settable release delay time of a safety relay.
Background
With the continuous generation of safety production problems in the industrial production process, the industrial production safety is increasingly emphasized by people, and the safety production method is particularly important in the field of port machinery and cranes which often relate to the safety of people and mechanical equipment. With the emergence and continuous development of system safety theory in recent 20 years, the research on the safety problem of industrial production reaches a new stage, and the safety relay is used as one of safety product families, and the application of the safety relay is gradually widened. The safety relay is not a relay without a fault but a relay which makes regular action when a fault occurs, has a forced guide contact structure, can ensure safety in case of contact fusion, is completely different from the conventional relay, is specially designed for a demanding task or safety-related application, and does not bring danger to personnel safety or process safety when the safety relay fails.
Because the process of partial automation equipment is complex, when the equipment needs to be stopped emergently, the main contactor in the equipment cannot carry out breaking operation, and a safety relay with time delay disconnection is needed; because the delay time required by different devices is different in length, the safety relay with fixed delay output cannot meet the requirements of wide application client groups, and therefore the development of the safety relay with the release delay time capable of being set is particularly important.
At present, the existing delay output safety relay products at home and abroad have the following two realization methods:
1. the method is realized by a pure hardware circuit, but the set delay time range is narrow, so that the method is not beneficial to the application of various industries;
2. hardware and an embedded type are combined to realize, but the cost of the product is increased due to the introduction of the embedded type; and because the failure mode of the embedded chip cannot be well defined, some uncontrollable results are easy to occur.
Disclosure of Invention
The invention provides a drive circuit device capable of setting the release delay time of a safety relay, which realizes the setting of the delay time by adjusting a switch and a potentiometer and has a stable and reliable realization mode.
In order to realize the purpose of the invention, the adopted technical scheme is as follows: a drive circuit device with settable release delay time of a safety relay comprises an optical coupling input circuit, a combinational logic circuit, an RC oscillation circuit, a regulating switch circuit, a programmable timing circuit and a bistable circuit, wherein the optical coupling input circuit is used for converting a switching value input signal of the safety relay into a logic level signal and transmitting the logic level signal to the combinational logic circuit and the bistable circuit, the combinational logic circuit triggers the programmable timing circuit to enter a reset or delay state according to the logic level signal generated by the optical coupling input circuit and an output control signal of the safety relay, the RC oscillation circuit is used for changing the oscillation frequency of the programmable timing circuit, the regulating switch circuit is used for generating a digital frequency division signal to the programmable timing circuit, the programmable timing circuit sets a pulse signal of the delay time to the bistable circuit according to the digital frequency division signal generated by the regulating switch circuit, the oscillation frequency signal provided by the RC oscillation circuit and the delay state triggered by the combinational logic circuit, the bistable circuit outputs an output control signal of the safety relay according to a logic level signal generated by the optical coupling input circuit and a pulse signal of delay time generated by the programmable timing circuit.
As an optimized scheme of the invention, the RC oscillating circuit comprises a first potentiometer RP1, the first potentiometer RP1 is connected with the programmable timing circuit, and the oscillating frequency of the programmable timing circuit is changed by adjusting the first potentiometer RP 1.
As an optimized scheme of the invention, the adjusting switch circuit comprises a first adjusting switch S1, the first adjusting switch S1 is connected with the programmable timing circuit, and the position of the first adjusting switch S1 is changed to output a digital frequency division signal to the programmable timing circuit.
The optical coupling input circuit comprises a first resistor R1, a first capacitor C1, a first optical coupler U1, a second resistor R2, a third resistor R3, a second capacitor C2, a fourth resistor R4 and a triode Q1, wherein the first resistor R1 is connected between a switching value input signal end of the safety relay and an anode of the first optical coupler U1, the first capacitor C1 is connected between an anode of the first optical coupler U1 and the ground, the second resistor R2 is connected between an emitter of the first optical coupler U1 and the third resistor R3, the third resistor R3 and the second capacitor C2 are connected between a base of the triode Q1 and the ground in parallel, and the fourth resistor R4 is connected between a power supply VCC and a collector of the triode Q1.
As an optimized scheme of the invention, the combinational logic circuit comprises a first NAND gate U2A, one input end of the first NAND gate U2A is connected with the output end of the optical coupling input circuit, the other input end of the first NAND gate U2A is connected with the output control signal output end of the safety relay, and the output end of the first NAND gate U2A is connected with the programmable timing circuit.
As an optimized scheme of the invention, the programmable timing circuit comprises a first programmable timing chip U3 and a second NAND gate U2B, wherein the input end of the second NAND gate U2B is connected with the first programmable timing chip U3, and the output end of the second NAND gate U2B is connected with the bistable circuit.
As an optimized solution of the present invention, the bistable circuit includes a third nand gate U2C, a fourth nand gate U2D, a fifth capacitor C5 and a sixth capacitor C6, one input of the third nand gate U2C is connected to the programmable timing circuit, the other input of the third nand gate U2C is connected to the output of the fourth nand gate U2D, the fifth capacitor C5 is connected between one input of the third nand gate U2C and ground, one input of the fourth nand gate U2D is connected to the output of the third nand gate U2C, the other input of the fourth nand gate U2D is connected to the output of the optical coupling input circuit, and the sixth capacitor C6 is connected between VCC and the output of the third nand gate U2C.
The invention has the positive effects that 1) the potentiometer and the regulating switch are combined to realize the setting of the release delay time of the safety relay, and the total delay time T is N × T, wherein N is a multiple set by the regulating switch, and T is the minimum time base unit set by the potentiometer;
2) the invention is realized by pure hardware, has stable and reliable realization mode, is convenient for actual batch production, has strong applicability, low cost and controllable result, and all devices are conventional universal devices.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a schematic circuit connection diagram of an optocoupler input circuit;
FIG. 3 is a schematic circuit diagram of a combinational logic circuit;
FIG. 4 is a schematic circuit diagram of an RC oscillator circuit;
FIG. 5 is a schematic circuit connection diagram of the regulating switch circuit;
FIG. 6 is a schematic circuit connection diagram of a programmable timing circuit;
FIG. 7 is a schematic circuit diagram of a bistable circuit;
fig. 8 is safety relay release delay timing logic.
Wherein: 1. the circuit comprises an optical coupling input circuit 2, a combinational logic circuit 3, an RC oscillating circuit 4, an adjusting switch circuit 5, a programmable timing circuit 6 and a bistable circuit.
Detailed Description
As shown in figure 1, the invention discloses a drive circuit device with settable release delay time of a safety relay, which comprises an optical coupling input circuit 1, a combinational logic circuit 2, an RC oscillating circuit 3, an adjusting switch circuit 4, a programmable timing circuit 5 and a bistable circuit 6, wherein the optical coupling input circuit 1 is used for converting a switching value input signal of the safety relay into a logic level signal and transmitting the logic level signal to the combinational logic circuit 2 and the bistable circuit 6, the combinational logic circuit 2 triggers the programmable timing circuit 5 to enter a reset or delay state according to the logic level signal generated by the optical coupling input circuit 1 and an output control signal of the safety relay, the RC oscillating circuit 3 is used for changing the oscillation frequency of the programmable timing circuit 5, the adjusting switch circuit 4 is used for generating a digital frequency division signal to the programmable timing circuit 5, and the programmable timing circuit 5 is used for generating a digital frequency division signal, a digital frequency division signal and, The oscillation frequency signal provided by the RC oscillation circuit 3 and the pulse signal of the delay time set by the delay state triggered by the combinational logic circuit 2 are sent to the bistable circuit 6, and the bistable circuit 6 outputs the output control signal of the safety relay according to the logic level signal generated by the optical coupler input circuit 1 and the pulse signal of the delay time generated by the programmable timing circuit 5.
As shown in fig. 2, the optical coupling input circuit 1 includes a first resistor R1, a first capacitor C1, a first optical coupler U1, a second resistor R2, a third resistor R3, a second capacitor C2, a fourth resistor R4, and a transistor Q1, the first resistor R1 is connected between a switching value input signal terminal of the safety relay and an anode of a first optical coupler U1, the first capacitor C1 is connected between an anode of the first optical coupler U1 and ground, a cathode of the first optical coupler U1 is grounded, a collector of the first optical coupler U1 is connected to VCC, the second resistor R2 is connected between an emitter of the first optical coupler U1 and a third resistor R3, the third resistor R3 and the second capacitor C2 are connected in parallel between a base of a transistor Q1 and ground, the fourth resistor R4 is connected between the power VCC and a collector of the transistor Q1, and an emitter of the transistor Q1 is grounded.
As shown in fig. 3, the combinational logic circuit 2 includes a first nand gate U2A, one input terminal of the first nand gate U2A is connected to the output terminal of the opto-coupler input circuit 1, the other input terminal of the first nand gate U2A is connected to the output control signal output terminal of the safety relay, the output terminal of the first nand gate U2A is connected to the programmable timing circuit 5, the 1 st pin of the first nand gate U2A is connected to the collector of the transistor Q1, the 2 nd pin of the first nand gate U2A is connected to the output control signal output terminal of the safety relay, the 3 rd pin of the first nand gate U2A is connected to the 2 nd pin of the first programmable timing chip U3, so that when the input signal is at low level and the output signal is at high level, the first programmable timing chip U3 can achieve delayed output, and the truth table of the reset signal is shown in table 1.
Table 1 reset signal truth table
As shown in fig. 4, the RC oscillation circuit 3 includes a first potentiometer RP1, a fifth resistor R5, a third capacitor C3 and a sixth resistor R6, the first potentiometer RP1 is connected to the programmable timing circuit 5, and the oscillation frequency of the programmable timing circuit 5 is changed by adjusting the first potentiometer RP 1. The fifth resistor R5 is connected between the 3 rd pin of the first programmable timing chip U3 and the third capacitor C3, the third capacitor C3 is connected between the fifth resistor R5 and the 4 th pin of the first programmable timing chip U3, the sixth resistor R6 is connected between the 5 th pin of the first programmable timing chip U3 and the first potentiometer RP1, and the oscillation frequency of the first programmable timing chip U3 can be changed by adjusting the first potentiometer RP 1.
As shown in fig. 5, the adjustment switch circuit 4 includes a first adjustment switch S1, an eighth resistor R8, and a ninth resistor R9, the first adjustment switch S1 is connected to the programmable timing circuit 5, and outputs a digital frequency-divided signal to the programmable timing circuit 5 by changing the position of the first adjustment switch S1. The eighth resistor R8 is connected between pin 3 of the first adjustment switch S1 and ground, and the ninth resistor R9 is connected between pin 6 of the first adjustment switch S1 and ground, so that the user can output different digital code signals to the first programmable timing chip U3 by changing the position of the first adjustment switch S1, thereby realizing different frequency division coefficients, and the truth table of the adjustment switches is shown in table 2.
TABLE 2 regulating switch truth table
As shown in fig. 6, the programmable timing circuit 5 includes a first programmable timing chip U3, a second nand gate U2B, a fourth capacitor C4 and a seventh resistor R7, wherein an input terminal of the second nand gate U2B is connected to the first programmable timing chip U3, and an output terminal of the second nand gate U2B is connected to the bistable circuit 6. The fourth capacitor C4 is connected between VCC and the 1 st pin of the first programmable timing chip U3, the 9 th pin of the first programmable timing chip U3 is connected with the 3 rd pin of the first adjusting switch S1, the 10 th pin of the first programmable timing chip U3 is connected with the 6 th pin of the first adjusting switch S1, the 13 th pin and the 14 th pin of the first programmable timing chip U3 are connected with the 5 th pin of the second NAND gate U2B, and the first programmable timing chip U3 is determined to enter a reset or timing state through oscillation frequency and digital frequency division signals and combined with the change of a reset signal.
As shown in fig. 7, the bistable circuit 6 includes a third nand gate U2C, a fourth nand gate U2D, a fifth capacitor C5 and a sixth capacitor C6, one input terminal of the third nand gate U2C is connected to the programmable timing circuit 5, the 8 th pin of the third nand gate U2C is connected to the 4 th pin of the second nand gate U2B, the other input terminal of the third nand gate U2C is connected to the output terminal of the fourth nand gate U2D, the fifth capacitor C5 is connected between one input terminal of the third nand gate U2C and ground, one input terminal of the fourth nand gate U2D is connected to the output terminal of the third nand gate U2C, the other input terminal of the fourth nand gate U2D is connected to the output terminal of the optical coupling input circuit 1, the 13 th pin of the fourth nand gate U2D is connected to the 1 st pin of the first nand gate U2A, and the sixth capacitor C6 is connected between VCC and the output terminal of the third nand gate U2C. According to the states of the input signal and the delayed pulse signal, the output signal is realized to reach a stable state through the bistable circuit 6, and the bistable truth table is shown in table 3.
TABLE 3 Bistable circuit truth table
The principle of the driving circuit device with the adjustable release delay time of the safety relay is described in detail with reference to fig. 1 to 8.
When the Input is at a high level (attraction of the safety relay is achieved), an Input signal passes through the first resistor R1 and the diode of the first optocoupler U1, so that the primary side of the first optocoupler U1 is conducted, and then the emitter of the first optocoupler U1 generates a high level signal. The optical coupler input circuit 1 can realize the electrical isolation and level conversion of input signals. After a high-level signal generated by an emitter of the first optocoupler U1 passes through an inverter formed by the transistor Q1 and the fourth resistor R4, a collector of the transistor Q1 generates a low-level signal, that is, a 13 th pin of the fourth nand gate U2D is a low-level signal. According to the 3 rd row of the truth table in table 1, the 2 nd pin of the first programmable timer chip U3 is at a high level, which makes the first programmable timer chip U3 enter a reset state, thereby reducing the power consumption of the whole system, and the 13 th pin of the first programmable timer chip U3 outputs a low level signal, which passes through the second nand gate U2B to generate a high level signal at the 4 th pin of the second nand gate U2B, i.e., the 8 th pin of the third nand gate U2C is at a high level signal. At this time, two input signals of the bistable circuit 6 composed of the third nand gate U2C and the fourth nand gate U2D are determined, the 1 st line in the bistable truth table shown in the table look-up 3 is available, and at this time, the output driving signal is at a high level, so that when the input signal in fig. 8 is at a high level, the output control signal of the safety relay is synchronously output at a high level.
When the input signal changes from high level to low level (delayed release of the safety relay is realized), the high level signal is generated at the collector of the triode Q1 through the first optocoupler U1 and the triode Q1, that is, the 13 th pin of the fourth nand gate U2D is a high level signal. The output driving signal keeps high level unchanged as the 3 rd row in the bistable truth table shown in the table look-up 3 is available. Since the input signal is low and the output driving signal is high, it can be obtained according to line 2 of the truth table of table 1, pin 2 of the first programmable timing chip U3 is low, and the first programmable timing chip U3 enters the timing phase.
The timing time is determined by the resistance of the first potentiometer RP1, the resistance of the sixth resistor R6, the capacitance of the third capacitor C3, and the adjustment position of the first adjustment switch S1. Assume that the resistance of the first potentiometer RP1 is RaThe resistance value of the sixth resistor is RbThe capacitance value of the third capacitor is CaThe adjustment position of the first adjustment switch is "3", and the calculation formula of the timing time T known from the data manual of the first programmable timing chip U3 is as follows:
T＝2(n-1)×2.3×Rtc×C
wherein R istcIn order to obtain the resistance value of the oscillation resistor, C is the capacitance value of the oscillation capacitor, n is the frequency division number of the first programmable timing chip, and is determined by the level signals of pins 6, 9, 10, 11 and 12 of the first programmable timing chip U3, since the current level average of the pin 6, the pin 11 and the pin 12 of the first programmable timing chip U3 is known fixedly, the above calculation formula can be converted into:
T＝2(13-1)×N×2.3×(Ra+Rb)×Ca
from the current position "3" of the first adjustment switch S1, look-up table 2 may be used, where N is 4. The user can adjust the resistance value of the first potentiometer RP1 and the position of the rotary adjusting switch according to the time delay time required to be set. To facilitate easier calculation of the delay time by the user, the product has mapped the angle of rotation of the first potentiometer RP1 to the respective smallest time base unit t on the meter housing, and the position of the first adjustment switch S1 has also mapped to the respective multiple N on the meter housing.
When the time exceeds the timing time T, the 13 th pin of the first programmable timing chip U3 outputs a high level, and after passing through the second nand gate U2B, a high level signal is generated at the 4 th pin of the second nand gate U2B, i.e., the 8 th pin of the third nand gate U2C is a high level signal. The row 2 in the bistable truth table shown in the table look-up 3 can be obtained, the output control signal of the safety relay outputs low level, and then the release delay of the safety relay is realized.
After the safety relay is released in a delayed mode, at the moment, because the input signal and the output signal are both changed into low level, the input signal and the output signal can be obtained according to the line 1 in the table 1, the 2 nd pin of the first programmable timing chip U3 is changed into high level, and the first programmable timing chip U3 enters a reset state again to wait for the triggering of the delay signal at the next time.
The principle of the driving circuit device with the settable release delay time of the safety relay has completely realized the sequential logic requirement of fig. 8.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides a drive circuit device that safety relay release time delay can be established which characterized in that: the circuit comprises an optical coupling input circuit (1), a combinational logic circuit (2), an RC oscillation circuit (3), an adjusting switch circuit (4), a programmable timing circuit (5) and a bistable circuit (6), wherein the optical coupling input circuit (1) is used for converting a switching value input signal of a safety relay into a logic level signal and transmitting the logic level signal to the combinational logic circuit (2) and the bistable circuit (6), the combinational logic circuit (2) triggers the programmable timing circuit (5) to enter a reset or delay state according to the logic level signal generated by the optical coupling input circuit (1) and an output control signal of the safety relay, the RC oscillation circuit (3) is used for changing the oscillation frequency of the programmable timing circuit (5), the adjusting switch circuit (4) is used for generating a digital frequency division signal to the programmable timing circuit (5), and the programmable timing circuit (5) generates the digital frequency division signal according to the adjusting switch circuit (4), An oscillation frequency signal provided by the RC oscillation circuit (3) and a pulse signal of which the delay time is set by a delay state triggered by the combinational logic circuit (2) are sent to the bistable circuit (6), and the bistable circuit (6) outputs an output control signal of the safety relay according to a logic level signal generated by the optical coupler input circuit (1) and the pulse signal of which the delay time is generated by the programmable timing circuit (5).
2. The safety relay release delay time settable drive circuit arrangement according to claim 1, wherein: the RC oscillating circuit (3) comprises a first potentiometer RP1, the first potentiometer RP1 is connected with the programmable timing circuit (5), and the oscillating frequency of the programmable timing circuit (5) is changed by adjusting the first potentiometer RP 1.
3. The safety relay release delay time settable drive circuit arrangement according to claim 2, wherein: the adjusting switch circuit (4) comprises a first adjusting switch S1, the first adjusting switch S1 is connected with the programmable timing circuit (5), and the position of the first adjusting switch S1 is changed to output a digital frequency division signal to the programmable timing circuit (5).
4. A safety relay release delay time settable drive circuit arrangement according to claim 3, wherein: the optical coupler input circuit (1) comprises a first resistor R1, a first capacitor C1, a first optical coupler U1, a second resistor R2, a third resistor R3, a second capacitor C2, a fourth resistor R4 and a triode Q1, wherein the first resistor R1 is connected between a switching value input signal end of the safety relay and an anode of a first optical coupler U1, the first capacitor C1 is connected between an anode of the first optical coupler U1 and the ground, the second resistor R2 is connected between an emitter of the first optical coupler U1 and the third resistor R3, the third resistor R3 and the second capacitor C2 are connected between a base of a triode Q1 and the ground in parallel, and the fourth resistor R4 is connected between a power supply VCC and a collector of a triode Q1.
5. The safety relay release delay time settable drive circuit arrangement according to claim 4, wherein: the combinational logic circuit (2) comprises a first NAND gate U2A, one input end of the first NAND gate U2A is connected with the output end of the optical coupling input circuit (1), the other input end of the first NAND gate U2A is connected with the output control signal output end of the safety relay, and the output end of the first NAND gate U2A is connected with the programmable timing circuit (5).
6. The safety relay release delay time settable drive circuit arrangement according to claim 5, wherein: the programmable timing circuit (5) comprises a first programmable timing chip U3 and a second NAND gate U2B, wherein the input end of the second NAND gate U2B is connected with the first programmable timing chip U3, and the output end of the second NAND gate U2B is connected with the bistable circuit (6).
7. The safety relay release delay time settable drive circuit arrangement according to claim 6, wherein: the bistable circuit (6) comprises a third NAND gate U2C, a fourth NAND gate U2D, a fifth capacitor C5 and a sixth capacitor C6, one input end of the third NAND gate U2C is connected with the programmable timing circuit (5), the other input end of the third NAND gate U2C is connected with the output end of the fourth NAND gate U2D, the fifth capacitor C5 is connected between one input end of the third NAND gate U2C and the ground, one input end of the fourth NAND gate U2D is connected with the output end of the third NAND gate U2C, the other input end of the fourth NAND gate U2D is connected with the output end of the optical coupling input circuit (1), and the sixth capacitor C6 is connected between VCC and the output end of the third NAND gate U2C.
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