CN111477470B - Asymmetric high-voltage chip type energy storage device and preparation method and application thereof - Google Patents

Asymmetric high-voltage chip type energy storage device and preparation method and application thereof Download PDF

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CN111477470B
CN111477470B CN202010184530.1A CN202010184530A CN111477470B CN 111477470 B CN111477470 B CN 111477470B CN 202010184530 A CN202010184530 A CN 202010184530A CN 111477470 B CN111477470 B CN 111477470B
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energy storage
storage device
area
silicon wafer
mask
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CN111477470A (en
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张海涛
谢岩廷
杨维清
黄海超
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Sichuan Jinshi Xinneng Technology Co.,Ltd.
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Sichuan Jinshi Xinneng Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/04—Hybrid capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/04—Hybrid capacitors
    • H01G11/06—Hybrid capacitors with one of the electrodes allowing ions to be reversibly doped thereinto, e.g. lithium ion capacitors [LIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/22—Electrodes
    • H01G11/26—Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00—Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof
    • H01G11/84—Processes for the manufacture of hybrid or EDL capacitors, or components thereof
    • H01G11/86—Processes for the manufacture of hybrid or EDL capacitors, or components thereof specially adapted for electrodes

Abstract

An asymmetric high-voltage chip type energy storage device and a preparation method and application thereof belong to the technical field of energy storage. The preparation method of the asymmetric high-voltage chip type energy storage device comprises the following steps: covering the first mask on the surface of the silicon wafer and processing to form a first area and a second area in the shape of an interdigital electrode, removing the first mask of the first area to expose the positive electrode area and the negative electrode area on the surface of the silicon wafer, and forming gold current collectors in the positive electrode area and the negative electrode area on the surface of the silicon wafer. Covering the second mask on the anode region and the cathode region respectively, and spraying electrode materials corresponding to the electrode region which is not covered with the second mask, so that the silicon wafer forms an anode and a cathode respectively. And pouring an electrolyte material on the surface of the silicon wafer and packaging to obtain the asymmetric high-voltage chip type energy storage device. According to the method, different electrode materials can be selected according to actual requirements to form the positive electrode and the negative electrode, and then the asymmetric high-voltage chip type energy storage device with the asymmetric structure is manufactured according to the mass ratio of the positive electrode and the negative electrode which are matched in a calculation mode.

Description

Asymmetric high-voltage chip type energy storage device and preparation method and application thereof
Technical Field
The application relates to the technical field of energy storage, in particular to an asymmetric high-voltage chip type energy storage device and a preparation method and application thereof.
Background
The super capacitor has the remarkable characteristics of higher energy storage density, larger discharge power, longer cycle life and the like, and plays an increasingly greater role in various aspects of energy power, transportation, aerospace, automobile industry, biomedical treatment and the like as a novel energy storage element.
The existing chip-type super capacitor and lithium ion capacitor preparation technology usually adopts a photoetching method and a thin film deposition method. However, the capacitor manufactured by the method is an asymmetric high-voltage chip type energy storage device with a symmetric structure, and no manufacturing method for the asymmetric high-voltage chip type energy storage device with the asymmetric structure exists at present.
Disclosure of Invention
The application provides an asymmetric high-voltage chip type energy storage device and a preparation method and application thereof, and the asymmetric high-voltage chip type energy storage device with an asymmetric structure can be prepared.
The embodiment of the application is realized as follows:
in a first aspect, the present application provides a method for manufacturing an asymmetric high-voltage chip-type energy storage device, including:
covering the surface of a silicon wafer with a first mask, processing the first mask on the surface of the silicon wafer to form a first area and a second area, wherein the first area forms an interdigital electrode shape, removing the first mask of the first area to expose the surface of the silicon wafer to an anode area and a cathode area, and forming gold current collectors in the anode area and the cathode area on the surface of the silicon wafer.
And respectively covering the anode region and the cathode region of the silicon wafer by adopting a second mask, spraying electrode materials corresponding to the electrode regions which are not covered by the second mask, wherein the electrode materials sprayed in the anode region and the cathode region are different, so that the silicon wafer respectively forms an anode and a cathode.
And removing the first mask of the second area, pouring an electrolyte material on the surface of the silicon wafer, and packaging to obtain the asymmetric high-voltage chip type energy storage device.
According to the technical scheme, the first mask is covered on the surface of the silicon wafer, the first mask on the surface of the silicon wafer is processed to form the first area and the second area, the interdigital electrode shape can be quickly formed on the surface of the silicon wafer, the processing time is short, batch processing can be carried out, the cost is extremely low, and the surface of the silicon wafer cannot be damaged.
And the second mask is adopted to cover the anode area and the cathode area of the silicon wafer respectively, and electrode materials corresponding to the electrode areas without covering the second mask are sprayed, so that the silicon wafer can form an anode and a cathode respectively, different electrode materials can be selected according to actual requirements to form the anode and the cathode, and then the mass ratio of the anode and the cathode is matched according to calculation to prepare the asymmetric high-voltage chip type energy storage device with the asymmetric structure.
In a first possible example of the first aspect of the present application in combination with the first aspect, the finger width of the first area in the shape of the interdigital electrode is 0.5 to 3mm, the finger length is 5 to 10 mm, the inter-finger distance is 0.2 to 0.5 mm, and the number of fingers is 2 to 10.
In the above example, the energy storage device manufactured by using the above interdigital electrode shape has a large capacity.
With reference to the first aspect, in a second possible example of the first aspect of the present application, when the positive electrode region and the negative electrode region forming the gold current collector are both recessed in the second region and are covered with the second mask respectively, the second mask is located on the upper side of the gold current collector and is not in direct contact with the gold current collector.
In the above example, the first region of the gold current collector is recessed in the second region, that is, the first region of the gold current collector is lower than the second region, so that the second mask is only in direct contact with the first mask when covering the positive electrode region and the negative electrode region of the silicon wafer, and due to the height difference relationship, the second mask is located on the upper side of the first region where the gold current collector is formed and is not in direct contact with the first region where the gold current collector is formed, thereby preventing the second mask from being directly connected to the surface of the gold current collector of the silicon wafer, and adhering the gold current collector to the second mask, which results in poor performance of the manufactured asymmetric high-voltage chip-type energy storage device.
In a third possible example of the first aspect of the present application in combination with the first aspect, the first mask comprises pi tape or polyethylene terephthalate paper.
Optionally, the second mask comprises pi tape or polyethylene terephthalate paper.
With reference to the first aspect, in a fourth possible example of the first aspect of the present application, when the gold current collector is formed in the first region on the surface of the silicon wafer, a simple chromium substance is first plated on the first region on the surface of the silicon wafer to form a chromium layer, and then a simple gold substance is plated on the surface of the chromium layer to form the gold current collector.
In the above example, the elemental gold and the silicon wafer have good connectivity with the chromium layer, and the elemental gold can be stably attached to the silicon wafer through the chromium layer, so that the elemental gold is effectively prevented from falling off.
With reference to the first aspect, in a fifth possible example of the first aspect of the present application, the electrode material of the negative electrode region includes MXene, and the electrode material of the positive electrode region includes activated carbon, lithium nickel cobalt manganese oxide, or lithium manganese oxide.
In a sixth possible example of the first aspect of the present application in combination with the first aspect, the above-mentioned electrolyte material includes a polyvinyl alcohol/sodium sulfate gel, a polyvinyl alcohol/sulfuric acid gel, or a lithium bis (trifluoromethanesulfonic acid) imide-1, 3-dioxolane/glyme gel.
In a seventh possible example of the first aspect of the present application, in combination with the first aspect, the encapsulating includes encapsulating with polydimethylsiloxane by using a mold molding method to obtain the asymmetric high-voltage chip-type energy storage device.
In the above example, the mold molding method can form a uniform polydimethylsiloxane layer on the surface of the silicon wafer, thereby effectively encapsulating the whole device.
In a second aspect, the present application provides an asymmetric high-voltage chip-type energy storage device, which is prepared according to the preparation method of the asymmetric high-voltage chip-type energy storage device.
In the technical scheme, the anode material and the cathode material of the asymmetric high-voltage chip type energy storage device are different, so that different anode materials and different cathode materials can be selected to improve the capacity of the asymmetric high-voltage chip type energy storage device.
In a second aspect, the application example provides an application of the asymmetric high-voltage chip-type energy storage device in a sensor, an internet of things and an integrated circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a flow chart of a manufacturing process of an asymmetric high-voltage chip-type energy storage device according to the present application;
FIG. 2 is a schematic structural diagram of a silicon wafer covered with a first mask according to the present application;
FIG. 3 is a schematic structural diagram of a silicon wafer with a first mask of a first region removed according to the present application;
FIG. 4 is a schematic structural diagram of a silicon wafer with a second mask covering the anode region according to the present application;
FIG. 5 is a schematic structural diagram of a silicon wafer with a cathode region covered by a second mask according to the present application;
FIG. 6 is a schematic diagram of a device packaged by a molding method according to the present application;
FIG. 7 is a schematic view of a chip-type supercapacitor made according to example 1 of the present application;
FIG. 8 is a schematic diagram of a series connection of chip-type supercapacitors made according to example 1 of the present application;
FIG. 9 is a comparison graph of cyclic voltammograms of the chip-type supercapacitors prepared in example 1 and comparative example 1 of the present application.
Icon: 10-a silicon wafer; 100-a first area; 200-a second region; 300-positive electrode region; 400-negative electrode area; 500-second mask.
Detailed Description
Embodiments of the present application will be described in detail below with reference to examples, but those skilled in the art will appreciate that the following examples are only illustrative of the present application and should not be construed as limiting the scope of the present application. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
The following detailed description is made for an asymmetric high-voltage chip type energy storage device, and a manufacturing method and an application thereof in the embodiments of the present application:
the application provides a preparation method of an asymmetric high-voltage chip type energy storage device, a flow chart of which is shown in figure 1, and the preparation method comprises the following steps:
(1) forming interdigital electrode shape on silicon wafer
As shown in fig. 2, a first mask is used to cover the surface of a silicon wafer 10, and the first mask on the surface of the silicon wafer is processed to form a first region 100 and a second region 200, wherein the first region 100 is in the shape of an interdigital electrode, and the second region 200 is a portion of the surface of the silicon wafer except for the first region 100;
as shown in fig. 3, the first mask of the first region 100 is removed, so that the anode region 300 and the cathode region 400 are exposed on the surface of the silicon wafer 10.
The first mask includes pi tape (kapton tape) or polyethylene terephthalate (PCT paper), wherein the kapton tape is formed by coating a polyimide film as a base material with high-temperature-resistant glue and has superior high-temperature resistance and high adhesion.
It should be noted that, in order to make the second region significantly higher than the anode region and the cathode region, a first mask multi-layer covering the surface of the silicon wafer may be adopted.
Optionally, the first mask on the surface of the silicon wafer is processed into the shape of an interdigital electrode by adopting an ultraviolet laser cold processing technology, the marking speed of an ultraviolet laser marking machine is 100-500 mm/s, and the marking times are 10-70. The finger width of the first area in the shape of the interdigital electrode is 0.5-3 mm, the finger length is 5-10 mm, the inter-finger distance is 0.2-0.5 mm, and the number of fingers is 2-10.
(2) Forming gold current collectors
And forming a gold current collector in the positive electrode area and the negative electrode area on the surface of the silicon wafer, wherein the positive electrode area and the negative electrode area which form the gold current collector are sunken in the second area.
Because the gold simple substance is directly plated on the silicon wafer, the adhesion effect is poor, and the gold simple substance is easy to fall off from the surface of the silicon wafer. Firstly, a chromium simple substance is plated on a first area on the surface of a silicon wafer to form a chromium layer, and then a gold simple substance is plated on the surface of the chromium layer to form a gold current collector, so that the gold simple substance can be stably attached to the silicon wafer, and the gold simple substance is effectively prevented from falling off.
Optionally, a magnetron sputtering method is adopted, a chromium target is firstly used for sputtering the surface of the silicon wafer for 2-4 minutes to form a chromium layer, and then a gold target is used for sputtering for 4-6 minutes to form a gold current collector.
(3) Forming a positive electrode and a negative electrode
Covering the second masks on the anode area and the cathode area of the silicon wafer respectively, obtaining the mass ratio of the anode material and the cathode material through calculation, spraying the electrode material corresponding to the electrode area which is not covered with the second masks, enabling the silicon wafer to form an anode and a cathode respectively, and removing all the second masks.
The anode material and the cathode material of the asymmetric high-voltage chip type energy storage device are different, and the cathode material and the anode material can be selected according to actual conditions in the preparation process of the asymmetric high-voltage chip type energy storage device.
Optionally, the electrode material of the negative electrode region includes MXene, and the electrode material of the positive electrode region includes activated carbon, lithium nickel cobalt manganese oxide, or lithium manganese oxide.
The order of forming the positive electrode by spraying the positive electrode region and forming the negative electrode by spraying the negative electrode region was random. The second mask can be covered on the anode region of the silicon wafer firstly, then the cathode material is sprayed on the cathode region which is not covered with the second mask to form a cathode, then the second mask is covered on the cathode region of the silicon wafer, and then the anode material is sprayed on the anode region which is not covered with the second mask to form an anode; or the second mask is firstly covered on the cathode region of the silicon chip, then the anode material is sprayed on the anode region which is not covered with the second mask to form an anode, then the second mask is covered on the anode region of the silicon chip, and then the cathode material is sprayed on the cathode region which is not covered with the second mask to form a cathode.
Generally, the mass ratio of the positive electrode material and the negative electrode material is calculated, the thickness ratio of the positive electrode material to the negative electrode material to be sprayed in the positive electrode area and the negative electrode area is determined according to the mass ratio, and finally the total amount of the positive electrode material and the negative electrode material to be sprayed is controlled according to the concentration of the solution of the positive electrode material, so that the thickness ratio of the positive electrode material to the negative electrode material is controlled.
The spraying pressure is 0.1-0.2 MPa.
When the anode and cathode materials are respectively sprayed, the uniformity of spraying needs to be ensured, a stable spraying air pressure and the advancing speed of a spray gun are kept, and the anode and the cathode obtained by spraying are ensured to be uniform and flat.
The second mask comprises kapton tape or PCT paper.
Optionally, the first mask on the surface of the silicon wafer is processed into the shape of an interdigital electrode by adopting an ultraviolet laser cold processing technology, the marking speed of an ultraviolet laser marking machine is 300-500 mm/s, and the marking times are 10-30.
The second mask directly contacts the gold current collector, so that part of the gold simple substance may be adhered away, and the performance of the manufactured asymmetric high-voltage chip type energy storage device is deteriorated. In order to prevent the second mask from directly contacting the surface of the gold current collector, when the second mask is respectively covered on the anode region and the cathode region of the silicon wafer, the second mask is only contacted with the first mask.
As shown in fig. 4 and 5, in order to match the shapes of the positive electrode region and the negative electrode region, the second mask 500 is processed in the shape of an interdigital electrode, the finger width of the second mask 500 is greater than that of the first region, the finger length of the second mask 500 is greater than that of the first region, the number of fingers of the second mask 500 is equal to that of the first region, the second mask 500 is made to cover the positive electrode region 300 or the negative electrode region 400 through the first mask on the second region 200 between the positive electrode region 300 and the negative electrode region 400, and since the positive electrode region 300 and the negative electrode region 400 where gold is formed are recessed in the second region 200, the second mask 500 is located on the upper side of the positive electrode region 300 or the negative electrode region 400 where gold is formed without directly contacting the gold collector.
For example, the width of the first region is 2 mm, the length of the first region is 8 mm, the distance between the fingers is 0.5 mm, and the number of fingers is 6, that is, the width of the positive electrode region or the negative electrode region is 2 mm, the length of the first region is 8 mm, and the number of fingers is 3. The second mask had a finger width of 3mm, a finger length of 8.5 mm, and a number of 3 fingers between fingers. The second mask covers the positive electrode area or the negative electrode area through only directly contacting the first mask, and is suspended above the positive electrode area or the negative electrode area on which the gold current collector is formed.
(4) Casting of electrolytes
And removing the first mask of the second area, and pouring an electrolyte material on the surface of the silicon wafer by using a gel electrolyte pouring technology.
Alternatively, the electrolyte material comprises a polyvinyl alcohol (PVA)/sodium sulfate gel, a polyvinyl alcohol (PVA)/sulfuric acid gel, or a lithium bis (trifluoromethylsulfonate) imide-1, 3-dioxolane/glyme (LiTFSI-DOL/DME) gel.
The thickness of the gel electrolyte layer after casting is 1-3 mm.
(5) Packaging device
As shown in fig. 6, the asymmetric high-voltage chip-type energy storage device is manufactured by encapsulating the device with Polydimethylsiloxane (PDMS) by using a mold molding method.
Wherein, the mould for packaging is formed by processing the acrylic plate by adopting a laser cutting technology.
The application also provides an asymmetric high-voltage chip type energy storage device which is prepared according to the preparation method of the asymmetric high-voltage chip type energy storage device.
The anode material and the cathode material of the asymmetric high-voltage chip type energy storage device are different, so that the capacitance of the asymmetric high-voltage chip type energy storage device can be improved by selecting different anode materials and different cathode materials.
The application also provides application of the asymmetric high-voltage chip type energy storage device. According to the selection of the anode material and the cathode material, a micro super capacitor or a lithium ion capacitor can be manufactured, and the micro super capacitor or the lithium ion capacitor can be widely applied to sensors, the Internet of things and integrated circuits.
The following describes an asymmetric high-voltage chip-type energy storage device and a method for manufacturing the same in detail with reference to the following embodiments.
Example 1
The embodiment of the application provides an asymmetric high-voltage chip type energy storage device and a preparation method thereof, and the preparation method comprises the following steps:
(1) forming interdigital electrode shape on silicon wafer
Covering three layers of kapton adhesive tapes on the surface of the silicon wafer, processing the kapton adhesive tapes on the surface of the silicon wafer by adopting an ultraviolet laser cold processing technology to form a first area and a second area, wherein the first area is in an interdigital electrode shape, the finger width of the first area is 1 mm, the finger length is 5 mm, the inter-finger distance is 0.2 mm, and the number of fingers is 6. And removing the kapton adhesive tape in the first area to expose the positive electrode area and the negative electrode area on the surface of the silicon chip.
(2) Forming gold current collectors
And sputtering a chromium target on the positive electrode area and the negative electrode area of the surface of the silicon wafer for 3 minutes to form chromium layers by adopting a magnetron sputtering method, sputtering a gold target for 5 minutes to form a gold current collector, and forming the positive electrode area and the negative electrode area of the gold current collector to be sunken in the second area.
(3) Forming a positive electrode and a negative electrode
And processing the PCT paper into an interdigital electrode shape by adopting an ultraviolet laser cold processing technology, wherein the finger width of the PCT paper is 1.4 mm, the finger length is 5.2 mm, and the number of the fingers is 3. The mass ratio of the positive electrode material to the negative electrode material is obtained through calculation, firstly, PCT paper covers the positive electrode area of a silicon wafer, then, Mxene solution is sprayed on the negative electrode area which is not covered with the PCT paper to form a negative electrode, then, the PCT paper covers the negative electrode area of the silicon wafer, then, activated carbon solution is sprayed on the positive electrode area which is not covered with the PCT paper to form a positive electrode, and all the PCT paper is removed.
(4) Casting of electrolytes
And removing the kapton adhesive tape in the second area, and pouring an electrolyte material PVA/sodium sulfate gel on the surface of the silicon wafer by using a gel electrolyte pouring technology.
(5) Packaging device
The chip type super capacitor is manufactured by encapsulating the device with PDMS by adopting a mold molding method, and the manufactured chip type super capacitor is shown in FIG. 7.
Example 2
The embodiment of the application provides an asymmetric high-voltage chip type energy storage device and a preparation method thereof, and the preparation method comprises the following steps:
(1) forming interdigital electrode shape on silicon wafer
Covering four layers of kapton adhesive tapes on the surface of the silicon wafer, processing the kapton adhesive tapes on the surface of the silicon wafer by adopting an ultraviolet laser cold processing technology to form a first area and a second area, wherein the first area is in an interdigital electrode shape, the finger width of the first area is 2.5 mm, the finger length is 8 mm, the inter-finger distance is 0.5 mm, and the number of the fingers is 8. And removing the kapton adhesive tape in the first area to expose the positive electrode area and the negative electrode area on the surface of the silicon chip.
(2) Forming gold current collectors
And sputtering a chromium target on the positive electrode area and the negative electrode area of the surface of the silicon wafer for 2 minutes to form chromium layers by adopting a magnetron sputtering method, sputtering a gold target for 4 minutes to form a gold current collector, and forming the positive electrode area and the negative electrode area of the gold current collector to be sunken in the second area.
(3) Forming a positive electrode and a negative electrode
And processing the PCT paper into an interdigital electrode shape by adopting an ultraviolet laser cold processing technology, wherein the width of the PCT paper is 3.5 mm, the length of each finger is 8.5 mm, and the number of the fingers is 4. The mass ratio of the positive electrode material to the negative electrode material is obtained through calculation, firstly, PCT paper is covered on a negative electrode area of a silicon wafer, then, a nickel cobalt lithium manganate solution is sprayed on a positive electrode area which is not covered with the PCT paper to form a positive electrode, then, the PCT paper is covered on the positive electrode area of the silicon wafer, and then, an Mxene solution is sprayed on the negative electrode area which is not covered with the PCT paper to form a negative electrode.
(4) Casting of electrolytes
And removing the kapton adhesive tape in the second area, and pouring an electrolyte material PVA/sulfuric acid gel on the surface of the silicon wafer by using a gel electrolyte pouring technology.
(5) Packaging device
And (3) adopting a mould molding method to package the device with PDMS to obtain the chip type lithium ion capacitor.
Comparative example 1
The application provides an asymmetric high-voltage chip type energy storage device and a preparation method thereof, and the preparation method comprises the following steps:
(1) forming interdigital electrode shape on silicon wafer
Covering three layers of kapton adhesive tapes on the surface of the silicon wafer, processing the kapton adhesive tapes on the surface of the silicon wafer by adopting an ultraviolet laser cold processing technology to form a first area and a second area, wherein the first area is in an interdigital electrode shape, the finger width of the first area is 1 mm, the finger length is 5 mm, the inter-finger distance is 0.2 mm, and the number of fingers is 6. And removing the kapton adhesive tape in the first area to expose the positive electrode area and the negative electrode area on the surface of the silicon chip.
(2) Forming gold current collectors
And sputtering a chromium target on the positive electrode area and the negative electrode area of the surface of the silicon wafer for 3 minutes to form chromium layers by adopting a magnetron sputtering method, sputtering a gold target for 5 minutes to form a gold current collector, and forming the positive electrode area and the negative electrode area of the gold current collector to be sunken in the second area.
(3) Forming a positive electrode and a negative electrode
And spraying the Mxene solution on the positive electrode area and the negative electrode area to form a positive electrode and a negative electrode.
(4) Casting of electrolytes
And removing the kapton adhesive tape in the second area, and pouring an electrolyte material PVA/sodium sulfate gel on the surface of the silicon wafer by using a gel electrolyte pouring technology.
(5) Packaging device
And (3) adopting a mould molding method to prepare the chip type super capacitor by using the PDMS package device.
Test example 1
The chip-type super capacitors prepared in example 1 of the present application were connected in series, and as shown in fig. 8, the lamp was on.
Test example 2
Cyclic voltammetry tests were performed on the chip-type supercapacitors prepared in example 1 and comparative example 1, respectively, using an electrochemical workstation to obtain cyclic voltammetry curves, and then comparison graphs of the cyclic voltammetry curves of the two chip-type supercapacitors were obtained, as shown in fig. 9, in which the scan rate was 10 mv per second.
As can be seen from fig. 9, the capacity of the asymmetric-structure MXene-based chip micro supercapacitor prepared in example 1 is 3 times that of the symmetric-structure MXene-based chip micro supercapacitor prepared in comparative example 1. The voltage window of the MXene-based chip micro-supercapacitor prepared in example 1 with the asymmetric structure is as high as 1.6V, while the working voltage window of the MXene-based chip micro supercapacitor prepared in comparative example 1 with the symmetric structure is only 1.2V.
In summary, the preparation method of the asymmetric high-voltage chip-type energy storage device can select different electrode materials to form the anode and the cathode according to actual requirements according to actual conditions, and then the asymmetric high-voltage chip-type energy storage device with a symmetric structure and an asymmetric structure is prepared according to the mass ratio of the calculated and matched anode and cathode. The asymmetric high-voltage chip type energy storage device with the asymmetric structure has larger capacitance and higher voltage window. The asymmetric high-voltage chip type energy storage device can be widely applied to sensors, Internet of things and integrated circuits.
The foregoing is illustrative of the present application and is not to be construed as limiting thereof, as numerous modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A preparation method of an asymmetric high-voltage chip type energy storage device is characterized by comprising the following steps:
covering the surface of a silicon wafer with a first mask, processing the first mask on the surface of the silicon wafer to form a first area and a second area, wherein the first area forms an interdigital electrode shape, removing the first mask of the first area to expose an anode area and a cathode area on the surface of the silicon wafer, and forming gold current collectors in the anode area and the cathode area on the surface of the silicon wafer;
covering the anode region and the cathode region of the silicon wafer by adopting a second mask respectively, spraying electrode materials corresponding to the electrode regions which are not covered by the second mask, wherein the electrode materials sprayed on the anode region and the cathode region are different, so that the silicon wafer forms an anode and a cathode respectively;
removing the first mask of the second area, pouring an electrolyte material on the surface of the silicon wafer, and packaging to obtain the asymmetric high-voltage chip type energy storage device;
form the gold is collected the body the anodal region with the negative pole is regional all sunken in the second is regional, adopts the second mask cover respectively in the silicon chip the anodal region with during the negative pole is regional, the second mask is located the upside of the gold is collected the body and not direct with the contact of the gold is collected the body.
2. The method for manufacturing an asymmetric high-voltage chip-type energy storage device according to claim 1, wherein the finger width of the first region in the shape of the interdigital electrode is 0.5-3 mm, the finger length is 5-10 mm, the inter-finger distance is 0.2-0.5 mm, and the number of fingers is 2-10.
3. The method for manufacturing an asymmetric high-voltage chip-type energy storage device according to claim 1, wherein the first mask comprises pi tape or polyethylene terephthalate paper.
4. The method for manufacturing an asymmetric high-voltage chip-type energy storage device according to claim 3, wherein the second mask comprises pi tape or polyethylene terephthalate paper.
5. The method for manufacturing an asymmetric high-voltage chip-type energy storage device according to claim 1, wherein when the gold current collector is formed in the first region of the surface of the silicon wafer, a simple substance of chromium is first plated on the first region of the surface of the silicon wafer to form a chromium layer, and then a simple substance of gold is plated on the surface of the chromium layer to form the gold current collector.
6. The method for preparing an asymmetric high-voltage chip-type energy storage device according to any one of claims 1 to 5, wherein the electrode material of the negative electrode region comprises MXene, and the electrode material of the positive electrode region comprises activated carbon, lithium nickel cobalt manganese oxide or lithium manganese oxide.
7. The method for preparing an asymmetric high-voltage chip-type energy storage device according to any one of claims 1 to 5, wherein the electrolyte material comprises polyvinyl alcohol/sodium sulfate gel, polyvinyl alcohol/sulfuric acid gel or lithium bis (trifluoromethylsulfonic acid) imide-1, 3-dioxolane/glyme gel.
8. The method for preparing the asymmetric high-voltage chip-type energy storage device according to any one of claims 1 to 5, wherein the packaging comprises packaging with polydimethylsiloxane by adopting a die forming method to prepare the asymmetric high-voltage chip-type energy storage device.
9. An asymmetric high-voltage chip-type energy storage device, which is prepared according to the preparation method of the asymmetric high-voltage chip-type energy storage device of any one of claims 1 to 8.
10. Use of the asymmetric high voltage chip-based energy storage device of claim 9 in sensors, internet of things and integrated circuits.
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Citations (1)

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CN104377345A (en) * 2013-08-15 2015-02-25 纳米新能源（唐山）有限责任公司 Miniature energy storage device electrode and miniature energy storage device, and formation methods thereof

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