CN111465223A - Processing method for solving pad dropping problem in multi-layer thick circuit board packaging process - Google Patents
Processing method for solving pad dropping problem in multi-layer thick circuit board packaging process Download PDFInfo
- Publication number
- CN111465223A CN111465223A CN202010445880.9A CN202010445880A CN111465223A CN 111465223 A CN111465223 A CN 111465223A CN 202010445880 A CN202010445880 A CN 202010445880A CN 111465223 A CN111465223 A CN 111465223A
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- Prior art keywords
- hole
- height
- resin
- copper
- circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a processing method for solving pad dropping in the packaging process of a multilayer thick circuit board, wherein the multilayer thick circuit board is provided with an all-copper through hole and a back drilling hole arranged at the all-copper through hole, and the processing method comprises the following steps: and filling the back drill hole with resin, and back drilling air holes at the back drill hole after the resin is cured. According to the invention, the difference value of the expansion volumes of the resin of the all-copper via hole and the back-drilled hole is compensated by drilling the air hole in the resin, so that the expansion volumes of the back-drilled hole and the all-copper via hole are consistent, and the problem of PAD drop of the circuit board in the cooling process after welding and packaging is further solved.
Description
Technical Field
The invention relates to a processing method for solving the problem of pad dropping in the packaging process of a multilayer thick circuit board, and belongs to the technical field of printed circuit boards.
Background
The communication design is in signal transmission's consideration, need reduce the insertion loss of hole, and the BGA area is many to reduce the crosstalk of pore wall to the signal through the design back drilling, but along with the increase of thick and the number of piles, CTE expansion difference appears in the welding process in the back drilling region and to the through-hole region, and the expansion volume in full copper hole is less than the back drilling region to PAD phenomenon can appear falling when the circuit board in the cooling process after accomplishing the welding. The current methods for solving the problem mainly comprise: changing a design scheme and increasing the size of the bonding pad; and repairing and ball-planting the bad chip caused by welding. The existing method wastes cost, and the array density is reduced due to the increase of the size of the bonding pad.
Disclosure of Invention
The purpose is as follows: in order to overcome the defects in the prior art, the invention provides a processing method for solving the problem of PAD dropping in the process of packaging a multilayer thick circuit board, so that the PAD dropping phenomenon is avoided, and meanwhile, the cost is saved.
The technical scheme is as follows: in order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a processing method for solving the problem of pad dropping in the packaging process of a multilayer thick circuit board is provided, the multilayer thick circuit board is provided with an all-copper through hole and a back drilling hole arranged at the all-copper through hole, the processing method comprises the following steps,
and filling the back drilling hole with resin, and back drilling air holes at the resin position after the resin is cured.
Further, there is a height difference between the air hole and the back drilled hole, which is a thermal expansion compensation height.
Further, the pore diameter of the air hole is smaller than that of the back drilling hole.
Further, the thermal expansion compensation height = back drilled hole height-air hole height.
Further, the air hole height = { [ (volume of expansion of copper remaining via hole + volume of expansion of CTE before and after vitrification of resin) — volume of expansion of all copper of via hole ]/volume of expansion of CTE before and after vitrification of resin } × back-drilled hole height.
Further, the volume of CTE expansion before and after vitrification of the resin = [ (peak packaging process temperature-room temperature) × (coefficient of thermal expansion value of resin before vitrification + coefficient of thermal expansion value of resin after vitrification)]Back-drilled hole height/106；
Expansion volume of the via hole residual copper = [ (encapsulation process temperature peak value-indoor temperature) × copper extensibility]Back drilling residual height/106；
The expansion volume of the via hole total copper = [ (encapsulation process temperature peak value-indoor temperature) × copper extensibility]Height/10 of via6。
Further, the peak temperature value of the packaging process and the indoor temperature are obtained through thermometer measurement, the height of the back drilling hole, the residual height of the back drilling hole and the height of the through hole are designed values, and the coefficient of thermal expansion value of the resin before vitrification, the coefficient of thermal expansion value of the resin after vitrification and the elongation of copper are obtained through measuring material coefficients.
Has the advantages that: according to the invention, the difference value of the expansion volumes of the resin of the all-copper via hole and the back-drilled hole is compensated by drilling the air hole in the resin, so that the expansion volumes of the back-drilled hole and the all-copper via hole are consistent, and the problem of PAD drop of the circuit board in the cooling process after welding and packaging is further solved.
Drawings
FIG. 1 is a schematic diagram of an all copper via, back-drilled hole, and air hole of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The utility model provides a solve multilayer thick circuit board packaging in-process and fall processing method of pad, be equipped with full copper conducting hole 1 on the multilayer thick circuit board to and the back drilling 2 that sets up in full copper conducting hole 1 department, include the following process: the back drilled holes 2 are filled with resin, and after the resin is cured, air holes 3 are back drilled at the resin.
The pore diameter of the air hole 3 is smaller than that of the back drilling hole 2.
There is a height difference between the air holes 3 and the back drilled holes 2, which is a thermal expansion compensation height Δ H.
The thermal expansion compensation height Δ H = back-drilled hole height H2-height of air holes H3；
The height H of the air hole3= { [ (expansion volume of remaining copper + CTE expansion volume before and after vitrification of resin) { [ (expansion volume of via hole) } expansion volume of via hole all copper { ]]CTE expansion volume before and after vitrification of the resin } Back-drilled hole height H2。
Expansion volume of the resin = [ (packaging process temperature peak value-indoor temperature) × (thermal expansion coefficient value of resin before vitrification + thermal expansion coefficient value of resin after vitrification)]Height H of back drilled hole2/106；
Expansion volume of the via hole residual copper = [ (packaging process temperature peak-Room temperature) copper elongation]Back drilling residual height H4/106；
The expansion volume of the via hole total copper = [ (encapsulation process temperature peak value-indoor temperature) × copper extensibility]Height H of via1/106。
The peak temperature value and the indoor temperature in the packaging process are obtained through measurement of a thermometer, the height of the back drilling hole, the residual height of the back drilling hole and the height of the through hole are designed values, and the coefficient of thermal expansion of the resin before vitrification, the coefficient of thermal expansion of the resin after vitrification and the elongation of copper are obtained through measurement of material coefficients.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (7)
1. The utility model provides a solve multilayer thick circuit board packaging in-process and fall processing method of pad, be equipped with the full copper via hole on the thick circuit board of multilayer to and the back drilling hole that sets up in full copper via hole department, its characterized in that: comprises the following steps of,
and filling the back drilling hole with resin, and back drilling air holes at the resin position after the resin is cured.
2. The method as claimed in claim 1, wherein the method comprises the steps of: and a height difference exists between the air hole and the back drilling hole, and the height difference is thermal expansion compensation height.
3. The processing method for solving the problem of pad dropping in the packaging process of the multilayer thick circuit board according to claim 1, characterized in that: the pore diameter of the air hole is smaller than that of the back drilling hole.
4. The processing method for solving the problem of pad dropping in the packaging process of the multilayer thick circuit board according to claim 2, characterized in that: the thermal expansion compensation height = back drilled hole height-air hole height.
5. The processing method for solving the problem of pad dropping in the packaging process of the multilayer thick circuit board according to claim 4, characterized in that: the air hole height = { [ (volume of expansion of copper remaining via + volume of CTE expansion before and after vitrification of resin) — volume of expansion of all copper of via ]/volume of CTE expansion before and after vitrification of resin } × back drilled hole height.
6. The processing method for solving the problem of pad dropping in the packaging process of the multilayer thick circuit board according to claim 5, characterized in that: volume of CTE expansion before and after vitrification of the resin = [ (packaging process temperature peak-room temperature) × (coefficient of thermal expansion value of resin before vitrification + coefficient of thermal expansion value of resin after vitrification)]Back-drilled hole height/106；
Expansion volume of the via hole residual copper = [ (encapsulation process temperature peak value-indoor temperature) × copper extensibility]Back drilling residual height/106；
The expansion volume of the via hole total copper = [ (encapsulation process temperature peak value-indoor temperature) × copper extensibility]Height/10 of via6。
7. The processing method for solving the problem of pad dropping in the packaging process of the multilayer thick circuit board according to claim 6, characterized in that: the peak temperature value and the indoor temperature in the packaging process are obtained through measurement of a thermometer, the height of the back drilling hole, the residual height of the back drilling hole and the height of the through hole are designed values, and the coefficient of thermal expansion of the resin before vitrification, the coefficient of thermal expansion of the resin after vitrification and the elongation of copper are obtained through measurement of material coefficients.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010445880.9A CN111465223B (en) | 2020-05-25 | 2020-05-25 | Processing method for solving pad dropping problem in multi-layer thick circuit board packaging process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010445880.9A CN111465223B (en) | 2020-05-25 | 2020-05-25 | Processing method for solving pad dropping problem in multi-layer thick circuit board packaging process |
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| CN111465223A true CN111465223A (en) | 2020-07-28 |
| CN111465223B CN111465223B (en) | 2023-01-24 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204217212U (en) * | 2014-11-28 | 2015-03-18 | 杭州华三通信技术有限公司 | PCB board structure |
| CN108347821A (en) * | 2017-12-29 | 2018-07-31 | 加弘科技咨询(上海)有限公司 | High-speed line for BGA is fanned out to the printed circuit board of method and application this method |
| CN110868803A (en) * | 2018-08-28 | 2020-03-06 | 深南电路股份有限公司 | Machining method and system of micro-hole back drill and printed circuit board |
| CN111148355A (en) * | 2019-12-31 | 2020-05-12 | 生益电子股份有限公司 | Method for improving bonding force between copper layer and resin in back drilling area and PCB |
-
2020
- 2020-05-25 CN CN202010445880.9A patent/CN111465223B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204217212U (en) * | 2014-11-28 | 2015-03-18 | 杭州华三通信技术有限公司 | PCB board structure |
| CN108347821A (en) * | 2017-12-29 | 2018-07-31 | 加弘科技咨询(上海)有限公司 | High-speed line for BGA is fanned out to the printed circuit board of method and application this method |
| CN110868803A (en) * | 2018-08-28 | 2020-03-06 | 深南电路股份有限公司 | Machining method and system of micro-hole back drill and printed circuit board |
| CN111148355A (en) * | 2019-12-31 | 2020-05-12 | 生益电子股份有限公司 | Method for improving bonding force between copper layer and resin in back drilling area and PCB |
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|---|---|
| CN111465223B (en) | 2023-01-24 |
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