CN111464056A

CN111464056A - Power conversion device and power conversion method

Info

Publication number: CN111464056A
Application number: CN201911205562.9A
Authority: CN
Inventors: 渡边智史; 葛岛光则; 东川康儿; 高濑善康; 森本进也
Original assignee: Yaskawa Electric Corp
Current assignee: Yaskawa Electric Corp
Priority date: 2019-01-18
Filing date: 2019-11-29
Publication date: 2020-07-28
Also published as: JP2020115729A; JP6841288B2

Abstract

A power conversion device (1) is provided with a power conversion circuit (10) that converts power of a DC bus (12) into multi-phase AC power and supplies the multi-phase AC power to a load, a test control unit (115) that controls the power conversion circuit (10) so as to temporarily maintain a state in which at least 1 phase of the multi-phase and the remaining phase are connected to different poles of the DC bus (12) during a period in which the voltage of the DC bus (12) increases as the DC bus (12) is connected to a DC Power Supply (PS), and a phase failure detection unit (116) that detects a phase failure based on the output current to the load (L D) in the above-described state.

Description

Power conversion device and power conversion method

Technical Field

The present disclosure relates to a power conversion device and a power conversion method.

Background

Patent document 1 discloses a motor control device including: an energization unit that energizes each coil of the motor based on a d-axis current value and a q-axis current value used when detecting an abnormality in the motor coil and an electrical angle of the motor; and a phase failure determination unit that determines whether or not an abnormality has occurred in a certain coil based on the current flowing through each coil when the energization unit energizes the motor.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open No. 2014-121144.

Disclosure of Invention

Problems to be solved by the invention

The present disclosure provides a power conversion apparatus and a power conversion method effective for early detection of a phase failure.

Means for solving the problems

One aspect of the present disclosure relates to a power conversion apparatus including: a power conversion circuit that converts power of the dc bus into multi-phase ac power and supplies the multi-phase ac power to a load; a test control unit that controls the power conversion circuit so as to temporarily maintain a state in which at least 1 phase and the remaining phases of the plurality of phases are connected to different poles of the dc bus during a period in which the voltage of the dc bus rises as the dc bus is connected to the dc power supply; and a phase failure detection unit for detecting a phase failure based on the output current to the load in the above state

Other aspects of the present disclosure relate to a power conversion method, including: controlling a power conversion circuit that converts power of a dc bus into multi-phase ac power and supplies the power to a load, while temporarily maintaining a state in which at least 1 phase of a plurality of phases and a remaining phase are connected to different poles of the dc bus while a voltage of the dc bus rises as the dc bus of the power conversion circuit is connected to a dc power supply; and a phase loss detected based on the output current to the load in the above state.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present disclosure, a power conversion device and a power conversion method effective for early detection of a phase failure can be provided.

Drawings

Fig. 1 is a schematic diagram illustrating a schematic structure of a power conversion apparatus;

fig. 2 is a block diagram illustrating a hardware configuration of the control circuit;

FIG. 3 is a flowchart illustrating power conversion steps; .

Fig. 4 is a flowchart illustrating a phase loss checking step.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the drawings. In the description, the same elements or elements having the same function are denoted by the same reference numerals, and redundant description thereof is omitted.

(Power conversion device)

The power conversion device 1 shown in fig. 1 is a device that performs power conversion between a dc power supply PS and a load L D, the power conversion refers to conversion of a power form, and the power form may include the number of lines, dc or ac, voltage (voltage amplitude), current (current amplitude), frequency, and the like.

Load L D is, for example, a rotary electric motor (for example, a motor for a vehicle), specific examples of the motor for a vehicle include motors for an electric vehicle and a plug-in hybrid vehicle, and when load L D is a motor for a vehicle, power converter 1 is mounted on the vehicle together with load L D.

The dc power supply PS supplies dc power of a predetermined voltage to the power conversion device 1. The predetermined voltage is, for example, 100 to 700V, or 200 to 600V, or 300 to 500V.

The power conversion device 1 includes a power conversion circuit 10 and a control circuit 100 that controls the power conversion circuit 10, the power conversion circuit 10 is a so-called inverter circuit that converts power of a dc bus into multi-phase (e.g., 3-phase) ac power and supplies the power to a load L d, for example, the power conversion circuit 10 has a dc bus 12, a capacitor 16, an output line 13, a switching circuit 11,

input terminals

14P, 14N,

output terminals

15U, 15V, 15W,

current sensors

21U, 21V, 21W, and a voltage sensor 22.

The dc bus 12 is a bus for guiding dc power from the dc power supply PS. For example, the dc bus 12 includes a positive electrode line 12P and a negative electrode line 12N. Capacitor 16 is connected between

lines

12P and 12N, and smoothes the voltage of dc bus 12 (the voltage between

lines

12P and 12N). The dc power supply PS may be a multi-stage power supply capable of outputting dc power at a plurality of stages of voltage. In this case, the dc bus 12 may include 3 or more lines including a negative electrode line and a plurality of positive electrode lines corresponding to voltages of a plurality of stages.

The output line 13 is a bus for guiding ac power for output to the load L D, and the output line 13 includes

lines

13U, 13V, and 13W for guiding U-phase, V-phase, and W-phase of three-phase ac power, respectively, for example.

The switching circuit 11 performs power conversion between dc power of the dc bus 12 and ac power of the output line 13. For example, the switching circuit 11 includes a plurality of switching elements, and changes the connection state between the dc bus 12 and the output line 13 by switching on or off of each switching element. The switching element is, for example, a power MOSFET (Metal Oxide Semiconductor field effect Transistor), an IGBT (Insulated Gate bipolar Transistor), or the like, and is switched on and off in accordance with a pulse signal from the control circuit 100.

The

input terminals

14P and 14N are provided on, for example, a terminal block or the like, and are electrically connected to the

lines

12P and 12N of the dc bus bar 12, respectively. A cable of the dc power supply PS is connected to the

input terminals

14P and 14N via the power switch SW. The power switch SW is, for example, a high-voltage relay, and switches between an on state in which the dc power supply PS is connected to the dc bus 12 and an off state in which the dc power supply PS is disconnected from the dc bus 12 in accordance with an electric signal.

A rush current prevention circuit (rush current suppression circuit), not shown, may be provided between the

input terminals

14P and 14N and the

lines

12P and 12N of the dc bus 12. The inrush current prevention circuit is provided to limit the peak value of the charging current flowing through the

lines

12P and 12N when the dc power supply PS charges the capacitor 16, and protect the power switch SW. In the case where the peak value of the charging current is suppressed to the allowable level, the rush current prevention circuit may be omitted. For example, when the output impedance of the dc power supply PS is large, or when the dc power supply PS includes a control circuit for outputting a current, the inrush current prevention circuit may be omitted.

Output terminals

15U, 15V, and 15W are provided on a terminal block or the like, and are electrically connected to

lines

13U, 13V, and 13W, respectively, and cables of load L D are connected to

output terminals

15U, 15V, and 15W.

The

current sensors

21U, 21V, 21W detect currents of the

wires

13U, 13V, 13W, respectively. The voltage sensor 22 detects the voltage of the dc bus 12. When the dc power supply PS is at a multilevel level, the voltage sensor 22 detects a voltage between the negative line and any one of the plurality of positive lines as the voltage of the dc bus 12.

The control circuit 100 is configured to control the power conversion circuit 10 to temporarily maintain a state in which at least 1 phase and the remaining phases of the output line 13 are connected to different poles of the dc bus 12, respectively, during a period in which the voltage of the dc bus 12 rises as the power switch SW is turned on (i.e., the dc bus 12 is connected to the dc power supply PS) (hereinafter referred to as a "test state"), and to detect a phase failure based on an output current to the load L D in the test state, and for example, the control circuit 100 includes, as a functional configuration (hereinafter referred to as a "functional module"), a voltage information acquisition unit 111, a current information acquisition unit 112, a time measurement unit 113, a test control unit 115, and a phase failure detection unit 116.

The voltage information acquisition unit 111 acquires a detected value of the voltage of the dc bus 12 from the voltage sensor 22. The current information acquisition unit 112 acquires the detected value of the current of the output line 13 from the

current sensors

21U, 21V, and 21W. The time measuring unit 113 measures an elapsed time by counting clock pulses of a predetermined cycle or the like. The test control unit 115 controls the power conversion circuit 10 to temporarily maintain the test state described above while the voltage of the dc bus 12 rises as the dc bus 12 is connected to the dc power supply PS.

In the test state, at least 1 phase (at least one of the

lines

13U, 13V, and 13W) of at least the output line 13 and the remaining phases (remaining lines) may be connected to different poles of the dc bus 12, respectively, without any other limitation. For example, the line 13U may be connected to the line 12P, and the

lines

13V and 13W may be connected to the line 12N, the line 13V may be connected to the line 12P, and the

lines

13U and 13W may be connected to the line 12N, or the line 13W may be connected to the line 12P, and the

lines

13U and 13V may be connected to the line 12N. Further, the line 13U may be connected to the line 12N, and the

lines

13V and 13W may be connected to the line 12P, the line 13V may be connected to the line 12N, and the

lines

13U and 13W may be connected to the line 12P, or the line 13W may be connected to the line 12N, and the

lines

13U and 13V may be connected to the line 12P.

The open-phase detection unit 116 detects an open phase based on an output current to the load L D in a test state, the open phase is a state in which at least a part of a power supply path between the power conversion circuit 10 and the load L D is interrupted, the power supply path here includes a path in the power conversion circuit 10 and a path in the load L D, and specific examples of a cause of the open phase include a failure of a part of the switch circuit 11, disconnection of a cable, and disconnection of a winding in the load L D.

For example, the open-phase detection unit 116 detects the open phase based on whether or not there is a phase in which no current flows in the test state. In the absence of the above-mentioned phase loss, current flows in all phases in the test state. On the other hand, if a phase defect occurs in any one of the phases, a phase in which no current flows inevitably occurs. For example, in the test state, when the line 13U is connected to the line 12P and the

lines

13V and 13W are connected to the line 12N, if a phase defect occurs in the U phase, no current flows in any of the phases. If a phase defect occurs in the V phase, the same current flows in the U phase and the W phase (in different directions), but no current flows in the V phase. If a phase defect occurs in the W phase, the same current (different direction) flows in the U phase and the V phase, but no current flows in the W phase. In addition, if a phase loss occurs in 2 or more phases, no current flows in any of the phases. Therefore, the open-phase detection unit 116 checks whether or not a phase in which no current flows is present in the test state, detects that no open phase is present when a current flows in any of the phases, and detects that a phase in which no current flows is present.

The current information acquisition unit 112 can determine whether or not a current flows in each phase based on the detection values acquired from the

current sensors

21U, 21V, and 21W. For example, the open-phase detection unit 116 may determine that no current flows when the detection values of the

current sensors

21U, 21V, and 21W are smaller than a predetermined lower limit value. The lower limit value may be a small value that can be regarded as being as small as when no current flows. For example, the lower limit value is set to a value obtained by multiplying the resolution of the

current sensors

21U, 21V, 21W by a predetermined magnification.

The open-phase detection unit 116 may detect the open phase when a state in which a phase through which no current flows continues in a test state until a predetermined condition is satisfied. For example, the open-phase detection unit 116 may detect the open phase by setting, as the predetermined condition, a voltage of the dc bus 12 that has reached a predetermined voltage threshold (hereinafter, referred to as a "first condition") in a state where a phase in which no current flows exists. In other words, the open-phase detection unit 116 may detect the open phase when the voltage of the dc bus 12 reaches the voltage threshold in a state where a phase through which no current flows exists.

The open-phase detection unit 116 detects the open phase by using, as the predetermined condition, a predetermined determination time (hereinafter, referred to as a "second condition") that has elapsed in a state where a phase in which no current flows exists. In other words, the open-phase detection unit 116 can detect the open phase when a predetermined determination time has elapsed in a state where a phase in which no current flows exists.

The open-phase detection unit 116 detects the open phase by setting, as the predetermined condition, a current of another phase that has reached a predetermined current threshold (hereinafter referred to as a "third condition") in a state where a phase through which no current flows exists. In other words, the open-phase detection unit 116 can detect the open phase when the current of the other phase reaches a predetermined current threshold value in a state where the phase through which no current flows exists. The current threshold value may be set to a value that is smaller than the current value that can flow when the voltage of the dc bus 12 is 60 volts and is equal to or greater than the lower limit value.

The phase loss detection unit 116 may detect the phase loss when two or more of the first condition, the second condition, and the third condition are the predetermined conditions and any one of the two or more conditions is satisfied. For example, the open-phase detection unit 116 may detect the open phase when all of the first condition, the second condition, and the third condition are the predetermined conditions and any one of the first condition, the second condition, and the third condition is satisfied in a state where a phase through which no current flows exists.

The predetermined condition may be set such that the phase failure can be detected before the voltage of the dc bus 12 reaches 60 volts. For example, the voltage threshold may be set so that the open phase can be detected before the voltage of the dc bus 12 reaches 60 volts. For example, the voltage threshold may be set to less than 60 volts. The determination time may be set to a value shorter than the time from the rise of the voltage of the dc bus 12 to 60 volts.

The open-phase detection unit 116 may be configured to detect a open phase based on a current detection value of a detection target phase of any 2 phases out of the 3 phases. In this case, the test control unit 115 needs to connect the detection target phase of 2 phases and the other phase 1 to different poles of the dc bus 12 in a test state. With this configuration, the current sensor of the other phase can be omitted.

For example, when the open-phase detection unit 116 is configured to detect open phase based on the current detection values of the

current sensors

21U and 21W, the test control unit 115 needs to connect the

lines

13U and 13W to the line 12P and connect the line 13V to the line 12N, or connect the

lines

13U and 13W to the line 12N and connect the line 13V to the line 12P in a test state. For example, when no open phase occurs when the test control unit 115 connects the

lines

13U and 13W to the line 12P and connects the line 13V to the line 12N, current flows through both the

lines

13U and 13W. If a phase loss occurs in the U phase, a current flows through the line 13W, but no current flows through the line 13U. If a phase loss occurs in the V phase, no current flows through either of the

lines

13U and 13W. If a phase loss occurs in the W phase, a current flows through the line 13U, but no current flows through the line 13W. When a phase loss occurs in 2 or more phases, no current flows through either of the

lines

13U and 13W. As described above, when no open phase occurs, current flows through both

lines

13U and 13W, whereas when at least 1 open phase occurs, current does not flow through at least one of

lines

13U and 13W. Therefore, the above-described phase loss can be detected based on the current detection values of the

current sensors

21U, 21W.

The control circuit 100 may also perform detection of switching of the power switch SW from the off state to the on state, and may be configured to start processing for detecting the above-described phase loss in response to switching of the power switch SW from the off state to the on state. For example, the control circuit 100 further includes a power-on detection unit 114. The power-on detection unit 114 detects that the power switch SW is switched from the off state to the on state (that is, the dc bus 12 is connected to the dc power supply PS) based on the voltage rise of the dc bus 12. For example, power supply on detection unit 114 detects that dc bus 12 is connected to dc power supply PS based on the voltage detection value of voltage sensor 22 rising above a predetermined threshold (hereinafter referred to as an "on detection threshold").

The method of detecting that the power switch SW is in the on state is not limited to the method based on the voltage rise. For example, the power-on detection unit 114 may detect that the power switch SW is switched from the off state to the on state based on an electrical signal for switching the power switch SW from the off state to the on state. The test control unit 115 and the open-phase detection unit 116 start processing for detecting the open phase in accordance with the detection by the power-on detection unit 114 that the power switch SW has been switched from the off state to the on state. For example, the test control unit 115 controls the power conversion circuit 10 so that the test state is started at a timing when the power-on detection unit 114 detects that the power switch SW is switched from the off state to the on state, and the open-phase detection unit 116 starts processing for detecting the open phase in accordance with the start of the test state.

The control circuit 100 may be configured to start the processing for detecting the phase failure before the timing based on the information of the timing at which the power switch SW is switched from the off state to the on state. This timing information can be acquired from a higher-level controller or the like, for example.

The control circuit 100 may be configured to further perform control of the power conversion circuit 10 to convert the dc power supply PS into ac power and supply the ac power to the load L D when no phase loss is detected, and to prohibit power supply from the power conversion circuit 10 to the load L D when a phase loss is detected, and the control circuit 100 may be configured to notify the user of this information when a phase loss of the power conversion circuit 10 and the load L D is detected, for example, the control circuit 100 may further include a drive control unit 119, an output prohibition unit 117, and a phase loss notification unit 118.

When the open-phase detection unit 116 does not detect the open phase (that is, when the open phase is not detected), the drive control unit 119 controls the power conversion circuit 10 to supply the load L D with drive power corresponding to a command from a higher-level controller, for example, the drive control unit 119 controls the power conversion circuit 10 to convert the power of the dc power supply PS into drive power and supply the drive power to the load L D.

The output prohibition unit 117 prohibits the supply of power from the power conversion circuit 10 to the load L D when the open-phase detection unit 116 detects the open phase, for example, the output prohibition unit 117 controls the power conversion circuit 10 to keep the

lines

13U, 13V, 13W in a state where none of the

lines

12P, 12N are connected, and the open-phase notification unit 118 notifies the user of the information through a display device such as a liquid crystal monitor or a warning lamp when the open-phase detection unit 116 detects the open phase.

Fig. 2 is a block diagram illustrating a hardware configuration of the control circuit 100, as shown in fig. 2, the control circuit 100 includes a circuit 120, the circuit 120 includes one or more processors 121, a memory 122, a memory 123, a display device 124, an input/output port 125, and a timer 126, the memory 123 includes a computer-readable storage medium such as a nonvolatile semiconductor memory, and the like, the memory 123 stores a program that causes the control circuit 100 to execute controlling the power conversion circuit 10 to temporarily maintain a state in which at least 1 phase and the remaining phases of the output line 13 are connected to mutually different poles of the dc bus 12 (hereinafter referred to as a "test state") while the voltage of the dc bus 12 rises with the power switch SW being turned on (i.e., the dc bus 12 is connected to the dc power supply PS), and detecting a phase failure based on an output current to the load L D in the test state, for example, the memory 123 stores a program loaded from the storage medium of the memory 123 and an operation result of the processor 122, and a clock execution instruction to perform a clock pulse counting between the processor 121, the power supply voltage, the power supply, the monitor, the power supply, the monitor, and the power supply, and the monitor 21.

The control circuit 100 is not necessarily limited to a circuit in which each function is configured by a program. For example, the control circuit 100 may constitute at least a part of the functions by an Application Specific Integrated Circuit (ASIC) or an ASIC integrated with an ASIC.

[ Power conversion method ]

Next, as an example of the power conversion method, a step (hereinafter, referred to as "start-up step") until control corresponding to a command or the like from an upper controller is started in a power conversion step performed by the power conversion device 1 is illustrated, the start-up step includes controlling the power conversion circuit 10 to temporarily maintain the test state described above while the voltage rises along with the connection of the dc bus 12 to the dc bus 12 of the dc power supply, and detecting a phase failure based on the output current to the load L D in the test state.

For example, as shown in fig. 3, the control circuit 100 executes steps S01, S02. In step S01, voltage information acquisition unit 111 acquires a detected value of the voltage of dc bus 12 from voltage sensor 22. In step S02, the power supply on detection unit 114 checks whether or not the voltage detection value of the voltage sensor 22 exceeds the on detection threshold. If it is determined in step S02 that the detected value of the voltage does not exceed the on detection threshold, the control circuit 100 returns the process to step S01. Thereafter, the control circuit 100 repeats acquisition and confirmation of the voltage detection value of the dc bus 12.

If it is determined in step S02 that the detected value of the voltage exceeds the on detection threshold, the control circuit 100 executes steps S03 and S04. Step S03 includes checking for phase loss. Details of step S03 will be described in further detail. In step S04, the drive control unit 119 checks whether or not it is determined in step S03 that there is no phase loss.

If it is determined in step S04 that there is no phase loss, the control circuit 100 executes step S05. in step S05, the drive control unit 119 starts control for supplying drive power corresponding to an instruction from an upper controller to the load L D (hereinafter, referred to as "drive control").

If it is determined at step S04 that there is a phase loss, that is, if the phase loss detection unit 116 detects the phase loss, the control circuit 100 executes steps S11 and S12, and at step S11, the output prohibition unit 117 prohibits the supply of power from the power conversion circuit 10 to the load L D, and at step S12, the phase loss notification unit 118 notifies the user of the phase loss detected by the phase loss detection unit 116, and the startup procedure is completed.

Fig. 4 is a flowchart illustrating in detail the phase loss checking step of step S03. As shown in fig. 4, the control circuit 100 executes steps S21, S22, S23, S24, S25. In step S21, the time measurement unit 113 starts measurement of the elapsed time by a counter of clock pulses or the like. In step S22, the test control unit 115 controls the power conversion circuit 10 to start the test state. In step S23, the current information acquisition unit 112 acquires the detected values of the currents of the

lines

13U, 13V, and 13W from the

current sensors

21U, 21V, and 21W, respectively. In step S24, voltage information acquisition unit 111 acquires a detected value of the voltage of dc bus 12 from voltage sensor 22. In step S25, the open-phase detection unit 116 checks whether or not the detected values of all the currents in the

lines

13U, 13V, and 13W exceed the lower limit value.

If it is determined in step S25 that the detected values of all the currents in

lines

13U, 13V, and 13W exceed the lower limit value, control circuit 100 executes step S26. in step S26, open-phase detection unit 116 determines that there is no open phase between power conversion circuit 10 and load L D.

When it is determined in step S25 that the detected value of the current in any of

lines

13U, 13V, and 13W does not exceed the lower limit value, control circuit 100 executes step S27. In step S27, the open-phase detection unit 116 checks whether or not the current of any of the

lines

13U, 13V, and 13W is equal to or less than the current threshold (i.e., whether or not the third condition is satisfied).

When it is determined in step S27 that the current of any one of

lines

13U, 13V, and 13W is equal to or less than the current threshold value, control circuit 100 executes step S28. In step S28, the open-phase detection unit 116 checks whether or not the voltage of the dc bus 12 is equal to or less than the voltage threshold (i.e., whether or not the first condition is satisfied).

If it is determined in step S28 that the voltage of the dc bus 12 is equal to or lower than the voltage threshold, the control circuit 100 executes step S29. In step S29, the open-phase detection unit 116 checks whether the elapsed time measured by the time measurement unit 113 has reached the determination time (i.e., whether the second condition is satisfied).

When it is determined in step S29 that the elapsed time has reached the determination time, control circuit 100 executes step S31. when it is determined in step S27 that the detected values of all the currents in

lines

13U, 13V, and 13W exceed the current threshold value and when it is determined in step S28 that the voltage of dc bus 12 exceeds the voltage threshold value, control circuit 100 executes step S31 with step S29 omitted, and open-phase detection unit 116 determines in step S31 that there is an open phase between power conversion circuit 10 and load L D.

If it is determined in step S29 that the elapsed time has not reached the determination time, the control circuit 100 returns the process to step S23. Thereafter, the checking of the presence or absence of a phase defect based on the current detection values of the

lines

13U, 13V, and 13W, the voltage detection value of the dc bus 12, and the elapsed time is repeated until the current flows through all the

lines

13U, 13V, and 13W or any one of the first condition, the second condition, and the third condition is satisfied.

After steps S26, S31, the control circuit 100 executes step S32. In step S32, the test control unit 115 controls the power conversion circuit 10 so that the test state is ended. The above completes the phase loss inspection step. Fig. 4 illustrates all the open-phase inspection steps based on the detected values of the currents on the

lines

13U, 13V, and 13W, the detected value of the voltage on the dc bus 12, and the elapsed time, but these are not essential. For example, confirmation of the elapsed time may be omitted, and the presence or absence of a phase failure may be confirmed based on the current detection values of

lines

13U, 13V, and 13W and the voltage detection value of dc bus 12. The confirmation of the voltage of the dc bus 12 may be omitted, and the presence or absence of a phase defect may be confirmed based on the detected values of the currents on the

lines

13U, 13V, and 13W and the elapsed time.

(Effect of the present embodiment)

As described above, the power conversion device 1 includes the power conversion circuit 10 that converts the power of the dc bus 12 into the multi-phase ac power and supplies the multi-phase ac power to the load, the test control unit 115 that controls the power conversion circuit 10 so as to temporarily maintain a state in which at least 1 phase of the multi-phase and the remaining phases are connected to the different poles of the dc bus 12, respectively, while the voltage of the dc bus 12 increases as the dc bus 12 is connected to the dc power supply PS, and the open-phase detection unit 116 that detects the open phase based on the output current to the load L D in the above state.

According to the power converter 1, the phase failure detection is performed in the voltage rise period after the dc bus 12 is connected to the dc power supply PS, and compared to the state where the voltage between the dc buses 12 is maximized, the voltage can be applied to the phases without greatly moving the load L D in the voltage rise period.

The open-phase detection unit 116 may detect an open phase based on whether or not a phase through which no current flows exists. In this case, the phase failure can be detected more quickly with simple logic.

The phase loss detection unit 116 may detect a phase loss when a state in which a phase through which no current flows is present continues until a predetermined condition is satisfied. In this case, by continuing the state where no phase through which current flows exists until a predetermined condition is satisfied as a reference for detecting a phase loss, both rapidity of phase loss detection and reliability of phase loss detection can be achieved.

The open-phase detection unit 116 may detect an open phase by using a condition that the voltage of the dc bus 12 reaches a predetermined voltage threshold value in a state where a phase through which no current flows exists as a predetermined condition. In this case, by setting the voltage between the dc buses 12 to a predetermined voltage threshold value in a state where a phase in which no current flows exists as a reference for detecting a phase failure, it is possible to achieve both rapidity of phase failure detection and reliability of phase failure detection. In addition, when a plurality of conditions are combined, rapidity of the phase failure detection and reliability of the phase failure detection can be more reliably achieved.

The phase loss detection unit 116 may detect a phase loss under a predetermined condition that a predetermined determination time has elapsed in a state where a phase in which no current flows exists. In this case, by setting the predetermined determination time after the phase in which no current flows exists as a reference for detecting the phase loss, both rapidity of phase loss detection and reliability of phase loss detection can be achieved.

The open-phase detection unit 116 may detect a open phase under a predetermined condition that the current of the other phase reaches a predetermined current threshold in a state where the phase through which no current flows exists. In this case, by setting the current of the other phase to a predetermined current threshold value in a state where the phase in which no current flows exists as a reference for detecting the phase loss, both rapidity of phase loss detection and reliability of phase loss detection can be achieved. When a plurality of conditions are combined, the rapidity of the phase failure detection and the reliability of the phase failure detection can be more reliably achieved.

In this case, the open phase can be detected before the Voltage between the dc buses 12 reaches SE L V (safe Extra L ow Voltage) defined by IEC60364-4, IEC60950, and the like.

The power conversion circuit 10 converts the power of the dc bus 12 into 3-phase ac power, the open-phase detection unit 116 detects an open phase based on the current detection value of any 2-phase detection target phase among the 3 phases, and the test control unit 115 may control the power conversion circuit 10 to temporarily maintain a state in which the detection target phase of 2-phase among the 3 phases and the other 1-phase are connected to different poles of the dc bus 12 during a period in which the voltage of the dc bus 12 rises as the dc bus 12 is connected to the dc power supply PS. In this case, the above-described phase loss detection can be performed while reducing the number of sensors for current detection.

The power conversion apparatus 1 may further include a power supply on detection unit 114, the power supply on detection unit 114 may detect that the dc bus 12 is connected to the dc power supply PS based on a voltage rise of the dc bus 12, and the test control unit 115 and the open-phase detection unit 116 may start processing for detecting open phase based on the detection that the dc bus 12 is connected to the dc power supply PS by the power supply on detection unit 114. In this case, the above-described phase failure detection can be performed regardless of whether a sensor dedicated to detection of power supply on (connection of the dc bus to the dc power supply) is provided, or information on timing for switching the power switch SW from the off state to the on state is acquired from an upper controller or the like.

The embodiments have been described above, but the present disclosure is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the present invention.

1. A power conversion device, 10.. power conversion circuit, 12.. DC bus, 114.. power-on detection unit, 115.. test control unit, 116.. open-phase detection unit, L D.. load, PS.. DC power supply.

Claims

1. A power conversion device comprising:

a power conversion circuit that converts power of the dc bus into multi-phase ac power and supplies the multi-phase ac power to a load;

a test control unit that controls the power conversion circuit so as to temporarily maintain a state in which at least 1 phase and the remaining phases of the plurality of phases are connected to different poles of the dc bus, respectively, while the voltage of the dc bus increases as the dc bus is connected to a dc power supply; and

and a phase loss detection unit that detects a phase loss between the power conversion circuit and the load based on the output current to the load in the state.

2. The power conversion apparatus according to claim 1,

the open-phase detection unit detects the open phase based on whether or not there is a phase in which no current flows.

3. The power conversion apparatus according to claim 2,

the phase loss detection unit detects the phase loss when a state in which a phase in which no current flows continues until a predetermined condition is satisfied.

4. The power conversion apparatus according to claim 3,

the open-phase detection unit detects the open phase by using, as the predetermined condition, a condition that a voltage of the dc bus reaches a predetermined voltage threshold in a state where a phase through which no current flows exists.

5. The power conversion apparatus according to claim 3 or 4,

the open-phase detection unit detects the open phase by using, as the predetermined condition, a predetermined determination time that has elapsed in a state where a phase in which no current flows exists.

6. The power conversion apparatus according to claim 3 or 4,

the open-phase detection unit detects the open phase by using, as the predetermined condition, a condition that a current of another phase reaches a predetermined current threshold value in a state where a phase through which no current flows exists.

7. The power conversion apparatus according to claim 3 or 4,

the predetermined condition is set so that the open phase can be detected before the voltage of the dc bus reaches 60 volts.

8. The power conversion apparatus according to any one of claims 1 to 4,

the power conversion circuit converts the power of the dc bus into the 3-phase ac power,

the open-phase detection unit detects an open phase between the power conversion circuit and the load based on a current detection value of a detection target phase of any 2 phases out of the 3 phases,

the test control unit controls the power conversion circuit to temporarily maintain a state in which the detection target phase of the 2 phases and the other 1 phases among the 3 phases are connected to different poles of the dc bus while the voltage of the dc bus increases as the dc bus is connected to the dc power supply.

9. The power conversion apparatus according to any one of claims 1 to 4, further comprising:

a power-on detection unit that detects that the DC bus is connected to the DC power supply based on a voltage rise of the DC bus,

the test control unit and the open-phase detection unit start processing for detecting the open phase in response to the power-on detection unit detecting that the dc bus is connected to the dc power supply.

10. A power conversion method, comprising:

controlling the power conversion circuit to temporarily maintain a state in which at least 1 phase and the remaining phase of the plurality of phases are connected to different poles of the dc bus, respectively, while a voltage of the dc bus rises as the dc bus of the power conversion circuit is connected to a dc power supply, the power conversion circuit converting power of the dc bus into multiphase ac power and supplying the multiphase ac power to a load; and

detecting a phase loss between the power conversion circuit and the load based on an output current to the load in the state.