JP2002136147A - Inverter circuit failure detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect an open failure in an inverter circuit formed with a boot strap capacitor for a high-arm driver driving a high-arm side switching device, without making judgment, from the availability of operation thereof. SOLUTION: With (i) fixed in a single switching period, a mode S0 and a mode Si (1<=i<=6) are switched alternately in a switching timing at ordinary operation, and the single switching period is repeated six times by changing (i). The types of the single switching periods, which cause electric current not to be passed through a shunt resistor 6, are different from each other, depending upon the type of the open failure. Diagnosis of open failures can be made by measuring the electrical current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for detecting a fault in a polyphase inverter circuit, and more particularly to a technique for detecting a fault in an inverter circuit provided with a bootstrap capacitor for a high-arm driver for driving a high-arm switching element. About.

[0002]

2. Description of the Related Art A so-called open fault is one type of fault in a polyphase inverter circuit for driving a polyphase motor. This is a failure in which the connection between the polyphase motor and the power supply that supplies a predetermined current to the polyphase motor is not established even when the timing is to connect the two.

[0003]

Such an open fault cannot be reliably detected only by the availability of the operation of the polyphase motor. When a fan with a large inertia is mounted on a multi-phase motor, even if an open failure occurs in one phase and so-called open-phase operation occurs, once the rotation due to conduction of the other phase occurs once, the rotation continues. Because.

On the other hand, conventionally, in a polyphase inverter circuit, a configuration in which a bootstrap capacitor is provided for a high-arm driver for driving a high-arm switching element has been used. Unless the bootstrap capacitor is charged, the high-arm driver cannot be operated, and thus the conduction of the high-arm switching element cannot be controlled.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an open failure of an inverter circuit provided with a bootstrap capacitor for a high-arm driver for driving a high-arm switching element is determined based on whether or not operation is possible. Instead, it aims to provide a detection technique.

[0006]

Means for Solving the Problems Claim 1 of the present invention
Are connected to the polyphase load (200) and output lines (81, 82,...) Corresponding to the respective phases of the polyphase (U, V, W).
83) and a high-arm switching element (21, 22, 23) provided corresponding to each phase and connected between the output line and the first power supply (VC) in each phase.
And a second, which is provided corresponding to each of the phases and gives a lower potential than the output line and the first power supply in each of the phases.
And a driver (41, 42, 4) for driving the low-arm switching element (31, 32, 33) connected between the low-arm switching element and the power supply (G).
3) In each of the phases, the corresponding output line is connected to the third power supply (G) which supplies a higher potential than the second power supply (G).
And a bootstrap capacitor (71, 72, 73) connected between the power supply (VD) of the inverter and a bootstrap capacitor (71, 72, 73). A first switching mode (S ₀ ) in which the switching element and the low-arm switching element are turned on, wherein the low-arm switching element is turned on in all of the phases; and at least one of the phases. one of the high-arm side switching element and the phase of the second switching mode of at least one of said low-arm side switching element is turned on (S ₁ ~S ₆₎ and is set. Then, a single switching cycle that alternately employs the first switching mode and the one second switching mode is set for each of the second switching modes. Then, the single switching cycle is repeated by changing the second switching mode.

[0007] According to a second aspect of the present invention,
A fault detection method of an inverter circuit according to claim 1, wherein in the single switching cycle, and the first switching mode (S _0), and one said second switching mode (S ₁ to S ₆₎ in all of the phases the low-arm side switching element is a third switching mode to off (S _7, S ₈₎ and is employed repeatedly.

[0008] According to a third aspect of the present invention,
3. The inverter circuit failure detection method according to claim 1, wherein the low-arm side switching element is turned off in all of the phases during the adjacent single switching cycle. 4. S ₇ ,
S ₈ ) is inserted.

[0009] The present invention according to claim 4 includes:
4. The method for detecting a fault in an inverter circuit according to claim 1, wherein the fault is measured in a period (T2) after an initial period (T1) of a current flowing through the inverter circuit. The presence or absence of a failure is determined based on the current flowing.

[0010] The invention according to claim 5 is as follows.
The fault detection method for an inverter circuit according to any one of claims 1 to 4, wherein the multi-phase load is a multi-phase motor (200) having a rotor, and The position of the rotor fixed by the second switching mode adopted by the switching cycle is the position of the rotor before the single switching cycle is given.

[0011] The invention according to claim 6 is as follows.
The fault detection method for an inverter circuit according to any one of claims 1 to 5, wherein the single switching cycle includes the second switching mode (S) in a predetermined order.
_{1 to} S ₆ ) are repeated, and in the second switching mode adjacent in the predetermined order, one of the high-arm switching elements (21, 22, 23) is turned on in common, One of the low-arm switching elements (31, 32, 33) is turned on in common.

According to a seventh aspect of the present invention,
4. The method for detecting a failure in an inverter circuit according to claim 1, wherein when the current flowing through the inverter circuit becomes excessive, the low-arm switching element in all of the phases. Turns off third
The switching mode (S ₈ ) is adopted, and the inter-phase short circuit is detected by stopping the current.

[0013] The present invention according to claim 8 includes:
4. The method according to claim 1, wherein a failure is determined based on a current flowing through the inverter circuit, and the determination level for determining whether the current is present is a temperature level. 5. Is corrected by

According to a ninth aspect of the present invention, there is provided:
4. The method for detecting a failure in an inverter circuit according to claim 1, wherein a failure level is determined based on a current flowing through the inverter circuit, and the determination level for determining the presence or absence of the current is the determination level. The correction is made by the voltage between the first power supply (VC) and the second power supply (G).

[0015]

In the inverter circuit fault detecting method according to the first aspect of the present invention, the bootstrap capacitors (71, 72, 73) are charged by the first switching mode (S ₀ ) in a single switching cycle. Whether or not a current flows in the second switching mode (S _{1 to} S ₆ ) employed in a single switching cycle differs depending on the location of a fault occurring in the inverter circuit.

In the inverter circuit fault detecting method according to the second or third aspect of the present invention, no current flows through the inverter circuit in the third switching mode (S ₇ , S ₈ ). It does not hinder.

In the method for detecting a failure of an inverter circuit according to a fourth aspect of the present invention, the charging of the bootstrap capacitors (71, 72, 73) and the multiphase load (20) are performed.
0) during the initial period (T
1) is removed from the basis of the failure determination.

In the inverter circuit failure detecting method according to the present invention, the rotor position does not move during the first single switching cycle.

According to the inverter circuit failure detecting method of the present invention, the operation of the multi-phase load is performed smoothly.

In the method for detecting a fault in an inverter circuit according to the present invention, the current flowing through the inverter circuit is stopped by a switching mode adopted when an excessive current flows.

In the inverter circuit fault detecting method according to the present invention, the influence of an external factor on the current flowing through the inverter circuit is compensated.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a connection relationship between the inverter circuit and the multi-phase motor 200. Output lines 81, 82, and 83 are provided corresponding to the U-phase, V-phase, and W-phase, respectively, and these are connected to the polyphase motor 200. For example, an IGBT with a protection diode as a high-arm side switching element
21, 22, and 23 are provided corresponding to the U phase, the V phase, and the W phase, respectively. For example, the motor power supply VC that supplies 300 V conducts to the output lines 81, 82, and 83, respectively, when the IGBTs 21, 22, and 23 are turned on.
On the other hand, for example, IGBTs 31, 32, and 33 with protection diodes are provided corresponding to the U-phase, V-phase, and W-phase, respectively, as the low-arm side switching elements. Is electrically connected to the ground G via the shunt resistor 6 for current detection. The current flowing through the shunt resistor 6 can be detected as a voltage drop in the shunt resistor 6 by the voltage measuring unit 9. Of course, it is sufficient that the current flowing through each phase can be measured without using a combination of the shunt resistor 6 and the voltage measuring unit 9. May be detected.

IGBTs 21, 22, 23, 31, 32,
33 are turned on / off by drivers 41, 42, 4 respectively.
3, 51, 52, and 53 control the gate potential. These drivers 41, 42, 4
The operations of 3, 51, 52, and 53 are performed by the microprocessor 1
The signals are controlled based on signals S ₄₁ , S ₄₂ , S ₄₃ , S ₅₁ , S ₅₂ , S ₅₃ from 00, respectively. For example, when the current flowing through the shunt resistor 6 is excessive, the voltage measuring unit 9 transmits a signal 91 to the microprocessor 100 and notifies the microprocessor 100 of the fact. The microprocessor 100 performs control to turn off all the IGBTs 21, 22, 23, 31, 32, and 33 based on the signal 91.

Drivers 41, 42, 43 on the high arm side
Are supplied from bootstrap capacitors 71, 72, 73, respectively, so that a gate potential can be appropriately applied to the IGBTs 21, 22, 23 on the high arm side. Bootstrap capacitors 71, 72, 73 are U
, V, and W-phase resistors 11, 12,
13, a charging power supply VD for supplying 15 V, for example.
And the output lines 81, 82, and 83, and are charged. That is, the resistors 11, 12, and 13 are connected in series to the charging paths of the bootstrap capacitors 71, 72, and 73. Even when the potentials of the output lines 81, 82 and 83 are high, the resistor 12 and the bootstrap capacitor 7 are connected between the resistor 11 and the bootstrap capacitor 71 so that the bootstrap capacitors 71, 72 and 73 do not discharge.
2, the resistor 13 and the bootstrap capacitor 73
And a diode is interposed between them.

In the inverter circuit configured as described above, the signals S ₄₁ and S ₄₂ due to a failure of the IGBTs 21, 22 and 23 or a poor connection between the motor power supply VC and the output lines 81, 82 and 83. , regardless of the S _43, open failure may occur that between the power supply VC motor and the output lines 81, 82 and 83 enters an open state. Similarly, regardless of the signals S ₅₁ , S ₅₂ and S ₅₃ , the ground G and the output line 8
1, 82, 83 may cause an open failure.

In order to detect such an open fault, I
The switching modes of the GBTs 21, 22, 23, 31, 32, and 33 are variously controlled. Normally, under the control of the microprocessor 100, when the switching element of one arm of a phase is on, the switching element of the other arm of the phase is off. In other words, under the control of the microprocessor 100, the IGBTs on the high arm side and the low arm side do not turn on simultaneously in the same phase. For example, when the IGBT 21 is on, the IG
The BT 31 turns off. In the normal operation, the IGBTs on the high arm side and the low arm side are exclusively turned on / off in the same phase. However, when the switching mode changes, all IGBs are locally
A period during which T21, 22, 23, 31, 32, and 33 are turned off (hereinafter, referred to as "guard band") may be provided.

When variables u, v, and w are set for the IGBTs 21, 22, 23, and the values 1, 0 are used for the on / off states, the switching mode of the inverter circuit is S _{4u + 2v +} It can be represented by _w . For example aspects S ₄ is IGBT21,22,23,31,32,
Reference numeral 33 denotes a switching mode for turning on, off, off, off, on, and on, respectively.

In the following description, it is assumed that no short-circuit fault has occurred. For example, in the embodiment S ₄ IGBT 31
Are provided in the U-phase low arm side, the V-phase high arm side provided with the IGBT 22, and the W-phase high arm side provided with the IGBT 23. Therefore, if no current is detected in the shunt resistor 6, an open failure has occurred in the U-phase high arm provided with the IGBT 21 or the V-phase low arm provided with the IGBT 32 and the IGBT 33 are provided. This means that an open fault has occurred on both of the W-phase low arms, or that an open fault has occurred in all of the three arms. The possibility of such three types of open faults can be determined by narrowing the range of open faults by detecting the presence or absence of a current flowing through the shunt resistor 6 for the switching modes S _{1 to} S ₆ . it can.

[0029] If the current does not flow through the shunt resistor 6 only in aspects S ₄ for example, it is determined that open failure has occurred in the high-arm side of the U-phase. Aspects S ₅ and S ₆
In this case, no open failure has occurred on either the V-phase low arm side or the W-phase low arm side due to the current flowing through the shunt resistor 6.

However, an open failure occurs in three or more arms.
In some cases, switching mode S ₁~ S₆Against
Even if the presence or absence of the current flowing through the
Cannot be identified. For example, everything on the high arm side, lower
High side and lower in all two phases
If the four arms on the side of the
Is the switching mode S₁~ S₆In either case,
Since no current flows through the shunt resistor 6, these failures
Cannot be distinguished from each other. Also, for example,
If there is a failure on the U-phase and V-phase high arm side,
Unable to determine if there is an open failure on the low arm side of W phase
No. Regardless of whether there is an open failure on the low arm side of W phase
And aspect S₁, S_Three, S_FiveAt the shunt resistor 6
Flows, mode S_Two, S_Four, S₆At shunt resistor 6
This is because no current flows.

Therefore, when there are two or less open faults, the location of the open fault can be detected as shown in the following table.

[0032]

[Table 1]

In the column of the location of the open failure, × and ○ indicate
Indicates the presence or absence of an open fault, respectively.
○ and × indicate the current flowing through the shunt resistor 6 respectively.
Indicates nothing. The top and bottom of the column correspond to each other,
For example, as shown in the eighth column from the left, U-phase and V-phase
If there is an open failure on the system side,
S ₁, S_Three, S_Five, A current flows through the shunt resistor 6,
Aspect S_Two, S_Four, S₆Current flows through the shunt resistor 6 at
Not shown.

Now, in order to perform the above-mentioned switching mode, the switching elements IGBT21, IGBT21,
In order for the devices 22 and 23 to operate properly, it is necessary to realize a switching mode for charging the bootstrap capacitors 71, 72 and 73. That is, the switching elements IGBT31, 32, and 33 on the low arm side of all phases are turned on. In this case is the 4u + 2v + w = 0, represents the switching mode at S _0.

In order to measure the current flowing through the shunt resistor 6, a measuring period on the order of seconds is required. On the other hand, in normal operation, the switching mode changes between each other on the order of tens of microseconds. Therefore, in the switching mode of transition of the timing used in normal operation (hereinafter referred to as "switching timing of normal operation"), also perform aspects S ₁ once, the current flowing through the shunt resistor 6 in embodiments S ₁ Can not be measured. Further, executing the aspects S ₀ once in one cycle of the switching timing of the normal operation, the bootstrap capacitor 71, 72, 73
Cannot be sufficiently charged, and the switching modes S _{1 to} S ₆ cannot be normally realized.

As described above, according to the present invention, in the predetermined period (hereinafter referred to as "single switching period"), i is fixed and the switching timing during normal operation is changed to the mode S.
₀ and the mode S _i (1 ≦ i ≦ 6) are alternately switched,
The open fault is diagnosed by changing the i and repeating the single switching cycle six times.

FIG. 2 shows that a single switching cycle is repeated six times.
The switching mode when returning and the shunt resistor 6
The relationship between the flowing current and the U-phase low arm side and V-phase
If there is an open fault only on the low arm side
It is a timing chart shown as an example. Right of Table 1
In this case, as shown in the third column,
S ₁, S_Three, S_FiveCurrent flows through the shunt resistor 6 at
And aspect S_Two, S_Four, S₆A current flows at. Current
The presence / absence is determined by the determination level I indicated by a chain line in the figure._thThan electricity
It is determined by whether the flow is large or small.

[0038] FIG. 3 is a timing chart showing the details of a single switching period with aspects S _1. The modes S ₁ and S ₀ are alternately performed at the switching timing during normal operation indicated by the broken line by turning on / off the signals S ₄₁ , S ₄₂ , S ₄₃ , S ₅₁ , S ₅₂ , and S ₅₃ .

As described above, according to the present embodiment, an open failure of an inverter circuit provided with a bootstrap capacitor can be detected without determining whether or not operation is possible.

Further, a short circuit between phases can be detected. For example between the output lines 81 and 82, i.e., when a short circuit has occurred between the U-phase and V-phase, via the load that polyphase motor 200 from IGBT21 to IGBT32 in a single switching period with aspects S ₄ The current flows without any change. Therefore, the current flowing through the shunt resistor 6 becomes transiently excessive, and the voltage measurement unit 9 and the microprocessor 10
Due to the function of 0, no current flows through the shunt resistor 6 thereafter. Therefore, if a current flows through the shunt resistor 6 even after repeating a single switching cycle six times, it can be determined that not only an open fault but also a short-circuit between phases has not occurred.

Second embodiment. FIG. 4 is a timing chart showing the second embodiment of the present invention, and shows a modification of the timing chart shown in FIG. 3 of the first embodiment. Is shown here as an example a case of using a mode S ₁ in a single switching cycle. To turn on the switching element IGBT21,22,23 the high-arm side of all phases, and aspects S ₇ to turn off the switching element IGBT31,32,33 the low-arm side are provided in this embodiment. Aspects S ₇ of the switching, since no current to the shunt resistor 6 does not become an obstacle in the determination of the open failure.

As described above, by forcibly providing a period during which no current flows through the shunt resistor 6, it is possible to prevent the motor from being damaged by excessively flowing the current.

Similarly, a single switching cycle using modes S ₀ and S ₇ may be interposed between adjacent single switching cycles in FIG. FIG. 5 shows embodiment S _7.
7 is a timing chart showing a case where a single switching cycle is interpolated using a case where no failure occurs. In this view in the same way as in FIG. 2, the presence or absence of current is determined by whether the current is greater smaller than the decision level I _th indicated by a chain line. Without open failure has occurred in a single switching period with aspects S _7, no current flows through the shunt resistor 6.

Alternatively, a more specific switching mode is used.
And the mode S corresponding to the guard band ₈You can also adopt
it can. Single switching in FIG. 2
Aspect S during the cycle₈Or in FIG. 4
Aspect S₇Mode S during the period when₈You may adopt
No.

Third Embodiment At the beginning of a single switching cycle, a transient current flows due to charging of the boot capacitors 71, 72, 73 regardless of the presence or absence of an open fault. Further, a magnetic field is generated in the motor 200 by the current flowing in a single switching cycle, and the rotor moves, so that the current flowing in the shunt resistor 6 also fluctuates.

Therefore, in a single switching cycle using the modes S _{1 to} S ₆ , the current measured in the subsequent period T 2 is averaged except for the initial period T 1 shown in the graph of FIG. The basis for the judgment
Desirable for accurate judgment. The initial period T1 is set to, for example, 0.1 second. The function of measuring the current during the period set as described above can be assigned to the voltage measurement unit 9 using a known technique.

Fourth Embodiment The magnetic field generated in the multi-phase motor 200 is unique for each switching mode, and in a single switching period in which a certain switching mode is adopted, the rotor of the multi-phase motor 200 is fixed at a predetermined fixed position.

Therefore, in the present embodiment, a switching mode in which the position of the rotor of the multi-phase motor 200 before the single switching cycle is given is adopted as the single switching cycle given first. Thus, the rotor of the multi-phase motor 200 does not move in the single switching cycle, and the calculation time for measuring the current flowing through the shunt resistor 6 in the switching mode adopted here can be reduced. As a result, the time required for failure detection can be shortened.

Fifth Embodiment The single switching periods need not necessarily be provided in the order shown in FIG.
Rather, it is desirable to provide them in a predetermined order in order to smoothly move the rotor of the multi-phase motor 200. This predetermined order, considering except aspects S _0, switching mode employed in a single switching cycle of adjacent,
There is a phase commonly turned on on each of the high arm side and the low arm side. The following table shows the example, a switching mode employed in a single switching cycle (excluding aspects S _0), are shown in each ON / OFF to the phase ○ / in ×.

[0050]

[Table 2]

[0051] First, it looks at the high-arm side, U-phase and V-phase in the switching mode S ₆ is on. Since only switching mode S ₄ the U-phase is turned on, between the two are on common the U-phase. Since switching mode S ₅ in the U-phase and W-phase are turned on, are turned on in common the U-phase in between switching mode S _4, S _5. Since W-phase in the switching mode S1 only is turned on, are turned on in common is the W phase between the switching mode S _5, S _1. Since the V-phase and W-phase in the switching mode S ₃ is turned on, the W-phase even during switching mode S _1, S ₃ is turned on in common. Since only switching mode S ₂ the V-phase is turned on, V is between the switching mode S _3, S ₂
The phases are on in common. Further, the V-phase is commonly turned on between the switching modes S ₂ and S ₆ .

[0052] and then look at the low-arm side, only the W-phase in switching mode S ₆ is turned on. Since the V-phase in the switching mode S ₄ and W-phase are turned on, between the two W-phase are turned on in common. Since only switching mode S ₅ the V-phase is turned on, are turned on in common is the V-phase among the switching mode S _4, S _5. Since switching mode S ₁ in U and V phases are turned on, are turned on in common is the V phase in between switching mode S _5, S _1. Since the only U-phase switching mode S ₃ is turned on, between the switching mode S _1, S ₃ are turned on in common the U-phase. Since switching mode S ₂ in the U-phase and W-phase are turned on, U even during switching mode S _3, S ₂
The phases are on in common. Further, between the switching modes S ₂ and S ₆ , the W phase is commonly turned on.

Therefore, if the switching modes including the single switching cycle are considered except for the mode S ₀ , S ₆ ,
By shifting in the order of S ₄ , S ₅ , S ₁ , S ₃ , S ₂ , S ₆ ,..., There is a phase that is commonly turned on on each of the high arm side and the low arm side. Therefore, the rotor of the multi-phase motor 200 can be moved smoothly, and the calculation time for obtaining the average of the current detection shown in the fifth embodiment can be reduced.

Of course, starting from a single switching cycle employing any switching mode, single switching employing a switching mode determined based on the position of the rotor of the multi-phase motor 200 according to, for example, the fourth embodiment. You may start with a cycle. For example, S ₃ , S ₂ , S
_6, S _4, S _5, may be adopted order of S _1. Alternatively, the order from bottom to top of Table 2, for example, S ₂ , S ₃ , S
_1, S _5, S _4, may be adopted order of S _6.

Sixth embodiment. The current flowing through the shunt resistor 6 fluctuates due to factors other than the charging of the boot capacitors 71, 72, 73. In the present invention, when the open failure of the multi-phase motor 200 is determined, a check is performed by applying a voltage to the multi-phase motor 200 and flowing a current. This is because the resistance of the coil of the coil is also affected by the temperature change.

[0056] Thus, in this embodiment, to detect the temperature and power supply voltage, so that by increasing or decreasing the determined level I _th corrected according to, to compensate for the influence of external factors of the current flowing through the inverter circuit. This makes it possible to more accurately determine the open failure according to the first to third embodiments.

Such a function can be realized by the voltage measuring unit 9 as shown in the circuit diagram of FIG. 7, for example.
The voltage measurement unit 9 includes a temperature sensor 92 and a power supply VC for the motor.
There are connected, to detect the temperature and power supply voltage, the determination level I _th increases or decreases according to the result, to transmit a signal 91 to the microprocessor 100 in accordance with the decision level I _th.

[0058]

According to the inverter circuit failure detecting method according to the first aspect of the present invention, the multi-phase load (200).
By detecting the sum of the currents flowing through the respective phases without confirming the operation of the inverter circuit, it is possible to detect a fault in the inverter circuit, particularly, two or less open faults.

According to the inverter circuit failure detecting method according to claim 2 or 3, a period in which no current flows is forcibly provided, so that the current flows excessively and the multi-phase load (200 ) Can be avoided.

According to the inverter circuit failure detecting method of the present invention, the failure can be accurately determined.

According to the inverter circuit fault detecting method of the present invention, the time required for fault detection can be shortened.

According to the inverter circuit failure detecting method of the present invention, the calculation time for measuring the current flowing through the inverter circuit can be reduced.

According to the inverter circuit fault detecting method of the present invention, not only an open fault but also a short-circuit between phases can be detected.

According to the inverter circuit fault detecting method of the present invention, an open fault can be determined more accurately.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit to which a first embodiment of the present invention is applied;

FIG. 2 is a timing chart showing the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a timing chart showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing a second embodiment of the present invention.

FIG. 6 is a graph showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a circuit used in a sixth embodiment of the present invention.

[Explanation of symbols]

6 Current detection resistor 9 Voltage measurement unit 21, 22, 23, 31, 32, 33 IGBT 41, 42, 43 Driver 71, 72, 73 Bootstrap capacitor 81, 82, 83 Output line 200 Multi-phase motor S ₀ , S _{1, S 2, S 3,} S 4, S 5, S 6, S 7, S 8 switching mode G grounding VC motor power supply VD charging power source

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshiaki Sato Okamoto-cho, Okamoto-cho, Shiga, 1000-2 Daiya Industries Co., Ltd. Shiga Works (72) Inventor Masanobu Tomoe, Okamoto-cho, Okamoto-cho, Shiga, 1000 F-term (reference) in Daikin Industries, Ltd. Shiga Works 5H007 AA05 BB06 CA01 CB04 CB05 CC23 DB12 DC02 DC05 DC08 FA13

Claims (9)

[Claims] An output line (81, 82,...) Connected to a polyphase load (200) and corresponding to each phase of the polyphase (U, V, W).
83); a high-arm switching element (21, 22, 23) provided corresponding to each of the phases and connected between the output line and the first power supply (VC) in each of the phases; A low-arm switching element (31, 32) provided corresponding to each phase and connected between the output line in each phase and a second power supply (G) for applying a lower potential than the first power supply; , 33) and the driver (41, 42, 43) for driving the high-arm switching element, so that in each of the phases, the corresponding output line and a higher potential than the second power supply (G) are applied. A high-side switching element is exclusively provided in each phase for an inverter circuit including a bootstrap capacitor (71, 72, 73) connected to a third power supply (VD). A first switching mode (S ₀ ) in which the low-arm switching element is turned on in all of the phases; and a first switching mode (S ₀ ) in which the low-arm switching element is turned on in all of the phases. A second switching mode (S _{1) in which the} high-arm switching element and at least one of the low-arm switching elements of each of the phases are turned on.
To S ₆ ) are set, and a single switching cycle that alternately employs the first switching mode and the one second switching mode is set for each of the second switching modes, and the single switching mode is set. A method for detecting a fault in an inverter circuit, wherein a cycle is repeated by changing the second switching mode. 2. In one single switching cycle, the first switching mode (S ₀ ) and the second switching mode
And the switching mode (S ₁ to S _6), the low-arm side switching elements in all of the phases is a third switching mode (S _7, S ₈₎ to turn off and is employed repeatedly, according to claim 1, wherein Method of detecting inverter circuit failure. 3. A third switching mode (S ₇₎ in which the low-arm switching element is turned off in all of the phases during the adjacent single switching cycle.
S ₈₎ is interposed, the failure detection method of an inverter circuit according to claim 1 or claim 2, wherein. 4. The method according to claim 1, wherein the presence or absence of a failure is determined based on a current measured in a period (T2) after the initial period (T1) of the current flowing through the inverter circuit. The method for detecting a failure of the inverter circuit according to any one of the above. 5. The multi-phase load is a multi-phase motor (200) having a rotor, wherein the position of the rotor fixed by the second switching mode adopted by the single switching cycle given first is: The method for detecting a fault in an inverter circuit according to claim 1, wherein the position is the position of the rotor before the single switching cycle is given. 6. The single switching cycle is repeated by changing the second switching modes (S _{1 to} S ₆ ) in a predetermined order, and in the second switching mode adjacent in the predetermined order. , The high-arm side switching element (2
, 22, 23) turns on in common, and the low-arm side switching element (31, 32, 33)
6. The method for detecting a fault in an inverter circuit according to claim 1, wherein any one of the methods is turned on in common. 7. A third switching mode (S ₈ ) in which the low-arm switching element is turned off in all of the phases when the current flowing through the inverter circuit becomes excessive, and the current is stopped. The method for detecting a fault in an inverter circuit according to any one of claims 1 to 3, wherein a short circuit between phases is detected by the following method. 8. The method according to claim 1, wherein a failure is determined based on a current flowing through the inverter circuit, and a determination level for determining the presence or absence of the current is corrected based on a temperature. Inverter circuit failure detection method. 9. A failure level is determined based on a current flowing through the inverter circuit, and a determination level for determining the presence or absence of the current is a level between the first power supply (VC) and the second power supply (G). 4. The method for detecting a fault in an inverter circuit according to claim 1, wherein the fault is corrected by a voltage.