JP2015154572A - Failure detection method of inverter circuit, driving device and motor driving system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a configuration for detecting an open-circuit failure in switching elements which are connected in parallel.SOLUTION: A failure detection method of an inverter circuit is disclosed. The inverter circuit includes a plurality of phases of switching circuits. In each of the switching circuits, a plurality of switching elements connected in parallel are provided in each of upper and lower arms and the upper arm and the lower arm are connected in series. According to the failure detection method of the inverter circuit, while any one of the upper arm and the lower arm is driven, driving of partial switching elements among the plurality of switching elements provided in the one arm is stopped. When it is detected that a current that re-flows during a period in which the driving of the partial switching elements is stopped flows to the other arm provided in the switching circuit of the same phase as the one arm, it is determined that an open-circuit failure occurs in switching elements different from the partial switching elements among the plurality of switching elements provided in the one arm.

Description

  The present invention relates to a failure detection method, a drive device, and a motor drive system for an inverter circuit having a switching circuit in which a plurality of switching elements connected in parallel are provided on each of an upper arm and a lower arm.

  Conventionally, an inverter device having a switching circuit in which a plurality of switching elements connected in parallel is provided in each of an upper arm and a lower arm is known (see, for example, Patent Document 1). This inverter device detects an open failure of a plurality of switching elements by a temperature detection sensor arranged in the middle of the plurality of switching elements connected in parallel.

JP 2012-75279 A

  However, since the above-described conventional technology requires a temperature detection sensor for each group of switching elements connected in parallel, an open failure cannot be detected with a simple configuration, and the cost may increase.

  Therefore, an object of the present invention is to provide an inverter circuit failure detection method, a drive device, and a motor drive system that can simplify the configuration for detecting an open failure of each switching element connected in parallel.

One idea is that
A fault detection method for an inverter circuit having a plurality of switching elements provided in parallel in which a plurality of switching elements connected in parallel are provided in each of an upper arm and a lower arm, and the upper arm and the lower arm are connected in series Because
During driving of either the upper arm or the lower arm, driving of some of the switching elements provided in the one arm is stopped,
When it is detected that a current that circulates during the period when the driving of some of the switching elements is stopped flows to the other arm provided in the switching circuit in phase with the one arm, Provided is a fault detection method for an inverter circuit, in which it is determined that an open fault has occurred in a switching element different from the part of the plurality of switching elements provided.

  According to one aspect, it is possible to simplify the configuration for detecting an open failure of each switching element connected in parallel.

Configuration diagram showing an example of a drive device and a motor drive system Flow chart showing an example of a failure detection method for an inverter circuit The figure for demonstrating an example of the detection method of the open failure of the switching element of the one side of an upper arm Timing chart showing an example of each waveform when the switching element on one side of the upper arm has no open failure Timing chart showing an example of each waveform when the switching element on one side of the upper arm has an open failure The figure for demonstrating an example of the detection method of the open failure of the switching element of the one side of a lower arm Timing chart showing an example of each waveform when the switching element on one side of the lower arm does not have an open failure Timing chart showing an example of each waveform when the switching element on one side of the lower arm has an open failure

  FIG. 1 is a configuration diagram illustrating an example of a drive device 11 and a motor drive system 1. The motor drive system 1 is an example of a system mounted on a vehicle, and includes a drive device 11 and a motor 12 driven by the drive device 11.

  The motor 12 is an example of an inductive load that is driven by a current supplied from the inverter circuit 20 of the drive device 11. The motor 12 is, for example, a three-phase (U-phase, V-phase, W-phase) brushless motor, but may be a multiphase motor other than the three-phase motor (for example, a five-phase motor). .

  In the illustrated inverter circuit 20, only the switching circuits 40 and 60 for two phases are shown for convenience of explanation, and the illustration of the switching circuit for one phase is omitted. In other words, if the inverter circuit 20 is a case of driving a three-phase motor, the inverter circuit 20 has the same three switching circuits as the number of phases of the three-phase motor and is driving a five-phase motor. The five switching circuits have the same number of phases as the five-phase motor.

  A specific example of the motor drive system 1 is an electric power steering device that assists the steering operation by the driver. In this case, the motor 12 is an example of an actuator that generates an assist force for assisting the steering operation by the driver by being driven by the inverter circuit 20 of the drive device 11.

  The drive device 11 includes an inverter circuit 20 and a control unit 30.

  The inverter circuit 20 is an example of an inverter circuit having a plurality of phases of switching circuits provided by connecting an upper arm and a lower arm in series, and has a circuit configuration in which a plurality of switching circuits having the same configuration are connected in parallel. doing. The inverter circuit 20 includes, for example, a U-phase switching circuit 40, a V-phase switching circuit 60, and a W-phase switching circuit (not shown).

  The switching circuit 40 is an example of a switching circuit provided with an upper arm 41 and a lower arm 46 connected in series between the high power supply potential unit 21 and the low power supply potential unit 22. The upper arm 41 is a switching element group provided on the high side on the high power supply potential part 21 side with respect to the intermediate node 51, and the lower arm 46 is on the low side on the low power supply potential part 22 side with respect to the intermediate node 51. It is a switching element group provided. The intermediate node 51 is connected to a U-phase coil of the motor 12, for example.

  The high power supply potential unit 21 is a part that is conductively connected to a positive terminal of a power supply such as a battery or a converter. The low power supply potential portion 22 having a lower potential than the high power supply potential portion 21 is a ground portion that is conductively connected to, for example, a negative terminal of a power source such as a battery or a converter, or a vehicle body grounding portion.

  In the switching circuit 40, a plurality of switching elements connected in parallel are provided on each of the upper arm 41 and the lower arm 46. In the illustrated case, the upper arm 41 is provided with two transistors 42 and a transistor 43 connected in parallel, and the lower arm 46 is provided with two transistors 47 and a transistor 48 connected in parallel. Yes.

  The switching circuit 60 is an example of a switching circuit in which an upper arm 61 and a lower arm 66 are provided in series between the high power supply potential unit 21 and the low power supply potential unit 22. The upper arm 61 is a switching element group provided on the high side on the high power supply potential unit 21 side with respect to the intermediate node 71, and the lower arm 66 is on the low side on the low power supply potential unit 22 side with respect to the intermediate node 71. It is a switching element group provided. The intermediate node 71 is connected to, for example, a V-phase coil of the motor 12.

  In the switching circuit 60, a plurality of switching elements connected in parallel are provided in each of the upper arm 61 and the lower arm 66. In the illustrated case, the upper arm 61 is provided with two transistors 62 and 63 connected in parallel, and the lower arm 66 is provided with two transistors 67 and 68 connected in parallel. Yes.

  Each transistor is an example of a switching element that performs an on / off operation. For example, the transistor is an insulated gate voltage-controlled semiconductor element that includes a control electrode, a first main electrode, and a second main electrode. Specific examples of the transistor include power transistor elements such as MOSFET and IGBT. In the drawing, an N-channel type MOSFET is shown.

  Hereinafter, for convenience of explanation, it is assumed that each transistor is a MOSFET. If each transistor is an IGBT, it may be read by replacing “drain” with “collector” and “source” with “emitter”.

  The gate electrode of the transistor 42 is an example of a control electrode connected to the inverter drive circuit 31 of the control unit 30. The drain electrode of the transistor 42 is an example of a first main electrode connected to the high power supply potential unit 21. The source electrode of the transistor 42 is an example of a second main electrode connected to the low power supply potential unit 22 via the intermediate node 51 and the lower arm 46. The same applies to the transistor 43.

  The gate electrodes of the transistors 42 and 43 are connected to the inverter drive circuit 31 and are connected to different pre-drivers. The drain electrodes of the transistors 42 and 43 are connected to each other, and the source electrodes of the transistors 42 and 43 are also connected to each other.

  The gate electrode of the transistor 47 is an example of a control electrode connected to the inverter drive circuit 31 of the control unit 30. The drain electrode of the transistor 47 is an example of a first main electrode connected to the high power supply potential unit 21 via the intermediate node 51 and the upper arm 41. The source electrode of the transistor 47 is an example of a second main electrode connected to the low power supply potential unit 22. The same applies to the transistor 48.

  The gate electrodes of the transistors 47 and 48 are connected to the inverter drive circuit 31 and are connected to different pre-drivers. The drain electrodes of the transistors 47 and 48 are connected to each other, and the source electrodes of the transistors 47 and 48 are also connected to each other.

  The transistor 42 includes a diode 44 for reverse conduction between the drain electrode and the source electrode. The diode 44 is an element that is reversely connected to the transistor 42, and has a cathode connected to the drain electrode of the transistor 42 and an anode connected to the source electrode of the transistor 42. The same applies to the diodes 45, 49, 50.

  Since the configuration of the switching circuit 60 is the same as the configuration of the switching circuit 40, the description of the switching circuit 60 is omitted by using the description of the switching circuit 40.

  The control unit 30 includes an inverter drive circuit 31 and a control circuit 32.

  The inverter drive circuit 31 includes a plurality of pre-drivers that output a control signal for turning on or off each transistor of the inverter circuit 20 to the control electrode of each transistor in accordance with a command signal supplied from the control circuit 32. Each pre-driver of the inverter drive circuit 31 uses each transistor in the inverter circuit 20 as a command signal from the control circuit 32 so that three-phase AC power for driving the motor 12 is supplied from the inverter circuit 20 to the motor 12. A control signal for turning on or off in synchronization is output. The pre-driver is, for example, an IC (integrated circuit).

  The inverter drive circuit 31 turns on or off the upper arm 41 of the switching circuit 40 according to the command signals S13 and S14 from the control circuit 32, and the lower arm 46 of the switching circuit 40 according to the command signals S15 and S16 from the control circuit 32. Turn on or off. The inverter drive circuit 31 turns on or off the upper arm 61 of the switching circuit 60 according to the command signals S33 and S34 from the control circuit 32, and the lower arm 66 of the switching circuit 60 according to the command signals S35 and S36 from the control circuit 32. Turn on or off.

  The drive device 11 includes a detection circuit 52 that detects a phase current I1 flowing in the lower arm 46 disposed between the low power supply potential unit 22 and the intermediate node 51, and a low power supply potential unit 22 and the intermediate node 71. And a detection circuit 72 that detects a phase current I2 flowing through the lower arm 66 disposed. The detection circuit 52 outputs a feedback signal S21 corresponding to the current value of the phase current I1 flowing in the lower arm 46, and the detection circuit 72 outputs a feedback signal S41 corresponding to the current value of the phase current I2 flowing in the lower arm 66. To do. In the drawing, an example of the detection circuits 52 and 72 is shown.

  The detection circuit 52 includes, for example, a shunt resistor 53, a differential amplifier 54, and an AD converter 55. The shunt resistor 53 is inserted in series between the lower arm 46 and the low power supply potential unit 22 and generates a detection voltage corresponding to the current value of the phase current I1. The differential amplifier 54 outputs an analog voltage S22 obtained by differentially amplifying the detection voltage generated by the shunt resistor 53. The AD converter 55 performs AD conversion on the analog voltage S22 and outputs a digital feedback signal S21.

  The detection circuit 72 includes, for example, a shunt resistor 73, a differential amplifier 74, and an AD converter 75. The shunt resistor 73 is inserted in series between the lower arm 66 and the low power supply potential unit 22 and generates a detection voltage corresponding to the current value of the phase current I2. The differential amplifier 74 outputs an analog voltage S42 obtained by differentially amplifying the detection voltage generated by the shunt resistor 73. The AD converter 75 AD converts the analog voltage S42 and outputs a digital feedback signal S41.

  The control circuit 32 includes a drive control unit 33, an interrupt unit 34, and a failure determination unit 37. A specific example of the control circuit 32 is a microcomputer equipped with a CPU. The AD converters 55 and 75 may be a circuit built in the microcomputer or a circuit external to the microcomputer.

  The drive control unit 33 outputs a PWM signal (pulse width modulation signal) for PWM driving each arm based on the feedback signal of the phase current flowing in the lower arm of each switching circuit and the target value of the phase current. Perform feedback control. The drive control unit 33 outputs PWM signals S11, S12, S31, and S32. The PWM signal S11 is a signal for turning on and off the upper arm 41 of the switching circuit 40. The PWM signal S12 is a signal for turning on and off the lower arm 46 of the switching circuit 40. The PWM signal S31 is a signal for turning on and off the upper arm 61 of the switching circuit 60. The PWM signal S32 is a signal for turning on and off the lower arm 66 of the switching circuit 60.

  The interrupt unit 34 gives an interrupt to the inverter drive circuit 31 for temporarily prohibiting the PWM drive of some transistors in the arm during the PWM drive of the arm, so that only the remaining transistors in the arm are PWM driven. Perform interrupt control. The interrupt unit 34 includes an interrupt control unit 35 that performs this interrupt control for each transistor by using an AND gate 36.

  The failure determination unit 37 obtains the expected value of the phase current of each phase determined by the state of each PWM signal output from the drive control unit 33, and the detected value of the phase current of each phase obtained from the feedback signals S21, S41, etc. In comparison, control for determining an open failure of each transistor is performed. When the failure determination unit 37 determines that any of the transistors has an open failure, for example, abnormality information of the transistor determined to be an open failure (for example, diagnostic information or a warning for notifying the user of the occurrence of an open failure) Information).

  FIG. 2 is a flowchart illustrating an example of a failure detection method for the inverter circuit 20. The failure detection method shown in FIG. 2 is executed for each transistor in the inverter circuit 20 by the control circuit 32 (drive control unit 33, interrupt unit 34, and failure determination unit 37). Hereinafter, FIG. 2 will be described with reference to FIG.

  When at least one of the upper arm and the lower arm is PWM-driven by the drive control unit 33 (step S10), the interrupt unit 34 temporarily performs PWM driving of some transistors in the one arm. (Step S20). That is, in step S20, among the plurality of transistors provided in one arm of the interrupt unit 34, another transistor connected in parallel to a part of the transistors for which PWM driving is temporarily stopped is as follows. The PWM drive is continued without temporarily stopping.

  Temporarily, a part of transistors in which PWM driving is temporarily stopped is referred to as “transistor A”, and another transistor connected in parallel to a part of transistors in which PWM driving is temporarily stopped is referred to as “transistor B”. To do. In addition, the other arm provided in the switching circuit in phase with the one arm having the transistor A (in other words, an arm facing the one arm) is referred to as “arm C”. A period in which the PWM drive of the transistor A is temporarily stopped is referred to as “period X”.

  In FIG. 1, for example, when the transistor A is the transistor 42, the transistor B corresponds to the transistor 43, and the arm C corresponds to the lower arm 46. For example, if the transistor A is the transistor 68, the transistor B corresponds to the transistor 67, and the arm C corresponds to the upper arm 61.

  If the transistor B is in a normal state with no open failure, the transistor B is turned on in the period X when a control signal for PWM driving the transistor B is input to the control electrode of the transistor B in the period X. Therefore, in the period X, the transistor A is turned on while the transistor A is turned off. Therefore, the phase current flowing back in the period X flows in the transistor B, but does not flow in the transistor A and the arm C.

  However, if the transistor B is in an abnormal state where an open failure occurs, the transistor B is not turned on even if a control signal for PWM driving the transistor B is input to the control electrode of the transistor B in the period X. Therefore, since both the transistor A and the transistor B are not turned on (turned off) in the period X, the phase current that circulates in the period X does not flow in the transistors A and B but flows in the arm C.

  Therefore, in step S30, failure determination unit 37 detects whether or not the phase current that circulates in period X flows to the other arm (that is, arm C) that faces one arm. When it is detected that the phase current flowing back in the period X flows in the arm C, the failure determination unit 37 opens a transistor (that is, a transistor B) different from the transistor A among the plurality of transistors in one arm. It is determined that a failure has occurred (step S50). On the other hand, when it is detected that the phase current flowing back in the period X does not flow to the arm C, the failure determination unit 37 determines that the transistor B is not in an open failure (step S40).

  Therefore, since the failure detection method shown in FIG. 2 can be realized by a program executed by the control circuit 32 without adding a special element such as a temperature detection sensor, an open failure of each transistor connected in parallel can be realized. The configuration to be detected can be simplified.

  FIG. 3 is a diagram for explaining an example of a failure detection method of the inverter circuit 20 when detecting an open failure of the transistor 43 disposed in the upper arm 41 of the switching circuit 40. FIG. 4 is a timing chart showing an example of each waveform when the transistor 43 does not have an open failure. FIG. 5 is a timing chart showing an example of each waveform when the transistor 43 has an open failure. Hereinafter, FIG. 3 will be described with reference to FIGS.

  4 and 5, when the command signal S14 is at a high level (H), a high-level control signal for turning on the transistor 43 is input to the control electrode of the transistor 43. When the command signal S14 is at a low level (L), a low level control signal for turning off the transistor 43 is input to the control electrode of the transistor 43. Similarly, when the command signal S13 is at a high level (H), a high level control signal for turning on the transistor 42 is input to the control electrode of the transistor 42. When the command signal S13 is at the low level (L), a low level control signal for turning off the transistor 42 is input to the control electrode of the transistor 42.

  4 and 5, the phase current I <b> 2 is a current that flows back to the lower arm 66 of the switching circuit 60. The positive (+) phase current I2 indicates that the current flows back from the intermediate node 71 to the low power supply potential unit 22 via the lower arm 66 and the detection circuit 72. When the phase current I2 is zero (0), it indicates that the phase current I2 does not flow through the lower arm 66.

  4 and 5, the phase current I <b> 1 is a current that flows back to the lower arm 46 of the switching circuit 40. The negative (−) phase current I1 indicates that the low power supply potential unit 22 is flowing back in the direction of flowing to the intermediate node 51 via the detection circuit 52 and the lower arm 46. When the phase current I1 is zero (0), it indicates that the phase current I1 does not flow through the lower arm 46.

  In FIG. 3, during the PWM drive of the upper arm 41, the transistor 42 and the transistor 43 are turned on and off at the same timing. During the PWM drive of the upper arm 41, the interrupt control unit 35 temporarily inputs the low-level interrupt signal S17 to the AND gate 36 to which the PWM signal S11 is input while the interrupt signal S18 is fixed at the high level. To do.

  As a result, the level of the command signal S14 repeats the high level and the low level at the same timing as the PWM signal S11, while the level of the command signal S13 is temporarily fixed to the low level (see FIGS. 4 and 5). (See period t3-t4). The period t3-t4 is an example of the period X described above.

  If the transistor 43 is in a normal state with no open failure, the transistor 43 is turned on by the high-level command signal S14 during a period t3-t4 in which the transistor 42 is temporarily turned off by the low-level command signal S13. . Therefore, in the period t3 to t4, the transistor 43 is turned on while the transistor 42 is turned off. Therefore, the phase current that circulates in the period t3-t4 flows through the path 81 (see FIG. 3) from the high power supply potential unit 21 through the transistor 43 to the intermediate node 51, and then the motor 12 and the on-state transistor 67. , 68 to the low power supply potential unit 22. However, the phase current that circulates in the period t3 to t4 does not flow through the transistor 42 and the lower arm 46. Therefore, the phase current I2 is detected by the detection circuit 72 in the period t3-t4, but the phase current I1 is not detected by the detection circuit 52 in the period t3-t4 (see FIG. 4).

  On the other hand, if the transistor 43 is in an abnormal state where an open failure occurs, the command signal S14 changes from the low level to the high level during the period t3-t4 when the transistor 42 is temporarily turned off by the low level command signal S13. Even after the transition, the transistor 43 is not turned on. Therefore, both the transistor 42 and the transistor 43 are off in the period t3-t4. Therefore, the phase current that circulates in the period t3-t4 flows through the path 82 (see FIG. 3) from the low power supply potential unit 22 through the diodes 49 and 50 to the intermediate node 51, and then the motor 12 and the on-state are turned on. It flows through the transistors 67 and 68 to the low power supply potential unit 22. The phase current that circulates in the period t3 to t4 does not flow in the transistors 42 and 43. Therefore, the phase current I2 is detected by the detection circuit 72 in the period t3-t4, and the phase current I1 is also detected by the detection circuit 52 in the period t3-t4 (see FIG. 5).

  Therefore, the failure determination unit 37 determines that the transistor 43 has an open failure when the detection circuit 52 detects that the phase current flowing back in the period t3 to t4 flows to the lower arm 46. On the other hand, the failure determination unit 37 determines that the transistor 43 does not have an open failure when the detection circuit 52 does not detect that the phase current flowing back in the period t3 to t4 flows to the lower arm 46.

  FIG. 6 is a diagram for explaining an example of a failure detection method of the inverter circuit 20 when detecting an open failure of the transistor 68 arranged in the lower arm 66 of the switching circuit 60. FIG. 7 is a timing chart showing an example of each waveform when the transistor 68 does not have an open failure. FIG. 8 is a timing chart showing an example of each waveform when the transistor 68 has an open failure. Hereinafter, FIG. 6 will be described with reference to FIGS.

  7 and 8, when the command signal S36 is at a high level (H), a high level control signal for turning on the transistor 68 is input to the control electrode of the transistor 68. When the command signal S36 is at a low level (L), a low level control signal for turning off the transistor 68 is input to the control electrode of the transistor 68. Similarly, when the command signal S35 is at a high level (H), a high-level control signal for turning on the transistor 67 is input to the control electrode of the transistor 67. When the command signal S35 is at a low level (L), a low level control signal for turning off the transistor 67 is input to the control electrode of the transistor 67.

  7 and 8, the phase current I <b> 2 is a current that flows back to the lower arm 66 of the switching circuit 60. The positive (+) phase current I2 indicates that the current flows back from the intermediate node 71 to the low power supply potential unit 22 via the lower arm 66 and the detection circuit 72. When the phase current I2 is zero (0), it indicates that the phase current I2 does not flow through the lower arm 66.

  7 and 8, the phase current I <b> 1 is a current that flows back to the lower arm 46 of the switching circuit 40. The negative (−) phase current I1 indicates that the low power supply potential unit 22 is flowing back in the direction of flowing to the intermediate node 51 via the detection circuit 52 and the lower arm 46. When the phase current I1 is zero (0), it indicates that the phase current I1 does not flow through the lower arm 46.

  In FIG. 6, during PWM driving of the lower arm 66, the transistor 67 and the transistor 68 are turned on and off at the same timing. During the PWM drive of the lower arm 66, the interrupt control unit 35 temporarily inputs the low level interrupt signal S39 to the AND gate 36 to which the PWM signal S32 is input in a state where the interrupt signal S40 is fixed at the high level. To do.

  As a result, the level of the command signal S36 repeats the high level and the low level at the same timing as the PWM signal S32, while the level of the command signal S35 is temporarily fixed to the low level (see FIGS. 7 and 8). (See period t3-t4). The period t3-t4 is an example of the period X described above.

  If the transistor 68 is in a normal state with no open failure, the transistor 68 is turned on by the high level command signal S36 during the period t3-t4 in which the transistor 67 is temporarily turned off by the low level command signal S35. . Therefore, in the period t3-t4, the transistor 68 is turned on while the transistor 67 is turned off. Therefore, the phase current that circulates in the period t3 to t4 flows from the high power supply potential unit 21 to the motor 12 through the transistors 42 and 43 and the intermediate node 51 that are in the on state, and then from the intermediate node 71 to the transistor 68. Then, it flows through a path 83 (see FIG. 6) that reaches the low power supply potential unit 22. However, the phase current that circulates in the period t3 to t4 does not flow through the transistor 67 and the upper arm 61. Therefore, the phase current I2 is detected by the detection circuit 72 in the period t3-t4, but the phase current I1 is not detected by the detection circuit 52 in the period t3-t4 (see FIG. 7).

  On the other hand, if the transistor 68 is in an abnormal state where an open failure occurs, the command signal S36 changes from the low level to the high level during the period t3-t4 when the transistor 67 is temporarily turned off by the low level command signal S35. Even after the transition, the transistor 68 is not turned on. Therefore, both the transistor 67 and the transistor 68 are off during the period t3-t4. Therefore, the phase current that circulates in the period t3 to t4 flows from the high power supply potential unit 21 to the motor 12 through the transistors 42 and 43 that are turned on and the intermediate node 51, and then from the intermediate node 71 to the diodes 64 and 65. It flows through a path 84 (see FIG. 6) that reaches the high power supply potential section 21 via the. The phase current that circulates in the period t3 to t4 does not flow through the transistors 67 and 68. Therefore, the phase current I2 is not detected by the detection circuit 72 in the period t3-t4, and the phase current I1 is not detected by the detection circuit 52 in the period t3-t4 (see FIG. 8).

  Therefore, the failure determination unit 37 detects that the phase current flowing back in the period t3-t4 does not flow through the lower arm 66 by the detection circuit 72 (or the phase current flowing back in the period t3-t4 flows through the lower arm 66). If it is detected by the detection circuit 72), it is determined that the transistor 68 has an open failure. That is, in the failure determination unit 37, when the detection circuit 72 does not detect that the phase current flowing back in the period t3-t4 flows in the lower arm 66 (or the phase current flowing back in the period t3-t4 flows in the lower arm 66. When it is detected by the detection circuit 72), it is estimated that the phase current flowing back in the period t3-t4 flows in the upper arm 61, and it is determined that the transistor 68 has an open failure. On the other hand, when the detection circuit 72 detects that the phase current flowing back in the period t3-t4 flows to the lower arm 66, the failure determination unit 37 determines that the transistor 68 does not have an open failure.

  Even if the detection target of the open fault is a transistor different from that in FIGS. 3 and 6, it can be considered in the same manner as in FIGS. The control circuit 32 may perform the above-described failure detection method repeatedly for each transistor in the inverter detection circuit 20.

  Although the inverter circuit failure detection method, the drive device, and the motor drive system have been described in the above, the present invention is not limited to the above embodiment. Various modifications and improvements such as combinations and substitutions with some or all of the other embodiments are possible within the scope of the present invention.

  For example, the switching element is not limited to a MOS transistor or an IGBT but may be a bipolar transistor.

  For example, the number of switching elements connected in parallel is not limited to two, and may be three or more. For example, in the case of an arm in which three transistors are connected in parallel, when the control circuit 32 detects that a current flowing back in the period C when the driving of one transistor A is stopped flows to the arm C, It is determined that the remaining two transistors B connected to the transistor A have an open failure. For example, in the case of an arm in which three transistors are connected in parallel, the control circuit 32 detects that a current flowing back in the period C when the driving of the two transistors A is stopped flows in the arm C. It is determined that the remaining one transistor B connected to one transistor A has an open failure.

  Further, the detection circuit for detecting the current flowing through the lower arm is not limited to the configuration for detecting the current using the shunt resistor. For example, the detection circuit for detecting the current flowing through the lower arm is configured to detect the current using a sense transistor connected in parallel to the lower arm transistor and a sense diode connected in parallel to the lower arm diode. It may be.

DESCRIPTION OF SYMBOLS 1 Motor drive system 11 Drive apparatus 12 Motor 20 Inverter circuit 21 High power supply potential part 22 Low power supply potential part 30 Control part 31 Inverter drive circuit 32 Control circuit 33 Drive control part 34 Interrupt part 35 Interrupt control part 36 AND gate 37 Failure determination Portions 40, 60 Switching circuits 41, 61 Upper arms 42, 43, 47, 48, 62, 63, 67, 68 Transistors 44, 45, 49, 50, 64, 65, 69, 70 Diodes 46, 66 Lower arm 51, 71 Intermediate node 52, 72 Detection circuit 53, 73 Shunt resistor 54, 74 Differential amplifier 55, 75 AD converter 81, 82, 83, 84 path

Claims (5)

A fault detection method for an inverter circuit having a plurality of switching elements provided in parallel in which a plurality of switching elements connected in parallel are provided in each of an upper arm and a lower arm, and the upper arm and the lower arm are connected in series Because
During driving of either the upper arm or the lower arm, driving of some of the switching elements provided in the one arm is stopped,
When it is detected that a current that circulates during the period when the driving of some of the switching elements is stopped flows to the other arm provided in the switching circuit in phase with the one arm, A fault detection method for an inverter circuit, wherein a switching element different from the part of the plurality of switching elements provided is determined to have an open fault. When it is detected that a current returning to the lower arm flows while the driving of the part of the switching elements provided in the upper arm is stopped, the other switching provided in the upper arm. Determine that the element has an open failure,
When it is detected that a current that circulates while the drive of the part of the switching elements provided in the lower arm is stopped does not flow into the lower arm, the other switching element provided in the lower arm The inverter circuit failure detection method according to claim 1, wherein the switching element is determined to have an open failure. A plurality of switching elements connected in parallel are provided in each of the upper arm and the lower arm, an inverter circuit having a plurality of switching circuits provided by connecting the upper arm and the lower arm in series,
A controller that stops driving of some of the plurality of switching elements provided in the one arm during driving of either the upper arm or the lower arm; and
When the control unit detects that a current that circulates in a period in which driving of some of the switching elements is stopped flows to the other arm provided in the switching circuit in phase with the one arm, The drive apparatus which determines with the switching element different from the said one part switching element among the some switching elements provided in the said one arm having an open failure. A detection circuit for detecting a current flowing through the lower arm;
The controller is
Provided in the upper arm when the detection circuit detects that a current that circulates in the period when driving of the part of the switching elements provided in the upper arm is stopped flows to the lower arm Determining that the other switching element has an open failure;
When the detection circuit does not detect that the current flowing back in the period when the driving of the part of the switching elements provided in the lower arm is stopped, the detection circuit detects the current provided in the lower arm. The drive device according to claim 3, wherein it is determined that another switching element has an open failure.   A motor drive system comprising the drive device according to claim 3 and a motor driven by the drive device.

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