CN111458953A - Optical analog-to-digital conversion architecture based on photon parallel sampling and implementation method thereof - Google Patents
Optical analog-to-digital conversion architecture based on photon parallel sampling and implementation method thereof Download PDFInfo
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Abstract
An optical modulus conversion framework based on photon parallel sampling is based on a photonics technology, an optical sampling clock with repetition frequency fs is decomposed into N paths, each path of relative delay is controlled to be 1/(fs x N), then the N paths of optical sampling clocks with equal time intervals are respectively input into N identical photon sampling gates, photon parallel sampling is completed, and optical modulus conversion of the same sampled signal source with actual total sampling rate of N fs is achieved. The framework can realize an optical analog-to-digital conversion system with high sampling rate based on a low-speed optical sampling clock, and the design requirement on the optical sampling clock is reduced. Meanwhile, the complexity of a demultiplexing module in the system is simplified, and the optical path loss can be effectively reduced. The architecture is expected to become a solution of a next-generation high-speed high-precision on-chip optical analog-to-digital conversion system.
Description
Technical Field
The invention relates to photon information processing, in particular to an optical analog-to-digital conversion framework based on photon parallel sampling and an implementation method thereof.
Background
In the information age, data transmission, processing and analysis are ubiquitous and permeate in aspects of life, military, scientific research and the like. However, the signals of nature are in analog continuous form, so the analog-to-digital converter becomes a bridge connecting the analog world and the digital world. In order to meet the requirements of people on mass data and the requirements of various fields on the quality of acquired information in the information explosion era, the analog-to-digital converter is inevitably developed to higher speed and higher precision. However, at present, three key indexes of input bandwidth, sampling rate and quantization precision of an analog-to-digital converter based on an electronic technology are all close to physical limits, and further improvement on an original framework is difficult to realize.
Since the introduction of optical analog-to-digital conversion technology, the advantages of large bandwidth and low jitter of photonics have been rapidly developed. Researchers originally put forward a scheme for realizing all-optical analog-to-digital conversion based on an electro-optical modulator with multiple half-wave voltages multiplied in sequence, the quantization precision of the scheme is always limited by the electrode length of the electro-optical modulator, and the quantization digit is difficult to break through four digits, so the practical value is not high. The scheme of combining the photon sampling front end with the rear end of the traditional electronic analog-to-digital converter is adopted, and the continuous improvement of the performance of the optoelectronic device and the gradual maturity of the integration technology lead to the great development and advance to the practicability. In the scheme, an optical pulse generated by a mode-locked laser serves as an optical sampling clock, an electro-optical modulator serves as a photon sampling gate, a sampled optical pulse sequence is decomposed into a plurality of channels through a demultiplexing module, the optical pulse sequence with the reduced repetition frequency in each channel is converted into an electric signal through a photoelectric detector in the channel, and digital quantization and encoding are completed through an electronic analog-to-digital converter at the rear end. However, the current solution of using a photonic sampling front-end in combination with a conventional electronic analog-to-digital converter back-end faces a series of problems in further scaling and miniaturization, including: when the large-scale expansion is carried out, the link loss caused by the fact that the demultiplexing module is larger and larger is increased sharply, the sampling rate is further improved due to the limited cavity length of the mode-locked laser, the performance stability of an optical sampling clock generated by the mode-locked laser is reduced along with the improvement of the sampling rate, an internal single component and a framework need to be redesigned aiming at optical analog-to-digital conversion systems with different sampling rates and channel numbers in the miniaturization design, the development period of the on-chip optical analog-to-digital conversion system is prolonged, and meanwhile the accuracy of the on-chip system design cannot be guaranteed.
The researchers have implemented two-channel optical analog-to-digital conversion chips based on the principle of time-wavelength interleaving using silicon-based optoelectronics ("optical express. vol.20, No.4,4454. 4469, 2012"), and also have implemented multi-channel optical analog-to-digital conversion systems based on an optical switch array of multiple Modulator cascades [ L. Yu, et al, Switching architecture of light-output mac-Zehnder Modulator-in channel-interleaved optical analog-to-digital converter, No. L, optical circuits 6316, and the high-speed optical analog-to-digital converter system has been developed, and the high-speed optical analog-to-digital conversion system has been greatly required to implement the high-speed optical analog-to-digital conversion system based on the high-speed optical wavelength interleaving principle.
Disclosure of Invention
The invention aims to provide an optical analog-to-digital conversion framework based on photon parallel sampling and an implementation method thereof aiming at the defects of the prior art. The framework is based on the photonic technology, the optical sampling clock with the repetition frequency of fs is decomposed into N paths, the relative delay of each path is controlled to be 1/(fs x N), then the N paths of optical sampling clocks with equal time intervals are respectively input into N identical photon sampling gates, photon parallel sampling is completed, and optical modulus conversion with the actual total sampling rate of N x fs for the same sampled signal source is realized. The framework can realize an optical analog-to-digital conversion system with high sampling rate based on a low-speed optical sampling clock, and the design requirement on the optical sampling clock is reduced. Meanwhile, the complexity of a demultiplexing module in the system is simplified, and the optical path loss can be effectively reduced. The architecture is expected to become a solution of a next-generation high-speed high-precision on-chip optical analog-to-digital conversion system. The technical scheme of the invention is as follows:
an optical analog-digital conversion architecture based on photon parallel sampling is characterized by comprising an optical sampling clock source, N paths of optical equal division modules, a delay line array, a sampled signal source, a photon sampling gate array, a demultiplexer array, a photoelectric detector array, an electronic analog-digital converter array and a data integration and processing module, wherein the delay line array is composed of N delay line units, the photon sampling gate array is formed by paralleling N same photon sampling gate units, the demultiplexer array is formed by paralleling N demultiplexer units, the photoelectric detector array is formed by paralleling N m PD units, and the electronic analog-digital converter array is formed by paralleling N × m electronic analog-digital converters. The output end of the optical sampling clock source is connected with the input end of the N paths of optical equal division modules, the N output ends of the N paths of optical equal division modules are respectively connected with the input ends of the N delay line units in the delay line array, the N output ends of the sampled signal source are respectively connected with the first input ends of the N photon sampling gate units in the photon sampling gate array, the output ends of the N delay line units are respectively connected with the second input ends of the N photon sampling gate units in the photon sampling gate array, the output ends of the N photon sampling gate units in the photon sampling gate array are respectively connected with the input ends of the N demultiplexer units in the demultiplexer array, the N demultiplexer units all have m output ends, and the m output ends of the N demultiplexer units are respectively connected with the input ends of the N + m PD units in the photoelectric detector array, the output ends of the N × m PD units in the photodetector array are respectively connected to the input ends of the N × m electronic analog-to-digital converters in the electronic analog-to-digital converter array, the output ends of the N × m electronic analog-to-digital converters in the electronic analog-to-digital converter array are respectively connected to the N × m input ends of the data integration and processing module, where N is a positive integer greater than or equal to 2, m is a positive integer greater than or equal to 1, and when m is equal to 1, the demultiplexer unit is a single-ended output optical fiber connector or a waveguide connector.
The optical sampling clock source is used as the optical sampling clock of the optical analog-to-digital conversion system, and can be realized by methods such as but not limited to a passive mode-locked laser, an active mode-locked laser or a modulation frequency comb.
The N paths of light equal division modules are used for equally dividing the light sampling clock output by the light sampling clock source into N parts, and an optical coupler or an array waveguide grating can be adopted, wherein N is a positive integer greater than or equal to 2.
The delay line unit is used for generating determined delay amount, and an optical fiber with determined length or an adjustable delay line can be adopted.
The sampled signal source is an electric analog signal generated by a voltage-controlled oscillator, a frequency synthesis source, an analog signal generator or an arbitrary waveform generator and the like.
The photon sampling gate unit realizes the sampling of the electric analog signal by utilizing a large-bandwidth modulator, the output of the photon sampling gate unit is an optical pulse sequence carrying the electric analog signal information, and the photon sampling gate unit can adopt a lithium niobate electro-optical modulator, a polymer electro-optical modulator, a silicon-based integrated electro-optical modulator, an acousto-optic modulator or a spatial light modulator.
The demultiplexer unit is used for decomposing an optical pulse sequence carrying electrical analog signal information into m paths of optical pulse sequences, and can adopt an optical switch array or a wavelength division multiplexer, wherein m is a positive integer greater than or equal to 1, and when m is equal to 1, the demultiplexer unit is a single-ended output optical fiber connector or a waveguide connector.
The PD unit is used for converting optical signals into electric signals and can adopt PIN tubes or APD tubes.
The electronic analog-to-digital converter is used for quantizing and coding the electric signals and can adopt an oscilloscope, an ADC chip or a signal development board.
The data integration and processing module is used for data reconstruction, interweaving and processing of the electric digital signals and can adopt a computer, a single chip microcomputer, an information processing board card and the like.
The method for realizing the optical analog-to-digital conversion architecture based on photon parallel sampling comprises the following steps:
1) an optical sampling clock source generates an optical sampling clock signal with a repetition frequency of fs, the optical sampling clock signal is input into an N-path optical equally dividing module, the N-path optical equally dividing module generates N paths of identical optical sampling clock signals, the optical sampling clock signals are respectively input into N delay line units in the delay line array, the N delay line units in the delay line array control each path of relative delay to be 1/(fs x N), the delay amount generated by the nth delay line unit is (N-1)/(fs x N), so that N paths of optical sampling clocks with equal time intervals are obtained, the time interval of two adjacent paths is 1/(fs x N), and N is 1, 2, 3 … … N;
2) n paths of output ends of a sampled signal source generate N paths of completely same electric analog signals and respectively input the electric analog signals to the N photon sampling gate units, parallel sampling at equal time intervals is realized by N paths of optical sampling clocks at equal time intervals, N paths of optical pulse sequences carrying electric analog signal information are respectively decomposed into m paths of demultiplexing optical pulse sequences in each path by a demultiplexer unit, and therefore N x m paths of demultiplexing optical pulse sequences are obtained in total;
3) and the N × m demultiplexing optical pulse sequences are subjected to photoelectric conversion by N × m PD units respectively to obtain N × m electric signals, the N × m electric signals are subjected to N × m electronic analog-to-digital converters to obtain N × m electric digital signals, the N × m electric digital signals are input into the data integration and processing module, and the data integration and processing module performs data reconstruction, interleaving and processing on the received N × m electric digital signals to obtain the information of the original electric analog signals.
Compared with the prior art, the invention has the following advantages:
1. by carrying out N-path equal division and equal time interval delay distribution on the optical sampling clock with the original repetition frequency fs, the optical modulus conversion with the actual total sampling rate of N & ltfs & gt of the same sampled signal source can be realized. The framework can realize an optical analog-to-digital conversion system with high sampling rate based on a low-speed optical sampling clock, and the design requirement on the optical sampling clock is reduced.
2. The complexity of a demultiplexer in the original optical analog-digital conversion system can be reduced, the optical path loss introduced by the demultiplexer can be reduced, and the performance of the optical analog-digital conversion system is greatly improved.
3. The advantages of fine and controllable photon time domain delay are utilized, the complex frequency division and phase shift circuits in the traditional electronic analog-to-digital conversion technology are avoided, the precision limit of clock distribution in the traditional electronic analog-to-digital conversion technology can be broken through, and therefore the conversion precision of the optical analog-to-digital conversion system is guaranteed.
4. The optical analog-to-digital conversion system with different total sampling rates and different channel numbers can be realized by equally dividing and delaying the same optical sampling clock by different channel numbers, the development process for realizing the optical analog-to-digital conversion system with different indexes is simplified, and a reliable technical scheme can be provided for realizing the optical analog-to-digital conversion system on a chip with a high sampling rate in the future.
Drawings
FIG. 1 is a general architecture diagram of an embodiment of an optical analog-to-digital conversion architecture based on photon parallel sampling according to the present invention;
fig. 2(a) is a schematic diagram of N paths of optical sampling clocks distributed with equal time interval delay through N paths of equal divisions; fig. 2(b) is a schematic diagram of the N optical pulse sequences obtained after the same electrical analog signal is simultaneously sampled by the N optical sampling clocks with equal time intervals; fig. 2(c) is a schematic diagram of N optical pulse sequences being decomposed into N × m optical pulse sequences by the demultiplexer unit in each optical path; fig. 2(d) is a schematic diagram of the interleaved signal reconstructed by the data integration and processing module from the N × m electronic analog-to-digital converters.
Detailed Description
An embodiment of the present invention is given below with reference to the accompanying drawings. The present embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a process are given, but the scope of the present invention is not limited to the following embodiments.
Referring to fig. 1, fig. 1 is an overall architecture diagram of an optical analog-to-digital conversion architecture embodiment based on photon parallel sampling, and it can be seen from the figure that the optical analog-to-digital conversion architecture based on photon parallel sampling of the present invention includes an optical sampling clock source 1, an N-way optical equal division module 2, a delay line array 3, a sampled signal source 4, a photon sampling gate array 5, a demultiplexer array 6, a photodetector array 7, an electronic analog-to-digital converter array 8, and a data integration and processing module 9, where the delay line array 3 is composed of N delay line units 3-1, the photon sampling gate array 5 is composed of N identical photon sampling gate units 5-1 in parallel, the demultiplexer array 6 is composed of N demultiplexer units 6-1 in parallel, the photodetector array 7 is composed of N × m PD units 7-1 in parallel, the electronic analog-to-digital converter array 8 is formed by connecting N m electronic analog-to-digital converters 8-1 in parallel. The output end of the optical sampling clock source 1 is connected with the input end of the N paths of optical equal division modules 2, N output ends of the N paths of optical equal division modules 2 are respectively connected with the input ends of N delay line units 3-1 in the delay line array 3, N output ends of the sampled signal source 4 are respectively connected with first input ends of N photon sampling gate units 5-1 in the photon sampling gate array 5, output ends of the N delay line units 3-1 are respectively connected with second input ends of N photon sampling gate units 5-1 in the photon sampling gate array 5, output ends of N photon sampling gate units 5-1 in the photon sampling gate array 5 are respectively connected with input ends of N demultiplexer units 6-1 in the demultiplexer array 6, the N demultiplexer units 6-1 each have m output terminals, the m output terminals of the N demultiplexer units 6-1 are respectively connected to the input terminals of the N × m PD units 7-1 in the photodetector array 7, the output ends of the N x m PD units 7-1 in the photodetector array 7 are respectively connected to the input ends of the N x m electronic analog-to-digital converters 8-1 in the electronic analog-to-digital converter array 8, the output ends of the N x m electronic analog-to-digital converters 8-1 in the electronic analog-to-digital converter array 8 are respectively connected with the N x m input ends of the data integration and processing module 9, wherein N is a positive integer of 2 or more, m is a positive integer of 1 or more, and when m is 1 or more, the demultiplexer unit 6-1 is a single-ended output optical fiber connector or a waveguide connector.
The method for realizing the optical analog-to-digital conversion architecture based on photon parallel sampling comprises the following steps:
1) the optical sampling clock source 1 generates an optical sampling clock signal with a repetition frequency fs and inputs the optical sampling clock signal into the N optical equally dividing module 2, the N optical equally dividing module 2 generates N identical optical sampling clock signals and respectively inputs the optical sampling clock signals into N delay line units 3-1 in the delay line array 3, the N delay line units 3-1 in the delay line array 3 control each path of relative delay to be 1/(fs × N), wherein a delay amount generated by an nth delay line unit is (N-1)/(fs × N), so that the optical sampling clock with N paths of equal time intervals shown in fig. 2(a) is obtained, a time interval of two adjacent paths is 1/(fs × N), wherein N is 1, 2, 3 … … N, and Ts is 1/fs;
2) n output ends of the sampled signal source 4 generate N identical electrical analog signals and respectively input the electrical analog signals to the N photon sampling gate units 5-1, and N optical sampling clocks with equal time intervals are used for realizing parallel sampling with equal time intervals, for example, N optical pulse sequences carrying electrical analog signal information shown in fig. 2(b) are respectively decomposed into m demultiplexing optical pulse sequences in each path by the demultiplexer unit 6-1, so that N × m demultiplexing optical pulse sequences are obtained in total, as shown in fig. 2 (c);
3) the obtained N × m demultiplexed optical pulse sequences are photoelectrically converted by the N × m PD units 7-1 to obtain N × m electrical signals, the N × m electrical signals are further processed by the N × m electronic analog-to-digital converters 8-1 to obtain N × m electrical digital signals, the N × m electrical digital signals are input to the data integration and processing module 9, and the data integration and processing module 9 performs data reconstruction and interleaving on the received N × m electrical digital signals and processes the electrical digital signals to obtain information of the original electrical analog signals, as shown in fig. 2(d), in this embodiment, N is 2, m is 2.
In the process, the optical sampling clock with the original repetition frequency fs is subjected to N-path equal division and equal time interval delay distribution to finish photon parallel sampling, so that the optical modulus conversion of the same sampled signal source with the actual total sampling rate of N x fs is realized. Experiments show that the optical sampling clock can realize optical analog-to-digital conversion with high sampling rate based on the low-speed optical sampling clock, and the design requirement on the optical sampling clock is reduced. Meanwhile, the complexity of a demultiplexer in the original optical analog-digital conversion system can be reduced, the optical path loss introduced by the demultiplexer is further reduced, and the performance of the optical analog-digital conversion system is greatly improved. The optical analog-digital conversion architecture based on photon parallel sampling simplifies the architecture development process for realizing optical analog-digital conversion systems with different indexes, and can provide a reliable technical scheme for realizing an on-chip optical analog-digital conversion system with a high sampling rate in the future.
Claims (11)
1. An optical analog-digital conversion architecture based on photon parallel sampling comprises an optical sampling clock source (1), an N-path optical equal division module (2), a delay line array (3), a sampled signal source (4), a photon sampling gate array (5), a demultiplexer array (6), a photoelectric detector array (7), an electronic analog-digital converter array (8) and a data integration and processing module (9), it is characterized in that the delay line array (3) is composed of N delay line units (3-1), the photon sampling gate array (5) is composed of N photon sampling gate units (5-1), the demultiplexer array (6) is composed of N demultiplexer units (6-1), the photodetector array (7) is composed of N x m PD units (7-1), the electronic analog-to-digital converter array (8) is composed of N m electronic analog-to-digital converters (8-1);
the output end of the optical sampling clock source (1) is connected with the input end of the N paths of optical equal division modules (2), N output ends of the N paths of optical equal division modules (2) are respectively connected with the input ends of N delay line units (3-1) in the delay line array (3), the output ends of the N delay line units (3-1) are respectively connected with the second input ends of N photon sampling gate units (5-1) in the photon sampling gate array (5), and the first input ends of the N photon sampling gate units (5-1) in the photon sampling gate array (5) are respectively connected with N paths of output ends of the sampled signal source (4);
the output ends of the N photon sampling gate units (5-1) are respectively connected with the input ends of N demultiplexer units (6-1) in the demultiplexer array (6), the N demultiplexer units (6-1) are respectively provided with m output ends, the m output ends of the N demultiplexer units (6-1) are respectively connected with the input ends of N × m PD units (7-1), the output ends of N × m PD units (7-1) in the photoelectric detector array (7) are respectively connected with the input ends of N × m electronic analog-to-digital converters (8-1) in the electronic analog-to-digital converter array (8), the output ends of N × m electronic analog-to-digital converters (8-1) in the electronic analog-to-digital converter array (8) are respectively connected with N × m input ends of the data integration and processing module (9), wherein N is a positive integer greater than or equal to 2, and m is a positive integer greater than or equal to 1.
2. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, characterized in that the optical sampling clock source (1) is a passive mode-locked laser, an active mode-locked laser or a modulation frequency comb.
3. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, wherein the N-path optical splitting module (2) is an optical coupler or an arrayed waveguide grating, where N is a positive integer greater than or equal to 2.
4. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, characterized in that the delay line unit (3-1) adopts a fiber with a determined length or an adjustable delay line.
5. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, characterized in that the sampled signal source (4) employs a voltage controlled oscillator, a frequency synthesizer source, an analog signal generator or an arbitrary waveform generator.
6. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, wherein the photon sampling gate unit (5-1) adopts a lithium niobate electro-optical modulator, a polymer electro-optical modulator, a silicon-based integrated electro-optical modulator, an acousto-optic modulator or a spatial light modulator.
7. The architecture of claim 1, wherein the demultiplexer unit (6-1) has m outputs, and is implemented by using an optical switch array or a wavelength division multiplexer, where m is a positive integer greater than or equal to 1, and when m is 1, the demultiplexer unit is a single-ended output optical fiber connector or a waveguide connector.
8. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, characterized in that the PD unit (7-1) adopts a PIN tube or an APD tube.
9. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, characterized in that the electronic analog-to-digital converter (8-1) adopts an oscilloscope, an ADC chip or a signal development board.
10. The optical analog-to-digital conversion architecture based on photon parallel sampling according to claim 1, wherein the data integration and processing module (9) can be a computer, a single chip, an information processing board, or the like.
11. A method for implementing an optical analog-to-digital conversion architecture based on photon parallel sampling according to any of claims 1 to 10, characterized in that it comprises the following steps:
1) an optical sampling clock source (1) generates an optical sampling clock signal with a repetition frequency of fs and inputs the optical sampling clock signal into an N-path optical equally dividing module (2), the N-path optical equally dividing module (2) generates N paths of same optical sampling clock signals and respectively inputs the optical sampling clock signals into N delay line units (3-1) in the delay line array (3), each delay line unit (3-1) controls the relative delay of each path to be 1/(fs x N), wherein the delay amount generated by the nth delay line unit is (N-1)/(fs x N), so that N paths of optical sampling clocks with equal time intervals are obtained, the time interval of two adjacent paths is 1/(fs x N), and N1, 2 and 3 … … N;
2) n paths of completely same electric analog signals are generated by N paths of output ends of a sampled signal source (4) and are respectively input into N photon sampling gate units (5-1), after parallel sampling at equal time intervals is realized by N paths of optical sampling clocks at equal time intervals, each optical pulse sequence carrying electric analog signal information is decomposed into m paths of demultiplexing optical pulse sequences by each demultiplexer unit (6-1), and therefore N x m paths of demultiplexing optical pulse sequences are obtained;
3) the N x m demultiplexing optical pulse sequences are respectively subjected to photoelectric conversion by N x m PD units (7-1) to obtain N x m electric signals, the N x m electric signals are respectively converted into N x m electric digital signals by N x m electronic analog-to-digital converters (8-1), and then the N x m electric digital signals are input into a data integration and processing module (9), and the data integration and processing module (9) performs data reconstruction and interleaving on the received N x m electric digital signals and processes the N x m electric digital signals to obtain original electric analog signal information.
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Application publication date: 20200728 |