CN111446956A - Differential sampling circuit - Google Patents
Differential sampling circuit Download PDFInfo
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- CN111446956A CN111446956A CN202010417418.8A CN202010417418A CN111446956A CN 111446956 A CN111446956 A CN 111446956A CN 202010417418 A CN202010417418 A CN 202010417418A CN 111446956 A CN111446956 A CN 111446956A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
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Abstract
The present invention provides a differential sampling circuit, comprising: the input circuit comprises a first subtractor, a first input circuit and a second input circuit which is connected with the first input circuit in parallel; the first input loop includes: the first voltage limiting and shunting unit is connected with a first subtracter through the first filtering unit, and a first sampling point is arranged between the first filtering unit and the first subtracter; the second input loop includes: the second voltage limiting and shunting unit is connected with the first subtracter through the second filtering unit, and a second sampling point is arranged between the second filtering unit and the first subtracter; the output end of the first subtracter outputs a voltage difference value between the first sampling point and the second sampling point. The circuit is based on the subtracter, the first input loop and the second input loop, and the voltage difference value between sampling points is acquired by feeding back four-point resistance voltages.
Description
Technical Field
The invention relates to the technical field of voltage sampling, in particular to a differential sampling circuit.
Background
Currently, in a working circuit of an electronic device or the like, it is necessary to realize functions such as ac voltage sampling and dc voltage sampling. In order to meet the above requirements, the existing voltage sampling circuit mainly depends on a sensor to realize voltage sampling. However, the sampling method is complicated in circuit structure due to the dependence on the sensor, is not convenient for debugging of the circuit, and has high cost. Therefore, it is necessary to provide a further solution to the above problems.
Disclosure of Invention
The present invention is directed to a differential sampling circuit to overcome the deficiencies of the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a differential sampling circuit, comprising: the input circuit comprises a first subtractor, a first input circuit and a second input circuit which is connected with the first input circuit in parallel;
the first input loop comprises: the first voltage limiting and shunting unit is connected with the first subtracter through the first filtering unit, and a first sampling point is arranged between the first filtering unit and the first subtracter;
the second input circuit includes: the second voltage limiting and shunting unit is connected with the first subtracter through the second filtering unit, and a second sampling point is arranged between the second filtering unit and the first subtracter;
and the output end of the first subtracter outputs a voltage difference value between the first sampling point and the second sampling point.
As an improvement of the differential sampling circuit of the present invention, the first voltage limiting and shunting unit includes: the filter circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R11 and a resistor R12 connected in series in sequence and connected between the resistor R11 and the first filter unit in a bridging mode.
As an improvement of the differential sampling circuit of the present invention, a voltage follower U1A is also connected in series between the first voltage limiting and shunting unit and the first filtering unit.
As an improvement of the differential sampling circuit of the present invention, the first filtering unit includes: a resistor R10 and a capacitor C1, the resistor R10 is directly electrically connected to the first subtracter, one end of the capacitor C1 is connected between the resistor R10 and the first subtracter, the other end is grounded, and the first sampling point is defined by a connection point between one end of the capacitor C1 and the resistor R10 and the first subtracter.
As an improvement of the differential sampling circuit of the present invention, the second voltage limiting and shunting unit includes: the resistor R4, the resistor R5, the resistor R6, the resistor R21 and the resistor R23 are connected in series in sequence and are connected between the resistor R21 and the second filtering unit in a bridging mode.
As an improvement of the differential sampling circuit of the present invention, a voltage follower U1B is further connected in series between the second voltage limiting and shunting unit and the second filtering unit.
As an improvement of the differential sampling circuit of the present invention, the second filtering unit includes: a resistor R20 and a capacitor C4, the resistor R20 is directly electrically connected to the first subtracter, one end of the capacitor C4 is connected between the resistor R20 and the first subtracter, the other end is grounded, and the second sampling point is defined by a connection point between one end of the capacitor C4 and the resistor R20 and the first subtracter.
As an improvement of the differential sampling circuit of the present invention, the first subtractor includes: a resistor R15, a resistor R13, a resistor R17, a resistor R19 and an amplifier U2A;
the first filtering unit is connected with the inverting input end of an amplifier U2A through the resistor R15, one end of the resistor R13 is connected between the resistor R15 and the first subtracter, and the other end of the resistor R13 is connected to the output end of the first subtracter;
the second filter unit is connected with the non-inverting input end of an amplifier U2A through the resistor R17, one end of the resistor R19 is connected between the resistor R17 and the first subtracter, and the other end of the resistor R19 is grounded.
As an improvement of the differential sampling circuit of the present invention, when the voltage of the resistor R15 is equal to the voltage of the resistor R13, and the voltage of the resistor R17 is equal to the voltage of the resistor R19, the voltage output by the output terminal of the first subtractor is the difference between the voltages of the first sampling point and the second sampling point.
As an improvement of the differential sampling circuit of the present invention, the differential sampling circuit further includes a third input circuit and a second subtractor;
the third input loop is connected with the first input loop and the second input loop in parallel, the second input loop and the third input loop are connected with the second subtracter, a third sampling point is arranged between the third input loop and the second subtracter, and the output end of the second subtracter outputs the voltage difference value between the second sampling point and the third sampling point.
Compared with the prior art, the invention has the beneficial effects that: the differential sampling circuit is based on the subtracter, the first input circuit and the second input circuit, and the voltage difference value between sampling points is acquired by feeding back four-point resistance voltages.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a circuit diagram of a differential sampling circuit according to a first embodiment of the present invention;
fig. 2 is a circuit diagram of a differential sampling circuit according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a differential sampling circuit according to a first embodiment of the present invention is a two-level sampling circuit. The differential sampling circuit includes: a first subtractor 1, a first input circuit 2, and a second input circuit 3 provided in parallel with the first input circuit 2.
The second input loop 3 is identical in circuit structure to the first input loop 2. Specifically, the second input circuit 3 includes: the second voltage limiting and shunting unit is connected with the first subtracter 1 through the second filtering unit, and a second sampling point is arranged between the second filtering unit and the first subtracter 1.
In one embodiment, the first voltage limiting and shunting unit includes: the filter circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R11 and a resistor R12 connected in series in sequence and connected between the resistor R11 and the first filter unit in a bridging mode. In addition, a voltage follower U1A is also connected in series between the first voltage limiting and shunting unit and the first filtering unit.
The first filtering unit includes: the circuit comprises a resistor R10 and a capacitor C1, wherein the resistor R10 is directly electrically connected to the first subtracter 1, one end of the capacitor C1 is connected between the resistor R10 and the first subtracter 1, the other end of the capacitor C1 is grounded, and a first sampling point is defined by a connection point between one end of the capacitor C1 and the resistor R10 and the first subtracter 1.
Similarly, the second voltage limiting and shunting unit includes: the resistor R4, the resistor R5, the resistor R6, the resistor R21 and the resistor R23 are connected in series in sequence and are connected between the resistor R21 and the second filtering unit in a bridging mode. In addition, a voltage follower U1B is also connected in series between the second voltage limiting and shunting unit and the second filtering unit.
The second filtering unit includes: the resistor R20 and the capacitor C4, the resistor R20 is directly electrically connected to the first subtracter 1, one end of the capacitor C4 is connected between the resistor R20 and the first subtracter 1, the other end of the capacitor C4 is grounded, and a second sampling point is defined by a connection point between one end of the capacitor C4 and the resistor R20 and the first subtracter 1.
The output of the first subtractor 1 outputs a voltage difference between the first sampling point and the second sampling point.
In one embodiment, the first subtractor 1 includes: a resistor R15, a resistor R13, a resistor R17, a resistor R19, and an amplifier U2A.
The first filter unit is connected with the inverting input end of the amplifier U2A through a resistor R15, one end of the resistor R13 is connected between the resistor R15 and the first subtracter 1, and the other end of the resistor R13 is connected to the output end of the first subtracter 1; the second filter unit is connected with the non-inverting input end of the amplifier U2A through a resistor R17, one end of the resistor R19 is connected between the resistor R17 and the first subtracter 1, and the other end of the resistor R3526 is grounded. At this time, when the voltage of the resistor R15 is equal to the voltage of the resistor R13, and the voltage of the resistor R17 is equal to the voltage of the resistor R19, the voltage output by the output end of the first subtractor 1 is the difference between the voltages at the first sampling point and the second sampling point.
In the differential sampling circuit of this embodiment, the principle of voltage sampling of "+" pair "N" is as follows:
for a '+' input loop, a current-limiting voltage-dividing loop is formed by a resistor R1, a resistor R2, a resistor R3, a resistor R11 and a resistor R12, and the voltage drop of the resistor R12 is sent to a lower-stage amplifier U2A through a voltage follower U1A and a filter circuit formed by the resistors R10 and C1; the "N" input circuit is the same as the "+" input circuit, the resistor R15, the resistor R13, the resistor R17, the resistor R19, and the resistor U2A constitute a subtractor, and if the voltage of the resistor R15 is equal to the voltage of the resistor R13 and the voltage of the resistor R17 is equal to the voltage of the resistor R19, the voltage at the point D is the difference between the voltages at the point a and the point B (UD is UA-UB). U2B is an inverting amplifier for adjusting the output amplitude and positive and negative; and sending the output Vdc + signal into an analog-to-digital converter or a digital processor DSP to finish accurate sampling.
As shown in fig. 2, a second embodiment of the present invention provides a differential sampling circuit, which is a three-level sampling circuit. The differential sampling circuit includes: a first subtractor 1, a first input circuit 2, and a second input circuit 3 provided in parallel with the first input circuit 2.
In addition, the differential sampling circuit further comprises a third input circuit 4 and a second subtractor 5. The third input circuit 4 has the same circuit configuration as the first input circuit 2 and the second input circuit 3, and the second subtractor 5 has the same circuit configuration as the first subtractor 1.
Based on the same working principle, the third input loop 4 is connected in parallel with the first input loop 2 and the second input loop 3, the second input loop 3 and the third input loop 4 are connected with the second subtracter 5, a third sampling point is arranged between the third input loop 4 and the second subtracter 5, and the output end of the second subtracter 5 outputs a voltage difference value between the second sampling point and the third sampling point.
In summary, the differential sampling circuit of the present invention has a plurality of transfer units and a plurality of calibration stages, which can achieve chip mounting by taking a plurality of chips at a time and continuously mounting the plurality of chips, thereby significantly improving chip mounting efficiency and productivity.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A differential sampling circuit, comprising: the input circuit comprises a first subtractor, a first input circuit and a second input circuit which is connected with the first input circuit in parallel;
the first input loop comprises: the first voltage limiting and shunting unit is connected with the first subtracter through the first filtering unit, and a first sampling point is arranged between the first filtering unit and the first subtracter;
the second input circuit includes: the second voltage limiting and shunting unit is connected with the first subtracter through the second filtering unit, and a second sampling point is arranged between the second filtering unit and the first subtracter;
and the output end of the first subtracter outputs a voltage difference value between the first sampling point and the second sampling point.
2. The differential sampling circuit of claim 1, wherein the first voltage limiting shunt unit comprises: the filter circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R11 and a resistor R12 connected in series in sequence and connected between the resistor R11 and the first filter unit in a bridging mode.
3. The differential sampling circuit according to claim 2, wherein a voltage follower U1A is further connected in series between the first voltage limiting and shunting unit and the first filtering unit.
4. The differential sampling circuit of claim 1, wherein the first filtering unit comprises: a resistor R10 and a capacitor C1, the resistor R10 is directly electrically connected to the first subtracter, one end of the capacitor C1 is connected between the resistor R10 and the first subtracter, the other end is grounded, and the first sampling point is defined by a connection point between one end of the capacitor C1 and the resistor R10 and the first subtracter.
5. The differential sampling circuit of claim 1, wherein the second voltage limiting shunt unit comprises: the resistor R4, the resistor R5, the resistor R6, the resistor R21 and the resistor R23 are connected in series in sequence and are connected between the resistor R21 and the second filtering unit in a bridging mode.
6. The differential sampling circuit according to claim 5, wherein a voltage follower U1B is further connected in series between the second voltage limiting and shunting unit and the second filtering unit.
7. The differential sampling circuit of claim 1, wherein the second filtering unit comprises: a resistor R20 and a capacitor C4, the resistor R20 is directly electrically connected to the first subtracter, one end of the capacitor C4 is connected between the resistor R20 and the first subtracter, the other end is grounded, and the second sampling point is defined by a connection point between one end of the capacitor C4 and the resistor R20 and the first subtracter.
8. The differential sampling circuit of claim 1, wherein the first subtractor comprises: a resistor R15, a resistor R13, a resistor R17, a resistor R19 and an amplifier U2A;
the first filtering unit is connected with the inverting input end of an amplifier U2A through the resistor R15, one end of the resistor R13 is connected between the resistor R15 and the first subtracter, and the other end of the resistor R13 is connected to the output end of the first subtracter;
the second filter unit is connected with the non-inverting input end of an amplifier U2A through the resistor R17, one end of the resistor R19 is connected between the resistor R17 and the first subtracter, and the other end of the resistor R19 is grounded.
9. The differential sampling circuit of claim 8, wherein when the voltage across the resistor R15 is equal to the voltage across the resistor R13, and the voltage across the resistor R17 is equal to the voltage across the resistor R19, the voltage output by the output of the first subtractor is the difference between the voltages at the first and second sampling points.
10. The differential sampling circuit of claim 1, further comprising a third input loop and a second subtractor;
the third input loop is connected with the first input loop and the second input loop in parallel, the second input loop and the third input loop are connected with the second subtracter, a third sampling point is arranged between the third input loop and the second subtracter, and the output end of the second subtracter outputs the voltage difference value between the second sampling point and the third sampling point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010417418.8A CN111446956A (en) | 2020-05-18 | 2020-05-18 | Differential sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010417418.8A CN111446956A (en) | 2020-05-18 | 2020-05-18 | Differential sampling circuit |
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| Publication Number | Publication Date |
|---|---|
| CN111446956A true CN111446956A (en) | 2020-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010417418.8A Pending CN111446956A (en) | 2020-05-18 | 2020-05-18 | Differential sampling circuit |
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| CN (1) | CN111446956A (en) |
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2020
- 2020-05-18 CN CN202010417418.8A patent/CN111446956A/en active Pending
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