CN111446266B - Display panel and preparation method thereof - Google Patents
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- CN111446266B CN111446266B CN202010399118.1A CN202010399118A CN111446266B CN 111446266 B CN111446266 B CN 111446266B CN 202010399118 A CN202010399118 A CN 202010399118A CN 111446266 B CN111446266 B CN 111446266B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The application provides a display panel and a preparation method of the display panel, wherein the display panel comprises a substrate, an active layer, a grid insulating layer, a grid layer, an interlayer dielectric layer, a source drain layer, a planarization layer and a connecting member which are arranged in a stacked mode; the source drain layer is patterned to form a source electrode, a drain electrode and a plurality of data lines, each data line comprises an in-plane routing located in the display area and a fan-out routing located in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other; the planarization layer is provided with a via hole in the display area; the connecting component is respectively connected with the in-plane routing and the fan-out routing of each first data line. In this application on the planarization layer on the first data line when toasting, the heat of fan-out line can not transmit to the face in and walk the line, and the bank angle of planarization layer in the via hole is normal, therefore the rete of follow-up processing procedure is difficult for producing the fracture in this department, and connecting elements can not influence the transmission of signal after connecting first data line.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method of the display panel.
Background
The display panel is usually provided with a plurality of data lines, the data lines are connected with a drive IC and used for providing drive signals to the inside of the display panel, the data lines comprise an inside wiring line positioned in the display area and a fan-out wiring line positioned in the fan-out area, in the existing Low Temperature Polysilicon (LTPS) process, a planarization layer is arranged on the inside wiring line to improve the flatness, the planarization layer is made of organic photoresist and needs to be formed through the steps of coating, exposing, developing and baking. However, in the baking process, because the fan-out wires are dense, the heat absorption is more during the metal baking, and the heat can be transferred to the in-plane wires, so that the final slope angle formed by the via holes close to the fan-out area in the planarization layer above the in-plane wires is larger, and the film layer in the subsequent process is easy to break when formed in the via holes.
Therefore, the existing display panel has the technical problem that the slope angle of the via hole close to the fan-out area in the planarization layer is large, and needs to be improved.
Disclosure of Invention
The embodiment of the application provides a display panel and a preparation method of the display panel, which are used for relieving the technical problem that the slope angle of a via hole close to a fan-out area in a planarization layer in the conventional display panel is large.
An embodiment of the present application provides a display panel, including:
a substrate;
an active layer formed on one side of the substrate;
the gate insulating layer is formed on one side, far away from the substrate, of the active layer;
the grid electrode layer is formed on one side, far away from the active layer, of the grid electrode insulating layer and is patterned to form a grid electrode;
the interlayer dielectric layer is formed on one side, away from the grid insulating layer, of the grid layer;
the source drain layer is formed on one side, far away from the gate layer, of the interlayer dielectric layer, and is patterned to form a source electrode, a drain electrode and a plurality of data lines, each data line comprises an in-plane routing in the display area and a fan-out routing in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other;
the planarization layer is formed on one side, away from the interlayer dielectric layer, of the source drain layer, and a through hole is formed in the planarization layer in the display area;
and the connecting component is formed on one side of the source drain layer, which is far away from the interlayer dielectric layer, and is respectively connected with the in-plane routing and the fan-out routing of each first data line.
In the display panel of this application, display panel is liquid crystal display panel, still includes first electrode layer, insulating layer and the second electrode layer of range upon range of setting, first electrode layer forms the planarization layer is kept away from one side of source drain layer, a plurality of first electrodes that the patterning formed array set up, walk the line in the face of data line and pass through via hole in the planarization layer with first electrode is connected.
In the display panel of the application, the display panel is an OLED display panel, and further comprises a first electrode layer, a pixel definition layer, a light emitting material layer and a second electrode layer, wherein the first electrode layer is formed on one side, away from the source drain layer, of the planarization layer, a plurality of first electrodes arranged in an array mode are formed in a patterning mode, and the first electrodes are connected with the drain electrodes through via holes in the planarization layer.
In the display panel of the present application, the connection member is the same material as the first electrode.
In the display panel of the present application, the connection member is different from the first electrode material.
In the display panel of the present application, the data lines are all first data lines.
In the display panel of this application, the data line still includes the second data line, the line is walked with the fan-out in the face of second data line and is walked line interconnect with the fan-out, display panel still includes the district of binding of being connected with the fan-out district, bind the district be provided with the fan-out is walked the line and is connected bind the terminal, bind the terminal including being close to the first terminal of binding in display panel middle part and being close to the second of display panel both sides and bind the terminal, the fan-out of first data line walk the line with the first terminal connection of binding, the fan-out of second data line walk the line with the second is bound the terminal connection.
The application also provides a preparation method of the display panel, which comprises the following steps:
providing a substrate;
preparing an active layer, a grid electrode insulating layer, a grid electrode layer and an interlayer dielectric layer on the substrate in sequence;
forming a source drain layer on one side of the interlayer dielectric layer, which is far away from the gate electrode layer, and patterning the source drain layer to form a source electrode, a drain electrode and a plurality of data lines, wherein each data line comprises an in-plane wire positioned in the display area and a fan-out wire positioned in the fan-out area, the data lines comprise at least one first data line, and the in-plane wire and the fan-out wire of each first data line are not in contact with each other;
forming a planarization layer on one side, away from the interlayer dielectric layer, of the source drain layer, wherein a through hole is formed in the planarization layer in the display area;
and forming a connecting member on one side of the source drain layer, which is far away from the interlayer dielectric layer, wherein the connecting member is respectively connected with the in-plane routing and the fan-out routing of each first data line.
In the method for manufacturing a display panel according to the present application, the step of forming a connecting member on a side of the source/drain layer away from the interlayer dielectric layer includes: and forming a first electrode layer on one side of the planarization layer, which is far away from the source drain layer, and patterning to form a plurality of first electrodes and the connecting members which are arranged in an array.
In the method for manufacturing a display panel of the present application, the step of forming a connection member on a side of the source drain layer away from the interlayer dielectric layer includes: and forming a first electrode layer on one side of the planarization layer, which is far away from the source drain layer, patterning the first electrode layer to form a plurality of first electrodes arranged in an array, and forming a connecting member on one side of the source drain layer, which is far away from the interlayer dielectric layer.
Has the advantages that: the application provides a display panel and a preparation method of the display panel, wherein the display panel comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer dielectric layer, a source drain electrode layer, a planarization layer and a connecting member; the active layer is formed on one side of the substrate; the grid insulating layer is formed on one side of the active layer far away from the substrate; the grid layer is formed on one side of the grid insulation layer far away from the active layer and is patterned to form a grid; the interlayer dielectric layer is formed on one side of the grid electrode layer far away from the grid electrode insulating layer; the source and drain electrode layer is formed on one side, far away from the grid layer, of the interlayer dielectric layer, a source electrode, a drain electrode and a plurality of data lines are formed in a patterning mode, each data line comprises an in-plane routing located in the display area and a fan-out routing located in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other; the planarization layer is formed on one side, away from the interlayer dielectric layer, of the source drain layer, and a through hole is formed in the planarization layer in the display area; the connecting component is formed on one side, far away from the interlayer dielectric layer, of the source drain layer, and the connecting component is connected with the in-plane routing and the fan-out routing of each first data line respectively. Through setting up an at least first data line in this application, and in the first data line in the face walk the line and fan-out walk the line and do not contact each other, then the planarization layer of first data line top is when toasting, the heat of fan-out walking the line can not transmit to in the face walk the line, the bank angle that is close to the via hole in the planarization layer in the fan-out district is normal, consequently, the rete formation in the follow-up processing procedure is difficult to produce the fracture when should cross downtheholely, and with the connecting means with the face of first data line walk the line and fan-out walk the line connection back, also can not influence the transmission of signal.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first film layer structure of a display panel according to an embodiment of the present disclosure.
Fig. 2 is a schematic plan view of a display panel in the prior art.
Fig. 3 is a schematic diagram of via formation of a planarization layer in the prior art.
Fig. 4 is a schematic view of a second film layer structure of the display panel according to the embodiment of the present disclosure.
Fig. 5 is a schematic view of a first planar structure of a display panel according to an embodiment of the present disclosure.
Fig. 6 is a schematic plan view of a second display panel according to an embodiment of the present disclosure.
Fig. 7 is a schematic flow chart of a manufacturing method of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular orientation, and thus are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
The embodiment of the application provides a display panel and a preparation method of the display panel, which are used for relieving the technical problem that the slope angle of a via hole close to a fan-out area in a planarization layer in the conventional display panel is large.
As shown in fig. 1, which is a schematic view of a first film layer structure of a display panel provided in an embodiment of the present disclosure, the display panel includes a substrate 101, an active layer 102, a gate insulating layer 103, a gate layer, an interlayer dielectric layer 105, a source drain layer, a planarization layer 109, and a connection member 110.
The active layer 102 is formed on the substrate 101 side;
a gate insulating layer 103 is formed on a side of the active layer 102 away from the substrate 101;
the gate layer is formed on one side of the gate insulating layer 103 far away from the active layer 102, and the gate 103 is formed in a patterning mode;
an interlayer dielectric layer 105 is formed on one side of the gate electrode layer away from the gate insulating layer 103;
the source and drain electrode layer is formed on one side, far away from the gate electrode layer, of the interlayer dielectric layer 105, and is patterned to form a source electrode 106, a drain electrode 107 and a plurality of data lines, each data line comprises an in-plane routing 1081 positioned in the display area 10 and a fan-out routing 1082 positioned in the fan-out area 20, each data line comprises at least one first data line, and the in-plane routing 1081 and the fan-out routing 1082 of each first data line are not in contact with each other;
the planarization layer 109 is formed on one side of the source drain layer away from the interlayer dielectric layer 105, and a through hole 30 is formed in the planarization layer in the display area 10;
the connecting member 110 is formed on a side of the source-drain layer away from the interlayer dielectric layer 105, and the connecting member 110 is connected with the in-plane trace 1081 and the fan-out trace 1082 of each first data line.
The substrate 101 may be a flexible substrate, and a material thereof may include at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone; the substrate may also be a rigid substrate, in particular a glass substrate or other rigid substrate. The present embodiment does not limit the kind and material of the substrate 101.
A light-shielding layer 111 and a barrier layer 112 are also typically provided on the substrate 101. The light-shielding layer 111 is made of metal, and the barrier layer 112 is made of at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
The active layer 102 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions, and a channel region between the source region and the drain region. The active layer 102 may be an amorphous silicon material, a polysilicon material, or a metal oxide material, wherein when the active layer 102 is a polysilicon material, the active layer may be formed by a low-temperature amorphous silicon technique, that is, the amorphous silicon material is melted by the laser to form the polysilicon material. In addition, the active layer 102 may also be formed using various methods such as a Rapid Thermal Annealing (RTA) method, a Solid Phase Crystallization (SPC) method, an Excimer Laser Annealing (ELA) method, a Metal Induced Crystallization (MIC) method, a Metal Induced Lateral Crystallization (MILC) method, or a Sequential Lateral Solidification (SLS) method.
The material of the gate insulating layer 103 is typically at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure.
A gate layer is on the gate insulating layer 103, and patterned to form a gate electrode 104, and the gate layer may be a single-layer or multi-layer structure including gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), Molybdenum (MO), or chromium (Cr), or a metal such as aluminum (Al): neodymium (Nd) alloy and Molybdenum (MO): an alloy of tungsten (W) alloy.
The interlayer dielectric layer 105 is disposed on the gate layer, and the interlayer dielectric layer 105 may be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two.
A source and drain layer is formed on the interlayer dielectric layer 105, a source electrode 106, a drain electrode 107, and a data line are patterned, and the source electrode 106 and the drain electrode 107 are electrically connected to a source region and a drain region of the active layer 102 through vias penetrating the gate insulating layer 103 and the interlayer dielectric layer 105, respectively.
The planarization layer 109 is located on the source/drain layer and is made of organic photoresist. The layers above and below the planarization layer 109 typically need to be connected, and thus the planarization layer 109 is formed with vias 30 in the display area 10.
The display panel of the application comprises a display area 10 and a non-display area, wherein the non-display area comprises a fan-out area 20 and a binding area, a plurality of parallel in-plane routing 1081 of the data lines are arranged in the display area 10, the data lines extend to the fan-out area 20 in a concentrated mode, the fan-out routing 1082 is connected with the binding area and bound with an external drive IC, and the drive IC provides drive signals for the data lines to drive the display panel to work.
In this embodiment, the display panel is a liquid crystal display panel, and further includes a first electrode layer, an insulating layer 202, and a second electrode layer stacked on the planarization layer 109 and the connection member 110, the first electrode layer is patterned to form a plurality of first electrodes 201 arranged in an array, the insulating layer 202 is formed on the first electrode layer, and the material of the insulating layer 202 may be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two. A second electrode layer is formed on the insulating layer 202, and patterned to form a second electrode 203.
In the present embodiment, the via 30 in the planarization layer 109 includes a first via 31 and a second via 32, the in-plane trace 1081 of the data line is connected to the first electrode 201 through the first via 31 in the planarization layer 109 to provide the driving signal to the first electrode 201, and the second electrode 203 is connected to the drain 107 through the second via 32. The first electrode 201 is a common electrode, and the second electrode 203 is a pixel electrode.
As shown in fig. 2, which is a schematic plan view of a display panel in the prior art, taking a liquid crystal display panel as an example, a first electrode layer is patterned to form a plurality of first electrodes 201 arranged in an array, the first electrodes 201 are independent from each other, and each first electrode 201 is connected to one data line through a first via hole 31 in a planarization layer (not shown), so as to implement independent transmission of signals. Each data line comprises an in-plane routing 1081 located in the display area 10 and a fan-out routing 1082 located in the fan-out area 20, the in-plane routing 1081 is parallel to the fan-out routing 1082, each fan-out routing 1082 is a folding line, each fan-out routing 1082 is connected to a binding terminal 400 in the binding area 30, and then the binding is achieved through the binding terminal 400 and the driver IC. The in-plane routing 1081 and the fan-out routing 1082 of each data line are integrally formed and connected in the same process.
Fig. 3 is a schematic diagram illustrating via formation of a planarization layer in the prior art. The material used by the planarization layer is organic photoresist, after the exposure and development process, the curve formed by the via hole 30 is the curve A in the figure, at this moment, the slope angle a is larger, because the organic photoresist is not completely cured at this moment, and has fluidity (Re-Flow), under an ideal state, the finally formed curve is the curve B in the figure, and the slope angle a is smaller. However, since the fan-out traces 1082 in the fan-out area 20 are distributed densely, in the final curing process of the organic photoresist, the via holes 30 near the fan-out traces 1082 are affected by the fan-out traces 1082 during the baking process, and are heated more quickly, so that the organic photoresist at the via holes 30 is cured in advance, the organic photoresist does not flow into a desired slope angle, the shape is cured, the curve after final molding is the curve C in the figure, so that the slope angle a at the position is larger, and in the subsequent process, the weak film layer formed in the via holes 30 is more prone to fracture, which finally affects the yield of the display panel.
In the present application, the data lines at least include one first data line, the in-plane trace 1081 and the fan-out trace 1082 of the first data line are not in contact with each other, so that when the planarization layer 109 formed at the place is baked, heat of the fan-out trace 1082 is not transferred to the in-plane trace 1081, a final molding curve of the planarization layer 109 is as expected, when the planarization layer 109 forms the via hole 30 close to the fan-out trace 1082, a slope angle is not large, a film layer in a subsequent manufacturing is not easily broken when formed in the via hole 30, and after the planarization layer 109 is formed, the in-plane trace 1081 and the fan-out trace 1082 of the first data line are connected by the connecting member 110, so that signal transfer is not affected.
Through the novel signal wiring design, after the organic photoresist is formed, the wiring in the plane and the fan-out wiring are connected, the problem that the slope angle of the via hole of the organic photoresist layer above the first data line is large is solved, and the product yield is improved.
In one embodiment, the connection member 110 is the same material as the first electrode 201. Because the first electrode 201 is formed on the planarization layer 109, the connection member 110 is formed on the side of the source drain layer away from the interlayer dielectric layer 105, and the planarization layer 109 is usually located in the display area 10 and is not disposed in the fan-out area 20, the first electrode 201 and the connection member 110 can be simultaneously formed through one process, and the connection between the in-plane trace 1081 and the fan-out trace 1082 of the first data line is realized without increasing the manufacturing process and the number of photomasks, which is simple and easy to implement.
In one embodiment, the connecting member 110 is a different material than the first electrode 201. The material of the first electrode 201 is usually indium tin oxide, and the material of the data line is usually metal, in order to achieve better connection effect of the data line, the first electrode 201 and the connection member 220 are separately manufactured in two processes, and the order of the two processes can be interchanged. The connection member 220 is made of the same metal material as the data line, and the first electrode 201 is formed using commonly used indium tin oxide. The method can enable the connection effect of the in-plane wiring 1081 and the fan-out wiring 1082 to be good, the resistance cannot be changed too much, and the transmission signals are stable.
Fig. 4 is a schematic view of a second film layer structure of the display panel according to the embodiment of the present application. The structure of the display panel is different from that of fig. 1 in that the display panel in this embodiment is an OLED display panel.
The display panel includes a substrate 101, an active layer 102, a gate insulating layer 103, a gate layer, an interlayer dielectric layer 105, a source/drain layer, a planarization layer 109, and a connection member 110, and the materials and positions of the structures are the same as those in fig. 1, and are not described herein again. In this embodiment, the display panel further includes a first electrode layer, a pixel defining layer 302, a light emitting material layer 303 and a second electrode layer, the first electrode layer is formed on a side of the planarization layer 109 away from the source drain layer, a plurality of first electrodes 301 arranged in an array are formed by patterning, and the first electrodes 301 are connected with the drain electrode 107 through the via holes 30 in the planarization layer 109. An opening area is formed between adjacent first electrodes 301, a pixel defining layer 302 is formed in the opening area, a light emitting material layer 303 is formed on the first electrodes 301, a second electrode layer is patterned to form a second electrode 304, and the second electrode 304 is located on the light emitting material layer 303 and extends to cover the pixel defining layer 302. The first electrode 301 is an anode, and the second electrode 304 is a cathode.
In the OLED display panel, the first electrode 301 needs to pass through the via 30 and the drain 107 in the planarization layer 109, and the via 30 also exists in the area close to the fan-out area 20, so that the in-plane trace 1081 and the fan-out trace 1082 in the first data line also need to be subjected to wire jumper processing, and then after the planarization layer 109 is exposed, developed and baked, the in-plane trace 1081 and the fan-out trace 1082 in the first data line are connected by the connection member 110.
In one embodiment, the connection member 110 is the same material as the first electrode 301. Because the first electrode 301 is formed on the planarization layer 109, the connection member 110 is formed on the side of the source drain layer away from the interlayer dielectric layer 105, and the planarization layer 109 is usually located in the display area 10 and is not disposed in the fan-out area 20, the first electrode 301 and the connection member 110 can be simultaneously formed through one process, and the connection between the in-plane trace 1081 and the fan-out trace 1082 of the first data line is realized without increasing the manufacturing process and the number of photomasks, which is simple and easy to implement.
In one embodiment, the connecting member 110 is a different material than the first electrode 301. The material of the first electrode 301 is typically indium tin oxide, and the material of the data line is typically metal, so that the first electrode 301 and the connecting member 220 are manufactured separately in two steps, and the order of the two steps can be interchanged, in order to achieve better connection effect of the data line. The connection member 220 is made of the same metal material as the data line, and the first electrode 301 is formed of commonly used indium tin oxide. The method can enable the connection effect of the in-plane routing 1081 and the fan-out routing 1082 to be good, the resistance cannot be changed too much, and transmission signals are stable.
In one embodiment, the data lines in the display panel are all first data lines. Fig. 5 is a schematic view of a first planar structure of a display panel according to an embodiment of the present disclosure. For convenience of explanation, the liquid crystal display panel is taken as an example, but the distribution of the data lines is also applicable to the OLED display panel.
In fig. 5, all the data lines are the first data lines, so that all the in-plane traces 1081 and the fan-out traces 1082 of the display panel are not in contact with each other, and are connected by the connecting member 110, so as to implement signal transmission. At this time, the planarization layer is not affected by the fan-out trace 1082 when forming all the first vias 31, and the slope angle formed by the planarization layer is ideal.
In an embodiment, as shown in fig. 6, the data lines further include second data lines, in-plane wires 1081 and fan-out wires 1082 of the second data lines are connected with each other, the display panel further includes a binding area 30 connected with the fan-out area, the binding area 30 is provided with binding terminals 400 connected with the fan-out wires 1082, the binding terminals 400 include first binding terminals 401 near the middle of the display panel and second binding terminals 402 near two sides of the display panel, the fan-out wires 1082 of the first data lines are connected with the first binding terminals 401, and the fan-out wires 1082 of the second data lines are connected with the second binding terminals 402.
The display panel is provided with a plurality of terminals 400 of binding in the district 30 that binds of display panel, every terminal 400 of binding is connected with a data line, in fan-out district 20, it is shorter to walk the line 1082 with the fan-out that is close to the first terminal 401 of binding that is connected in the middle part of the display panel, heat transfer speed is more fast, it is great to the bank angle influence of planarization layer, and it is longer to walk the line 1082 with the fan-out that is close to the second terminal 402 connection that binds of display panel both sides, heat transfer speed is less slowly, it is less to the influence of bank angle. Therefore, only the data line connected to the first binding terminal 401 may be set as the first data line to perform a jumper design, and then connected through the connection member 110, thereby improving the planarization layer slope angle problem, and the data line connected to the first binding terminal 401 may be set as the second data line to maintain the original design. The design mode only needs to improve partial data lines, so that the cost is relatively low, and the required quantity of the first data lines and the second data lines can be reasonably designed according to the factors such as the size of a panel, the length of fan-out routing lines and the like.
In the above embodiment, by providing at least one first data line, and the in-plane wires and the fan-out wires in the first data line are not in contact with each other, when the planarization layer above the first data line is baked, the heat of the fan-out wires is not transferred to the in-plane wires, and the slope angle of the via hole close to the fan-out region in the planarization layer is normal, so that the film layer in the subsequent process is not easily broken when formed in the via hole, and after the in-plane wires and the fan-out wires of the first data line are connected by the connecting member, the transfer of signals is not affected.
As shown in fig. 7, the present application further provides a method for manufacturing a display panel, including the steps of:
s701: providing a substrate;
s702: sequentially preparing an active layer, a grid electrode insulating layer, a grid electrode layer and an interlayer dielectric layer on a substrate;
s703: forming a source drain layer on one side of the interlayer dielectric layer, which is far away from the gate layer, and patterning the source drain layer to form a source electrode, a drain electrode and a plurality of data lines, wherein each data line comprises an in-plane routing in the display area and a fan-out routing in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other;
s704: forming a planarization layer on one side of the source drain layer, which is far away from the interlayer dielectric layer, wherein a through hole is formed in the planarization layer in the display area;
s705: and forming a connecting member on one side of the source drain layer far away from the interlayer dielectric layer, wherein the connecting member is respectively connected with the in-plane routing and the fan-out routing of each first data line.
The method is described in detail below with reference to fig. 1 to 7.
In S701, a substrate is provided. As shown in fig. 1, the substrate 101 may be a flexible substrate, and a material thereof may include at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone; the substrate may also be a rigid substrate, in particular a glass substrate or other rigid substrate. The kind and material of the substrate 101 are not limited in the embodiments of the present application.
In S702, an active layer, a gate insulating layer, a gate layer, and an interlayer dielectric layer are sequentially formed on a substrate. As shown in fig. 1, a light-shielding layer 111 and a barrier layer 112 are usually provided on the substrate 101. The light-shielding layer 111 is made of metal, and the barrier layer 112 is made of at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
The active layer 102 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions, and a channel region between the source region and the drain region. The active layer 102 may be an amorphous silicon material, a polysilicon material, a metal oxide material, or the like.
The material of the gate insulating layer 103 is typically at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure.
A gate layer is on the gate insulating layer 103, and patterned to form a gate electrode 104, and the gate layer may be a single-layer or multi-layer structure including gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), Molybdenum (MO), or chromium (Cr), or a metal such as aluminum (Al): neodymium (Nd) alloy and Molybdenum (MO): an alloy of tungsten (W) alloy.
The interlayer dielectric layer 105 is disposed on the gate layer, and the interlayer dielectric layer 105 may be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two.
In S703, a source/drain layer is formed on a side of the interlayer dielectric layer away from the gate layer, and a source electrode, a drain electrode, and a plurality of data lines are formed by patterning, each data line includes an in-plane trace in the display region and a fan-out trace in the fan-out region, the data line includes at least one first data line, and the in-plane trace and the fan-out trace of each first data line are not in contact with each other. As shown in fig. 1, a source and drain layer is formed on the interlayer dielectric layer 105, and a source electrode 106, a drain electrode 107, and a data line are patterned, and the source electrode 106 and the drain electrode 107 are electrically connected to a source region and a drain region of the active layer 102 through vias penetrating the gate insulating layer 103 and the interlayer dielectric layer 105, respectively.
The display panel of the application comprises a display area 10 and a non-display area, wherein the non-display area comprises a fan-out area 20 and a binding area, a plurality of parallel in-plane routing 1081 of the data lines are arranged in the display area 10, the data lines extend to the fan-out area 20 in a concentrated mode, the fan-out routing 1082 is connected with the binding area and bound with an external drive IC, and the drive IC provides drive signals for the data lines to drive the display panel to work.
In S704, a planarization layer is formed on a side of the source drain layer away from the interlayer dielectric layer, and a via hole is formed in the planarization layer in the display region. As shown in fig. 1, the planarization layer 109 is located on the source/drain layer and is made of organic photoresist. The layers above and below the planarization layer 109 typically need to be connected, and thus the planarization layer 109 is formed with vias 30 in the display area 10.
In S705, a connection member is formed on a side of the source drain layer away from the interlayer dielectric layer, and the connection member is connected to the in-plane trace and the fan-out trace of each first data line.
In one embodiment, as shown in fig. 1, the display panel is a liquid crystal display panel, and further includes a first electrode layer, an insulating layer 202 and a second electrode layer stacked on the planarization layer 109 and the connection member 110, the first electrode layer is patterned to form a plurality of first electrodes 201 arranged in an array, the insulating layer 202 is formed on the first electrode layer, and the material of the insulating layer 202 may be silicon oxide (SiOx), silicon nitride (SiNx), or a sandwich structure of the two. A second electrode layer is formed on the insulating layer 202, and a second electrode 203 is patterned. At this time, the via 30 in the planarization layer 109 includes a first via 31 and a second via 32, the in-plane trace 1081 of the data line is connected to the first electrode 201 through the first via 31 in the planarization layer 109 to provide the driving signal to the first electrode 201, and the second electrode 203 is connected to the drain electrode 107 through the second via 32. The first electrode 201 is a common electrode, and the second electrode 203 is a pixel electrode.
In one embodiment, as shown in fig. 4, the display panel is an OLED display panel, and the display panel further includes a first electrode layer, a pixel defining layer 302, a light emitting material layer 303, and a second electrode layer, the first electrode layer is formed on a side of the planarization layer 109 away from the source drain layer, the first electrode layer is patterned to form a plurality of first electrodes 301 arranged in an array, and the first electrodes 301 are connected to the drain electrodes 107 through the vias 30 in the planarization layer 109. An opening area is formed between adjacent first electrodes 301, a pixel defining layer 302 is formed in the opening area, a light emitting material layer 303 is formed on the first electrodes 301, a second electrode layer is patterned to form a second electrode 304, and the second electrode 304 is located on the light emitting material layer 303 and extends to cover the pixel defining layer 302. The first electrode 301 is an anode, and the second electrode 304 is a cathode.
In the prior art, the in-plane wiring 1081 and the fan-out wiring 1082 are directly connected, and in the baking process, because the fan-out wiring 1082 is dense, the heat absorption is more during the metal baking, and the heat can be transferred to the in-plane wiring 10811081, so that in the planarization layer 109 above the in-plane wiring, the final slope angle formed by the via hole 30 close to the fan-out area 20 is larger, and the film layer in the subsequent process is easy to break when formed in the via hole, thereby affecting the product yield.
In the present application, the data lines at least include one first data line, the in-plane trace 1081 and the fan-out trace 1082 of the first data line are not in contact with each other, so that when the planarization layer 109 formed at the place is baked, heat of the fan-out trace 1082 is not transferred to the in-plane trace 1081, a final molding curve of the planarization layer 109 is as expected, when the planarization layer 109 forms the via hole 30 close to the fan-out trace 1082, a slope angle is not large, a film layer in a subsequent manufacturing is not easily broken when formed in the via hole 30, and after the planarization layer 109 is formed, the in-plane trace 1081 and the fan-out trace 1082 of the first data line are connected by the connecting member 110, so that signal transfer is not affected.
In one embodiment, the step of forming the connecting member 110 includes: and forming a first electrode layer on one side of the planarization layer, which is far away from the source drain electrode layer, and patterning to form a plurality of first electrodes and connecting members arranged in an array. At this time, the connection member 110 is the same material as the first electrode 201. Because the first electrode 201 is formed on the planarization layer 109, the connection member 110 is formed on the side of the source drain layer away from the interlayer dielectric layer 105, and the planarization layer 109 is usually located in the display area 10 and is not disposed in the fan-out area 20, the first electrode 201 and the connection member 110 can be simultaneously formed through one process, and the connection between the in-plane trace 1081 and the fan-out trace 1082 of the first data line is realized without increasing the manufacturing process and the number of photomasks, which is simple and easy to implement.
In one embodiment, the step of forming the connecting member 110 may further include: and respectively forming a first electrode layer and a connecting component on one side of the planarization layer, which is far away from the source drain electrode layer, through two processes, wherein the first electrode layer is patterned to form a plurality of first electrodes arranged in an array. At this time, the connection member 110 is different in material from the first electrode 201. The material of the first electrode 201 is typically indium tin oxide, and the material of the data line is typically metal, in order to achieve better connection effect of the data line, the first electrode 201 and the connection member 220 are manufactured separately in two steps, and the order of the two steps can be interchanged. The connection member 220 is made of the same metal material as the data line, and the first electrode 201 is formed using commonly used indium tin oxide. The method can enable the connection effect of the in-plane wiring 1081 and the fan-out wiring 1082 to be good, the resistance cannot be changed too much, and the transmission signals are stable.
In an embodiment, as shown in fig. 5, the data lines in the display panel are all the first data lines, so that all the in-plane traces 1081 and the fan-out traces 1082 of the display panel are not in contact with each other, and are connected by the connecting member 110, so as to implement signal transmission. At this time, the planarization layer is not affected by the fan-out trace 1082 when forming all the first vias 31, and the slope angle formed by the planarization layer is ideal.
In an embodiment, as shown in fig. 6, the data line further includes a second data line, the in-plane routing 1081 and the fan-out routing 1082 of the second data line are connected to each other, the display panel further includes a bonding area 30 connected to the fan-out area, the bonding area 30 is provided with a bonding terminal 400 connected to the fan-out routing 1082, the bonding terminal 400 includes a first bonding terminal 401 near the middle of the display panel and second bonding terminals 402 near two sides of the display panel, the fan-out routing 1082 of the first data line is connected to the first bonding terminal 401, and the fan-out routing 1082 of the second data line is connected to the second bonding terminal 402.
The display panel is provided with a plurality of binding terminals 400 in the binding area 30, each binding terminal 400 is connected with one data line, in the fan-out area 20, the fan-out wiring 1082 connected with the first binding terminal 401 close to the middle of the display panel is shorter, the heat transfer speed is higher, the influence on the slope angle of the planarization layer is larger, the fan-out wiring 1082 connected with the second binding terminals 402 close to the two sides of the display panel is longer, the heat transfer speed is lower, and the influence on the slope angle is smaller. Therefore, only the data line connected to the first binding terminal 401 may be set as the first data line to perform a jumper design, and then connected through the connection member 110, thereby improving the planarization layer slope angle problem, while the data line connected to the first binding terminal 401 may be set as the second data line to maintain the original design. The design mode only needs to improve partial data lines, so that the cost is relatively low, and the required quantity of the first data lines and the second data lines can be reasonably designed according to the factors such as the size of a panel, the length of fan-out routing lines and the like.
According to the preparation method, through the novel signal wiring design, after the organic photoresist is formed, the wiring in the plane is connected with the fan-out wiring, the problem that the via hole slope angle of the organic photoresist layer above the first data line is large is solved, and the product yield is improved.
According to the above embodiment:
the application provides a display panel and a preparation method of the display panel, wherein the display panel comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer dielectric layer, a source drain electrode layer, a planarization layer and a connecting member; the active layer is formed on one side of the substrate; the grid insulating layer is formed on one side of the active layer far away from the substrate; the grid layer is formed on one side of the grid insulation layer far away from the active layer and is patterned to form a grid; the interlayer dielectric layer is formed on one side of the grid electrode layer far away from the grid electrode insulating layer; the source and drain electrode layer is formed on one side, far away from the grid layer, of the interlayer dielectric layer, a source electrode, a drain electrode and a plurality of data lines are formed in a patterning mode, each data line comprises an in-plane routing located in the display area and a fan-out routing located in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other; the planarization layer is formed on one side, away from the interlayer dielectric layer, of the source drain layer, and a through hole is formed in the planarization layer in the display area; the connecting component is formed on one side of the source drain layer far away from the interlayer dielectric layer and is respectively connected with the in-plane routing and the fan-out routing of each first data line. Through setting up an at least first data line in this application, and in the first data line in the face walk the line and fan-out walk the line and do not contact each other, then the planarization layer of first data line top is when toasting, the heat of fan-out walking the line can not transmit to in the face walk the line, the bank angle that is close to the via hole in the planarization layer in the fan-out district is normal, consequently, the rete formation in the follow-up processing procedure is difficult to produce the fracture when should cross downtheholely, and with the connecting means with the face of first data line walk the line and fan-out walk the line connection back, also can not influence the transmission of signal.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the method for manufacturing the display panel provided by the embodiment of the present application are described in detail above, and the principle and the implementation manner of the present application are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (9)
1. A display panel, comprising:
a substrate;
an active layer formed on one side of the substrate;
the gate insulating layer is formed on one side, far away from the substrate, of the active layer;
the grid electrode layer is formed on one side, far away from the active layer, of the grid electrode insulating layer, and a grid electrode is formed in a patterning mode;
the interlayer dielectric layer is formed on one side of the grid electrode layer, which is far away from the grid electrode insulating layer;
the source drain layer is formed on one side, far away from the gate layer, of the interlayer dielectric layer, and is patterned to form a source electrode, a drain electrode and a plurality of data lines, each data line comprises an in-plane routing in the display area and a fan-out routing in the fan-out area, each data line comprises at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other; the display panel further comprises a binding area connected with the fan-out area, the binding area is provided with binding terminals connected with the fan-out wiring, the binding terminals comprise first binding terminals close to the middle of the display panel and second binding terminals close to two sides of the display panel, the fan-out wiring of the first data line is connected with the first binding terminals, and the fan-out wiring of the second data line is connected with the second binding terminals;
the planarization layer is formed on one side, away from the interlayer dielectric layer, of the source drain layer, and a through hole is formed in the planarization layer in the display area;
and the connecting component is formed on one side of the source drain layer, which is far away from the interlayer dielectric layer, and is respectively connected with the in-plane routing and the fan-out routing of each first data line.
2. The display panel according to claim 1, wherein the display panel is a liquid crystal display panel, and further comprises a first electrode layer, an insulating layer, and a second electrode layer, which are stacked, the first electrode layer is formed on a side of the planarization layer away from the source drain layer, a plurality of first electrodes arranged in an array are formed by patterning, and the first electrodes are connected with in-plane routing lines of the data lines through via holes in the planarization layer.
3. The display panel according to claim 1, wherein the display panel is an OLED display panel, and further comprises a first electrode layer, a pixel defining layer, a light emitting material layer, and a second electrode layer, the first electrode layer is formed on a side of the planarization layer away from the source drain layer, and is patterned to form a plurality of first electrodes arranged in an array, and the first electrodes are connected to the drain electrodes through via holes in the planarization layer.
4. The display panel according to claim 2 or 3, wherein the connection member is the same material as the first electrode.
5. The display panel according to claim 2 or 3, wherein the connection member is different from the first electrode material.
6. The display panel according to claim 1, wherein the data lines are all first data lines.
7. A method for manufacturing a display panel, comprising:
providing a substrate;
sequentially preparing an active layer, a grid electrode insulating layer, a grid electrode layer and an interlayer dielectric layer on the substrate;
forming a source drain layer on one side of the interlayer dielectric layer away from the gate layer, and patterning to form a source electrode, a drain electrode and a plurality of data lines, wherein each data line comprises an in-plane routing in the display area and a fan-out routing in the fan-out area, the data lines comprise at least one first data line, and the in-plane routing and the fan-out routing of each first data line are not in contact with each other; the display panel further comprises a binding area connected with the fan-out area, the binding area is provided with binding terminals connected with the fan-out wiring, the binding terminals comprise first binding terminals close to the middle of the display panel and second binding terminals close to two sides of the display panel, the fan-out wiring of the first data line is connected with the first binding terminals, and the fan-out wiring of the second data line is connected with the second binding terminals;
forming a planarization layer on one side of the source drain layer, which is far away from the interlayer dielectric layer, wherein a through hole is formed in the display area by the planarization layer;
and forming a connecting member on one side of the source drain layer, which is far away from the interlayer dielectric layer, wherein the connecting member is respectively connected with the in-plane routing and the fan-out routing of each first data line.
8. The method for manufacturing a display panel according to claim 7, wherein the step of forming a connecting member on a side of the source drain layer away from the interlayer dielectric layer includes: and forming a first electrode layer on one side of the planarization layer, which is far away from the source drain layer, and patterning to form a plurality of first electrodes arranged in an array and the connecting member.
9. The method according to claim 7, wherein the step of forming a connecting member on a side of the source/drain layer away from the interlayer dielectric layer comprises: and respectively forming a first electrode layer and a connecting member on one side of the planarization layer, which is far away from the source drain layer, through two processes, wherein the first electrode layer is patterned to form a plurality of first electrodes arranged in an array.
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| CN202010399118.1A CN111446266B (en) | 2020-05-12 | 2020-05-12 | Display panel and preparation method thereof |
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| CN202010399118.1A CN111446266B (en) | 2020-05-12 | 2020-05-12 | Display panel and preparation method thereof |
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