CN111445872A

CN111445872A - Drive module, drive device and embedded touch control equipment

Info

Publication number: CN111445872A
Application number: CN202010115547.1A
Authority: CN
Inventors: 张盛东; 沈帅; 廖聪维; 杨激文
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2020-02-24
Filing date: 2020-02-24
Publication date: 2020-07-24
Anticipated expiration: 2040-02-24
Also published as: CN111445872B

Abstract

The application discloses a driving module, a driving device and an embedded touch device. The driving module includes: an input unit configured to acquire an input signal; an output unit configured to provide an output signal at an output node based on the input signal under the influence of the set of timing signals; a potential holding unit including a first node capacitively coupled to a first timing signal of the timing signal group and configured to hold an output node and a driving node of the output unit at a low potential through the first node, wherein the potential holding unit is further configured to: (i) storing the input signal at the first node by the timing signal group, and performing a charging operation to the driving node based on the stored input signal or the signal at the second node; or (ii) under the influence of the set of timing signals, storing the input signal at the second node and performing a charging operation to the drive node based on the signal at the first node.

Description

Drive module, drive device and embedded touch control equipment

Technical Field

The application belongs to the field of information display, and particularly relates to a driving module, a driving device and embedded touch equipment.

Background

The gate driver on array (GOA) has been widely used in TFT-L CD, and the GOA technology has the advantages of saving gate driver IC, reducing production cost, reducing space of fan-out routing, making the structure of the display screen more compact, and being beneficial to realizing narrow frame of the display screen.

The embedded touch display screen has the advantages of lighter and thinner structure. For the embedded touch technology, the touch detection function is integrated inside the liquid crystal display screen, so that a touch sensor does not need to be added outside the liquid crystal display screen. However, because the touch detection signal line is integrated in the display screen, the touch detection signal line and the display signal line are close to each other, and a large parasitic capacitance exists between the touch detection line and the display signal line; when the display and the touch detection are performed simultaneously, a signal crosstalk phenomenon is generated, that is, the touch detection precision and sensitivity are reduced due to the disturbance of the display driving signal, and meanwhile, the display frame is abnormal due to the touch detection.

The embedded touch screen generally adopts a strategy of performing display scanning and touch detection in a time-sharing manner, namely refreshing a display picture within one frame time is completed first, and then touch detection is completed by utilizing blank time between two frames. This method can effectively suppress crosstalk between touch detection and display signals, but has a limitation in that the touch detection frequency must be equal to the display refresh frequency. However, in order to improve the smoothness and accuracy of the touch operation, it is generally required to increase the frequency of touch detection to improve the sensitivity and accuracy of touch detection. In other words, the high-performance built-in touch screen requires multiple touch detections within one frame of display time, i.e. the touch detection frequency is greater than the display refresh frequency; therefore, multiple pauses are needed in the process of one-frame display scanning, touch detection is performed by utilizing the pause time, and display driving is continued after the touch detection is finished.

Disclosure of Invention

The application provides a drive module, drive module is nth level drive module in the drive module array, and it includes: an input unit configured to acquire an input signal; an output unit configured to provide an output signal at an output node based on the input signal under the influence of a set of timing signals; a potential holding unit including a first node capacitively coupled to a first timing signal of the timing signal group and configured to hold the output node and a driving node of the output unit at a low potential through the first node, wherein the potential holding unit is further configured to: (ii) (i) storing the input signal at the first node under the influence of the set of timing signals, and performing a charging operation to the drive node based on the stored input signal or a signal at a second node; or (ii) storing the input signal at the second node under the influence of the set of timing signals, and performing the charging operation to the drive node based on the signal at the first node.

The present application further provides a driving apparatus, including M driving modules, wherein the nth stage driving module includes: an input unit configured to acquire an input signal including an output signal of an N-1 th stage driving module; an output unit configured to provide an output signal at an output node based on the input signal under the influence of a set of timing signals; a potential holding unit configured to hold the output node and a driving node of the output unit at a low potential under the influence of the timing signal group, the potential holding unit being further configured to: (i) storing the input signal at the first node under the influence of the set of timing signals, and performing a charging operation to a driving node of the output unit based on the stored input signal or a signal at a second node; or (ii) store the input signal at the second node under the influence of the set of timing signals, and perform the charging operation to the drive node based on the signal at the first node; and a feedback unit configured to pull down a potential of the driving node to a low potential in response to a touch enable signal and an output signal of the (N +1) th-level driving module.

The application also provides an embedded touch control device, including: a display array which performs a display operation based on the first switching signal and the data signal transmitted on the display signal line; a touch array performing a touch detection operation based on the second switch signal and the touch detection line; and the driving device is coupled to the display signal line and the touch detection line to provide the first switch signal and the second switch signal under the influence of the timing signal group.

The present application also provides a driving method for a driving apparatus including M stages of driving modules as aforementioned, the method including: acquiring an input signal via the input unit to charge a driving node in the output unit; pulling down the potential of the driving node via the potential holding unit and storing the input signal; after touch detection is completed, the potential holding unit charges the driving node by using the stored input signal and provides the output signal at the output node; and deleting the stored input signal via the potential holding unit and holding the driving node and the output node at a low potential.

Drawings

Embodiments are shown and described with reference to the drawings. These drawings are provided to illustrate the basic principles and thus only show the aspects necessary for understanding the basic principles. The figures are not to scale. In the drawings, like reference numerals designate similar features.

FIG. 1 is a system block diagram of a drive module according to an embodiment of the present application;

FIG. 2a is a circuit diagram of a driving module according to a first embodiment of the present application;

FIG. 2b is a timing diagram of the driving module shown in FIG. 2 a;

FIG. 3a is a circuit diagram of a driving module according to a second embodiment of the present application;

FIG. 3b is a timing diagram of the driving module shown in FIG. 3 a;

FIG. 4a is a circuit diagram of a driving module according to a third embodiment of the present application;

FIG. 4b is a timing diagram of the driving module shown in FIG. 4 a;

FIG. 5 is a flow chart of a driving method according to an embodiment of the present application;

FIG. 6 is an architecture diagram of a drive device according to an embodiment of the present application;

fig. 7 is a structural diagram of an in-cell touch device according to an embodiment of the present disclosure.

Detailed Description

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the present application can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the application. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. For the connection between the units in the drawings, for convenience of description only, it means that at least the units at both ends of the connection are in communication with each other, and is not intended to limit the inability of communication between the units that are not connected. The number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the outputs provided, and is not intended to limit the communication between the two units to signals only as shown in the figure.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.

A transistor may refer to a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT). When the transistor is a field effect transistor, the transistor can be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, an organic transistor, or the like, depending on the channel material. An N-type transistor and a P-type transistor can be classified according to whether carriers are electrons or holes. The control electrode refers to a grid electrode of the field effect transistor, the first electrode can be a drain electrode or a source electrode of the field effect transistor, and the corresponding second electrode can be a source electrode or a drain electrode of the field effect transistor; when the transistor is a bipolar transistor, the control electrode of the transistor refers to a base electrode of the bipolar transistor, the first electrode may be a collector or an emitter of the bipolar transistor, and the corresponding second electrode may be an emitter or a collector of the bipolar transistor.

For the gate driving circuit of the multi-stage cascade, the first stage circuit is generally activated by one trigger signal, that is, the output signal of the nth stage gate driving circuit is used as the trigger signal of the (N +1) th stage gate driving circuit. In a conventional gate driving circuit, a gate scan signal is generated line by line and continuously during a complete one-frame display time. For the case that the touch detection frequency is greater than the display refresh frequency, the display scanning is suspended for multiple times corresponding to one frame of display time, i.e., the gate driving circuit is suspended for multiple times in different display rows. And after the touch detection is finished, starting from the pause position of the display scanning, and restarting the display scanning. Therefore, during the pause period of the display scanning, the pause line or the gate driving circuits in the front and rear stages of the pause line should have the capability of storing the "transfer" charge/voltage, so as to trigger and start the subsequent gate circuit to continue scanning by using the stored "transfer" charge/voltage after the touch detection is finished.

In the prior art, the gate node of the transistor is driven by the GOA circuit to store the charge for starting the "transfer". The applicant has studied and found that, firstly, the driving capability of the GOA circuit is directly related to the bias condition of the driving transistor, and long-term charge/voltage retention will cause the electrical characteristics of the driving transistor to drift, i.e. the transfer characteristics and output characteristics of the driving transistor cannot be maintained constant due to electrical stress. Secondly, in the touch sensing process, only a few driving transistors of the conventional GOA circuit are turned on for a long time, and most driving transistors in the gate driving circuit are kept in an off state, which causes the difference of different driving capabilities in the gate driving circuit, and finally causes the abnormality of the displayed picture.

In view of the above problems, the present application provides a driving circuit that can perform both display refresh and touch detection in a time-sharing manner (the touch detection frequency is higher than the display refresh frequency), and the driving circuit can also meet the requirement of storing "transfer" start-up charges without causing characteristic differences of driving transistors of different stages. The driving module keeps the electric charge at the grid electrode of the non-driving transistor in the touch detection stage, and can restart the grid electrode driving circuit after the touch detection is finished, so that the driving module is suitable for application scenes with high touch detection frequency.

The following description will be given taking an nth-stage driver module as an example, where the driver module is a driver array including M driver modules, and fig. 1 is a system block diagram of a driver module according to an embodiment of the present application.

The driving module 10 includes an input unit 11, an output unit 12, a feedback unit 13, and a potential holding unit 14. The input signal reaches the output unit 12 and the potential holding unit 14 via the input unit 11. Under the influence of the set of timing signals, the output unit 12 provides an output signal at an output node based on the input signal. The potential holding unit 14 includes a node P_N(not shown), node P_NCapacitively coupled (e.g., via a capacitor) to a timing signal in the set of timing signals and through node P_NTo connect the output node and the driving node Q of the output unit_NRemains at a low potential. The timing signal group is a combination of timing signals required for each circuit, and is different for different circuits.

In one embodiment, the potential holding unit 14 is at the node P under the influence of the set of timing signals_NStoring the input signal and based on the stored input signal or in the potential holding unit 14Node B_NTo drive node Q_NThe charging operation is performed. In another embodiment, at the node B under the influence of a set of timing signals_NStore the input signal and is based on the node P_NTo drive node Q_NThe charging operation is performed.

When detecting touch, the feedback unit 13 receives the touch enable signal TE to turn off the output unit 12 under the control of the touch enable signal TE, so that the output unit outputs a low voltage level. It is understood that the potential holding unit 14 is used for holding the input signal (charge) and maintaining the off state of the output unit 12, i.e. maintaining the output unit 12 outputting a low potential.

For a plurality of cascaded driving modules, the input signal received by the input unit 11 includes the output signal of the N-1 th driving module; the feedback unit 13 also receives the output signal of the (N +1) th stage driving module to drive the node Q under the influence of the signal_NAnd the scanning voltage is pulled down to a low potential, so that the function of progressive scanning is realized.

After the touch detection is finished, the potential holding unit 14 recharges the output unit 12 by using the saved input signal. After the recharging is completed, the output unit 12 provides the output signal G at the high potential_N. Subsequently, the output signal is flipped from high to low by the clock signal and the feedback unit 13.

With the drive module of the present application, it is possible to store an input signal charge in the low potential holding unit, and to reduce the complexity of the circuit configuration by multiplexing the potential holding unit 14 in a time-sharing manner.

Fig. 2a is a circuit diagram of a driving module according to a first embodiment of the present application, and fig. 2b is a timing diagram of the driving module in fig. 2 a.

As shown in fig. 2a, the input unit 21 comprises a transistor T21 having a control electrode and a first electrode coupled to receive the input signal G_N-1. The control electrode of the transistor T22 in the output unit 22 is coupled to the second electrode of the transistor T21 to receive the input signal G_N-1And the control electrode of transistor T22 is coupled to its own second electrode via capacitor C21 to provide an outputSignal G_N. The feedback unit 23 comprises a first feedback branch comprising a transistor T23 and a second feedback branch comprising a transistor T28 coupled at a driving node Q_NAnd a low potential V L, and a gate of transistor T23 receives signal G_N+1The control electrode of the transistor T28 receives the touch enable signal TE. The control electrode of the transistor T24 in the potential holding unit 24 is coupled to the control electrode of the transistor T22, and the control electrode of the transistor T29 receives the input signal Q_N-1A first pole of the transistor T25 is coupled to the control pole of the transistor T22, a second pole of the transistor T3526 receives the clock signal CK1, transistors T26, T27 are coupled between the transistor T22 and the low potential V L, and a control pole of the transistor T26 is coupled to the control pole of the transistor T25, a control pole of the transistor T27 receives the clock signal CK 1.

The operation of the driving module in fig. 2a is described below with reference to the timing sequence in fig. 2 b.

T1: starting phase

At this stage, the signal G is input_N-1And Q_N-1At the same time, the clock signal CK1 and the reset signal RST are high, turning on the transistors T21 and T29, respectively, and further turning on the node Q_NAnd P_NAnd charging is carried out. At node P_NAfter the potential rises, the voltage is synchronously supplied to Q through a transistor T25_NThe node is charged. The clock signal CK1 is high, which turns on the transistor T27 to pull down the output signal G_N。

T2: touch detection stage

At this stage, the clock CK1 toggles low, Q_N-1High, transistor T29 is turned on continuously, and node P is turned on_NThe high potential is maintained. At this time, the transistor T25 is turned on, and the node Q is low since the clock signal CK1 is low at this time_NIs pulled down to a low potential. Since the TE signal is high, the node Q of each stage of the driving module is at this time_NAre all pulled low and touch detection begins.

Understandably, due to Q_NAnd Q_N-1Are all low, therefore, at this stage, node P_NThe node will remain high.

T3: restart phase

At this stage, the touch enable signal TE becomes a low potential, the transistor T28 is turned off, and the touch detection is ended. The clock signal CK1 goes high because of the node P_NIs high, and therefore, the node Q can be given by the transistor T25_NPerforms recharging, node Q_NMakes the transistor T24 turned on. Since the reset signal RST becomes low at 3/4CK1 pulse time, the transistor T24 pulls down the node P_NThereby turning off the transistor T25. The clock signal CK1 becomes low after the pulse time, and the recharging is terminated.

T4: bootstrapping phase

At this stage, the clock signal CK2 goes high, providing an output signal G at a high level at the second pole of the transistor T22_NMeanwhile, node Q is coupled by capacitor C21_NIs bootstrapped to a higher potential V_QNFurther, the transistor T24 keeps the node PN at a low level, avoiding P_NThe node is coupled by a capacitor C22, reducing the output signal G of transistor T25_NThe influence of (c).

T5: pull-down phase

At this stage, the clock signal CK2 becomes low, and the output signal G_NThen becomes a low potential, node Q_NAnd the bootstrap is finished. In the interval time of the clock signals CK1 and CK2, CK1 and CK2 are both low, so G is low at this time_NPulled low by transistor T22.

T6: low potential hold phase

At this stage, the clock signal CK1 and the output signal G of the N +1 th stage_N+1High, pulling node Q low by turning transistor T23 on_NThe potential of (2). The clock signal CK1 turns on the transistor T27, thereby enabling the output signal G_NIs pulled down to a low potential. When the clock signal CK2 changes from low to high, the node P_NCoupling at capacitor C22Is pulled up to a high potential by the lower node, so that the transistors T25 and T26 are turned on to connect the node Q of the stage circuit_NAnd an output signal G_NIs pulled down and held at a low potential. Thus, at this stage, transistors T26 and T27 are at node P_NIs alternately turned on by the clock signal CK1 to output a signal G_NAnd is maintained at a low potential during this phase.

As can be seen from the above, the potential holding unit not only has the function of holding charges, but also can be used to restart the driving module.

Fig. 3a is a circuit diagram of a driving module according to a second embodiment of the present application, and fig. 3b is a timing diagram of the driving module in fig. 3 a.

As shown in fig. 3a, the input unit 31 comprises a transistor T31 having a control electrode and a first electrode coupled to receive the input signal G_N-1. The control electrode of the transistor T32 in the output unit 32 is coupled to the second electrode of the transistor T31 to receive the input signal G_N-1And the control electrode of transistor T32 is coupled to the second electrode via capacitor C31 to provide an output signal G at the second electrode_NThe transistors T33, T39 in the feedback unit 33 are coupled between the transistor T31 and the low potential V L, and the control electrode of the transistor T33 receives the signal G_N+1The control electrode of the transistor T38 receives the touch enable signal TE.

A control electrode of the transistor T37 in the potential holding unit 34 receives the clock signal CK1 and is coupled to the low potential V L via the capacitor C33, a control electrode of the transistor T38 is coupled to the node BN between the transistor 37 and the capacitor C33, a first electrode is coupled to the control electrode of the transistor 34, a second electrode receives the complex charging clock signal XCK1, a control electrode of the transistor T34 is coupled to a first electrode of the transistor T38 and is coupled to a first electrode of the transistor T32 via the capacitor C32, a first electrode of the transistor T34 is coupled to a control electrode of the transistor T32 and a second electrode receives the complex charging clock signal XCK2, the transistors T35, T36 are coupled between the transistor T32 and the low potential V L, and a control electrode of the transistor T35 is coupled to a control electrode of the transistor T34, and a control electrode of the transistor T36 receives the clock signal CK 1.

The operation of the drive module of fig. 3a is explained below with reference to the timing sequence of fig. 3 b.

t 1: starting phase

At this stage, the signal G is input_N-1(i.e., the output signal of the previous stage) and the clock signal CK1 are high, so that the transistors T31, T36, and T37 are turned on. Transistor T31 giving node Q_NCharging to a high voltage level, the driving transistor T32 is turned on, the transistor T36 pulls the output signal G low_N. After the transistor T37 is turned on, it is connected to the terminal B_NThe capacitance C33 of the node begins to charge.

t 2: touch detection stage

At this stage, the touch enable signal TE is at a high level, the clock signals CK1 and CK2 are at a low level, and the high touch enable signal TE turns on the transistor T39, thereby pulling down the control electrode potential of the driving transistor T22, suspending the display and performing the touch detection. Only node BN remains high during this touch detection phase, while charge remains on capacitor C33.

t 3: restart phase

At this stage, the touch enable signal TE becomes low, the transistor T39 is turned off, the touch sensing is ended, the recharging signal XCK1 becomes high, and the transistor T38 causes P to be turned on_NThe node charges to a high potential. The recharging signals XCK1 and XCK2 have a time interval T1, and XCK2 becomes high after XCK1 becomes high for a time T1, and the node Q is supplied through a transistor T34_NAnd then charged to a high potential. The charge-reset signal XCK1 then goes low, node P due to the high potential at the gate (node BN) of the transistor T38_NIs pulled low, then XCK2 becomes low, and the recharging is finished.

t 4: bootstrapping phase

At this stage, the clock signal CK2 goes high, so the transistor T32 outputs high at the second pole, and the signal G is output_NAt this time, at a high potential. Node Q_NIs bootstrapped to a higher potential V_QNAt this stage, the node P_NIs pulled low by the node BN through the transistor T38 to keep the low potential and avoid the node P_NCoupled by capacitor C32, ensures that the output is not affected by transistor T35.

t 5: pull-down phase

At this stage, the clock signal CK2 goes low, and the node Q_NAfter the bootstrap is finished, the voltage returns to the high level, and in the interval T2 between CK2 and CK1, since both CK1 and CK2 are at the low level, the output signal G is at this time_NPulled low by transistor T32.

t 6: low potential hold phase

At this stage, the signal G_N+1And CK1 is high, therefore, G_N+1So that the transistor T33 is turned on to pull down the node Q_NCK1 turns on transistor T36 to pull down the output signal G_N(CK2 is low at this time). In other words, node Q_NAnd an output signal G_NIs pulled down to a low potential. When the clock signal CK2 is high, the node P is enabled by the coupling effect of the capacitor C32_NReaches high potential to turn on the transistors T34 and T35, thereby turning on the Q of the stage circuit_NNode and output G_NIs pulled down and remains at a low potential. When the clock signal CK1 is high, the transistor T36 is turned on to output a signal G_NIs maintained at a low potential. Thus, the signal G is outputted in the whole low potential holding stage_NAre maintained at a low potential.

Fig. 4a is a circuit diagram of a driving module according to a third embodiment of the present application, and fig. 4b is a timing diagram of the driving module in fig. 4 a.

As shown in FIG. 4a, the input unit 41 comprises transistors T41 and T43, the gates of which receive the input signal G, respectively_N-1And G_N+1The first pole receives power signals U2D and D2U, respectively, where U2D and D2U are two voltage sources with opposite polarities, i.e., when U2D is high, D2U is low.

The control electrode of the transistor T42 in the output unit 42 is coupled to the second electrode of the transistor T41/T43, the first electrode receiving the clock signal CK2, the second electrode being coupled to its control electrode via the capacitor C41 and the transistor C48, wherein the control electrode of the transistor T48 receives the clock signal CK 2. At the input signal G_N-1Or G_N+1The transistor T41 or T43 supplies the power supply signals U2D and D2U to the transistor T42. In the feedback unit 43Is coupled between the second poles of the transistors T41 and T43 and the low potential V L, and the control pole of the transistor T47 receives the touch enable signal TE.

The transistor T44 in the potential holding unit 44 has a first pole coupled to the control pole of the transistor 22 and a second pole coupled to the first pole of the transistor T42 via the capacitor C42 to receive the second clock signal C42. The control electrode of the transistor T46 is coupled to the node P via a capacitor C43_NThe first pole is coupled to a node Q_NThe second pole receives a complex charging clock signal XCK; the control electrode of the transistor T45 is coupled to the node P_NA first pole coupled to the control pole (node B) of the transistor T46_N) And the second pole receives the complex charging clock signal XCK. A control electrode of the transistor T49 is coupled to the second electrode of the transistor T48, a first electrode is coupled to the node P_NAnd the second pole receives the touch enable signal TE. The control electrode of the transistor T410 is coupled to the node P_NThe control electrode of the transistor T411 is coupled to the clock signal CK1, the first electrodes of the two transistors are coupled to the second electrode of the transistor T42, and the second electrode is coupled to the low potential V L.

The operation of the drive module of fig. 4a is described below with reference to the timing sequence of fig. 4 b.

t 1: starting phase

At this stage, the input signal is the output signal G of the previous stage_N-1And the clock signal CK1 is high, turning on the transistors T41, T44 and T411, wherein the transistor T41 charges the node QN to high, turns on the driving transistors T42 and T411, and further pulls down the output signal G_N. After transistor T44 turns on, the connection is connected to P_NThe capacitance C42 of the node begins to charge.

t 2: touch detection stage

At this stage, the touch enable signal TE is at a high level, the clock signals CK1 and CK2 are at a low level, and TE turns on the transistor T47, thereby pulling down the gate of the driving transistor T42 to suspend the display and perform the touch detection. In the touch detection stage, only the node P_NHeld at a high potential with charge held on capacitor C42.

t 3: restart phase

At this stage, the touch enable signal TE becomes low, the transistor T47 is turned off, the touch sensing is ended, the recharging signal XCK becomes high, the transistor T45 charges the node BN to high, and the transistor T46 is turned on to charge the node Q_NAnd (6) charging. When the recharge signal XCK becomes low, the transistor T45 pulls the node BN low, and the recharge is completed.

t 4: bootstrapping phase

At this stage, the clock signal CK2 becomes high, and the transistor T42 outputs a high potential G_NNode Q_NIs bootstrapped to a higher potential V_QN. Due to the output signal G_NHigh, the transistor T49 is turned on, and the node P is pulled down_NE.g. node P_NKept at a low potential, reducing the capacitance C42 to the node P_NTo ensure the output signal G_NIs not affected by the transistor T410.

t 5: pull-down phase

At this stage, the clock signal CK2 goes low, and the node Q_NThe bootstrap is finished, the voltage returns to the high level, and CK1 and CK2 are both low level in the interval time of the clock signals CK2 and CK1, so that the output signal G is at this time_NPulled low by transistor T42.

t 6: low potential hold phase

At this stage, the signal G is input_N+1And the clock signal CK1 is high, therefore, the transistor T43 turns on and pulls down the node Q_NTransistor T411 turns on and pulls down the output signal G_N. When the clock signal CK2 is high, the node P is coupled via the capacitor C42_NTo a high potential, the transistors T48 and T410 are thus turned on, turning on the node Q_NAnd an output signal G_NRemains at a low potential. When the clock signal CK1 is high, the transistor T411 is turned on to output the signal G_NIs maintained at a low potential. Therefore, throughout the low potential holding period, the output G_NAre maintained at a low potential.

Fig. 5 is a flowchart of a driving method according to an embodiment of the present application.

In step S501, an input signal is acquired via an input unit, and a driving node in an output unit is charged. In step S502, the potential of the driving node is pulled down via the potential holding unit, and the input signal is stored at a specified node. In step S503, after the touch detection is completed, the driving node is charged with the stored input signal via the voltage holding unit, and an output signal is provided at the output node. In step S504, the stored input signal is deleted via the potential holding unit, and the driving node and the output node are held at a low potential.

Based on the foregoing driving module, the present application also provides a driving device, wherein fig. 6 is an architecture diagram of the driving device according to an embodiment of the present application.

As shown in the figure, the driving device comprises M cascaded driving modules, and the input end of the Nth stage driving module receives the output signal G of the N-1 th stage driving module_N-1(ii) a The input ends FB1 and FB2 of two feedback branches of the feedback unit respectively receive the output signal G of the (N +1) th stage driving module_N+1And a touch enable signal TE.

For the Nth-stage driving module, the input unit at least acquires the output signal G of the Nth-1-stage driving module_N-1(ii) a The output unit is to provide an output signal at an output node based on the input signal under the influence of the set of timing signals. The potential holding unit is configured to hold the output node and a driving node of the output unit at a low potential, and under the influence of the timing signal group, it is at a node P_NStoring the input signal and based on the stored input signal or node B_NThe signal at (b) performs a charging operation to a driving node of the output unit; or at node B under the influence of a set of sequential signals_NStore the input signal and is based on the node P_NThe signal at (b) performs a charging operation to the driving node. The feedback unit responds to the touch control enabling signal TE and the output signal G of the (N +1) th level driving module_N+1And the potential of the driving node is pulled down to a low potential.

Fig. 7 is a structural diagram of an in-cell touch display device according to an embodiment of the present disclosure.

The in-cell touch device 700 includes a display array 710, a touch array 720, and a driving device 730, wherein the display array 710 performs a display operation based on a first switching signal and a data signal Vdata transmitted on a display signal line; the touch array performs a touch detection operation based on the second switch signal and the touch detection line to detect the touch signal Vtouch. The driving device 730 is coupled to the display signal line and the touch detection line to provide a first switching signal and a second switching signal under the influence of the timing signal group.

While the present application has been described with reference to specific examples, which are intended to be illustrative only and not to be limiting of the application, it will be apparent to those of ordinary skill in the art that changes, additions or deletions may be made to the disclosed embodiments without departing from the spirit and scope of the application.

Claims

1. A drive module that is an nth level drive module in a drive array, comprising:

an input unit receiving an input signal;

an output unit providing an output signal at an output node based on the input signal under the action of the time series signal group;

a potential holding unit including a first node (P)_N) A first node capacitively coupled to a first timing signal (CK2) of the set of timing signals and configured to hold the output node and a driving node of the output unit at a low potential through the first node, wherein the potential holding unit is further configured to:

(i) storing the input signal at the first node under the influence of the set of timing signals, and based on the stored input signal or a second node (B)_N) The signal at (a) performs a charging operation to the driving node; or

(ii) Storing the input signal at the second node by the timing signal group, and performing the charging operation to the driving node based on the signal at the first node.

2. The driving module of claim 1, wherein the first node is coupled to the driving node via a first transistor (T25, T34, T45) and to the output node via a second transistor (T26, T35, T410), wherein the first transistor further receives a second timing signal (CK2, XCK2, XCK) of the set of timing signals to perform the charging operation.

3. The driving module of claim 2, wherein the potential holding unit further comprises:

a third transistor (T27, T36, T411) having a first pole coupled to the output node, a second pole coupled to a low potential, and a control pole coupled to a third timing signal (CK 1).

4. A driver module as claimed in claim 3, wherein the first node is coupled to a control electrode of a fourth transistor (T46) via the first transistor and the fourth transistor is coupled to the driver node, wherein the fourth transistor also receives the second timing signal (XCK).

5. The driving module of claim 3, wherein the potential holding unit further comprises:

a fifth transistor (T24) having a control electrode coupled to the driving node, a first electrode coupled to the first node, a second electrode receiving a Reset Signal (RST),

a sixth transistor (T29) having a gate receiving the first control signal (Q)_N-1) A first pole coupled to the first node, and a second pole receiving the Reset Signal (RST), wherein the first control signal is a potential of a driving node in the N-1 th driving module.

6. The driving module of claim 3, wherein the potential holding unit further comprises:

a seventh transistor (T38) having a first pole coupled to the first node, a second pole receiving a fourth timing signal (XCK1), and a control pole coupled to the second node;

an eighth transistor (T37) having a first pole coupled to the driving node, a second pole coupled to the second node, a control pole coupled to the third timing signal (CK1),

wherein the input signal is stored at the second node under the influence of the first and second timing signals, wherein the second node is capacitively coupled to the low potential.

7. The driving module of claim 3, wherein the potential holding unit further comprises:

a ninth transistor (T44) having a first pole coupled to the driving node, a second pole coupled to the first node, and a control pole receiving the third timing signal (CK 1).

8. The driving module of claim 5 or 6, wherein the input unit comprises:

a tenth transistor having a control electrode coupled to the first electrode for receiving the input signal and a second electrode coupled to the driving node.

9. The driving module of claim 8, wherein the input unit comprises:

an eleventh transistor (T41) having a control electrode receiving a second control signal, a first electrode receiving the first power signal, and a second electrode coupled to the driving node, wherein the second control signal is an output signal of the N-1 th stage driving module;

and a twelfth transistor (T43) having a control electrode receiving a third control signal, a first electrode receiving the second power signal, and a second electrode coupled to the driving node, wherein the third control signal is an output signal of the (N +1) th stage driving module.

10. The drive module of claim 1, further comprising:

a feedback unit coupled between the driving node and a low potentialBased on a fourth control signal (TE) and/or a third control signal (G)_N+1) To bring the driving node to the low potential.

11. The driving module of claim 10, wherein the feedback unit comprises:

a first feedback branch that causes the driving node to be at the low potential under the influence of the second control signal;

a second feedback branch at the third control signal (G)_N+1) Under the influence of (b), the driving node is at the low potential, wherein the third control signal is an output signal provided by the driving module of the (N +1) th stage.

12. The driving module of claim 1, wherein the output unit comprises:

a twelfth transistor (T22, T32, T42) having a control electrode coupled to the driving node, a first electrode for receiving the first timing signal, a second electrode coupled to the output node and capacitively coupled to the driving node.

13. A driving apparatus includes M driving modules, wherein an Nth stage driving module includes:

an input unit configured to acquire an input signal including an output signal (G) of the N-1 th stage driving module_N-1)；

An output unit configured to provide an output signal at an output node based on the input signal under the influence of a set of timing signals;

a potential holding unit configured to hold the output node and a driving node of the output unit at a low potential under the influence of the timing signal group, the potential holding unit being further configured to:

(i) storing the input signal at the first node under the influence of the set of timing signals, and based on the stored input signal or a second node (B)_N) To said output unitDriving the node to perform a charging operation; or

(ii) Storing the input signal at the second node under the influence of the set of timing signals, and performing the charging operation to the driving node based on the signal at the first node; and

a feedback unit configured to respond to a touch enable signal (TE) and an output signal (G) of the N +1 th stage driving module_N+1) And pulling down the potential of the driving node to a low potential.

14. An in-cell touch device, comprising:

a display array which performs a display operation based on the first switching signal and the data signal transmitted on the display signal line;

a touch array performing a touch detection operation based on the second switch signal and the touch detection line; and

the driving apparatus of claim 13, coupled to the display signal line and the touch detection line to provide the first switch signal and the second switch signal under the influence of the timing signal group.

15. A driving method for a driving apparatus including M stages of the driving module according to claim 1, the method comprising:

acquiring an input signal through the input unit, and charging a driving node in the output unit;

pulling down the potential of the driving node via the potential holding unit and storing the input signal at a designated node;

after touch detection is completed, the potential holding unit charges the driving node by using the stored input signal and provides the output signal at the output node; and

deleting the stored input signal via the potential holding unit, and holding the driving node and the output node at the low potential.