KR20200071206A - Scan driver and display device having the same - Google Patents

Abstract

The present invention relates to a scan driver and a display device including the same. The scan driver includes a plurality of stages each outputting a scanning signal, wherein the n^th (where n is a natural number) stage includes: a first driving control unit controlling a voltage of a first node and a voltage of a second node in response to a previous carry signal; a second driving control unit configured to control a voltage of the first driving node based on a sensing-on signal, a next carry signal, a voltage of a first power source, a voltage of the first node, and a voltage of a sampling node, and control a voltage of a second driving node based on the voltage of the sampling node and a sensing clock signal; an output buffer unit including a first output buffer unit configured to output a k^th (where k is a natural number) clock signal as a carry signal in response to the voltage of the first node and the voltage of the second node, a second output buffer unit configured to output a k^th scan clock signal as the scan signal in response to the voltage of the first driving node and the voltage of the second driving node, and a third output buffer unit configured to output a k^th sensing clock signal as a sensing signal in response to the voltage of the first driving node and the voltage of the second driving node; and a connection control unit electrically connecting the first node to the first driving node, and the second node to the second driving node, in response to a display-on signal.

Description

SCAN DRIVER AND DISPLAY DEVICE HAVING THE SAME

The present invention relates to a scanning driver and a display device including the same.

The display device includes a display panel, a scan driver, a data driver, and a timing driver. The scan driver provides a scan signal to the display panel through scan lines. To this end, the scan driver includes stage circuits for sequentially connected scan signal output, and each of the stage circuits is configured and operated with a plurality of oxide thin film transistors.

Recently, the display device performs driving to compensate for deterioration or change in characteristics of the driving transistor outside the pixel circuit by sensing the threshold voltage or mobility of the driving transistor included in the pixel circuit. At this time, scan methods for the display operation, the mobility sensing operation, and the threshold voltage sensing operation are different. Research is being conducted on a scan driver and a stage circuit thereof to minimize the complexity of the circuit while stably performing various operations.

One object of the present invention is to provide a scan driver that uses respective clock signals for generating scan signals, sensing signals, and carry signals.

Another object of the present invention is to provide a display device including the scan driver.

However, the object of the present invention is not limited to the above-described objects, and may be variously extended without departing from the spirit and scope of the present invention.

The scan driver according to an embodiment of the present invention includes a plurality of stages for respectively outputting a scan signal, and the nth (where n is a natural number) stage includes a voltage and a first node in response to a previous carry signal. Control the voltage of the first driving node based on the first driving control unit that controls the voltage of the two nodes, the sensing on signal, the carry signal after, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node , A second driving control unit that controls a voltage of the second driving node based on the voltage of the sampling node and a sensing clock signal, and a k (in response, k is in response to the voltage of the first node and the voltage of the second node) Natural number) A first output buffer unit outputting a clock signal as a carry signal, and a second output buffer outputting a k-th scan clock signal as the scan signal in response to the voltage of the first drive node and the voltage of the second drive node. In response to an output buffer unit and a display-on signal including a third output buffer unit configured to output a k-th sensing clock signal as a sensing signal in response to a voltage of the first driving node and the voltage of the second driving node, And a connection control unit electrically connecting the first node, the first driving node, and the second node and the second driving node, respectively.

In addition, the k-th scan clock signal and the k-th sensing clock signal may have the same waveform synchronized with the k-th clock signal.

In addition, one frame period includes a display period and a vertical blank period, and in the display period, the sensing on signal may be supplied to at least k stages of the stages.

Further, the at least k stages output the scan signal in response to the k-th scan clock signal and output the sensing signal in response to the k-th scan clock signal in the vertical blank period following the display period. It can be characterized by.

In addition, the at least k stages may be characterized by outputting the scan signal at least twice during the vertical blank period.

Also, the at least k stages may output the sensing signal at least once during the vertical blank period.

In addition, the output of the scan signal may be characterized in that it overlaps the output of the sensing signal.

In addition, the first driving control unit is a first transistor that is connected between the first power supply terminal to which the first power is applied and the first node, and the gate electrode receives the previous carry signal or the scan start signal. Second and third transistors connected in series between one node and the carry output terminal, and fourth transistors connected between the first node and the carry output terminal and receiving a carry signal after the gate electrode, the fourth a fifth transistor connected between a first clock terminal to which a clock signal different from a k clock signal is applied and the second node, and a gate electrode connected to the first node, and the first power terminal to which the first power is applied And a sixth transistor connected between the second node and a gate electrode connected to the first clock terminal, and a seventh transistor diode-connected between the first power terminal and the second node. Can be.

In addition, the second driving control unit is connected between the first input terminal to which the carry signal is applied and the sampling node, and an eighth transistor through which a gate electrode receives the sensing on signal and the sensing clock signal are applied. Third and third nodes between the ninth and tenth transistors and the ninth and tenth transistors are connected in series between the sensing clock terminal and the first driving node, and gate electrodes are commonly connected to the sampling node. It may be characterized in that it comprises an eleventh transistor connected between the output terminal of the carry signal and a gate electrode connected to the first driving node.

In addition, when the sensing clock signal is supplied, the eleventh transistor may supply the voltage of the first power supply to the third node in response to the voltage of the first driving node.

In addition, the second driving control unit is connected in series between the second power terminal to which the second power is applied and the capacitor connected between the sampling node and the third power terminal to which the third power is applied and the second driving node. Further comprising the twelfth and thirteenth transistors, the twelfth transistor includes a gate electrode for receiving the sensing clock signal, and the thirteenth transistor comprises a gate electrode connected to the sampling node. Can be.

In addition, the first output buffer unit may be connected between a second clock terminal to which the k-th clock signal is applied and a carry output terminal, and a 14th transistor and a carry output terminal to which a gate electrode is connected to the first node. It may be characterized in that it comprises a 15th transistor connected between the second power supply terminal to which power is applied, and a gate electrode connected to the second node.

In addition, the second output buffer unit includes a 16th transistor and a third power supply connected between a scan clock terminal to which the kth scan clock signal is applied and a first output terminal, and a gate electrode connected to the first driving node. It may be characterized in that it comprises a 17th transistor connected between the applied third power terminal and the first output terminal, the gate electrode is connected to the second driving node.

In addition, the third output buffer unit is connected between a sensing clock terminal to which the k-th sensing clock signal is applied and a second output terminal, and a 21st transistor and the third power source having a gate electrode connected to the first driving node. It may be characterized in that it further comprises a second transistor connected between the third power terminal and the second output terminal to which it is applied, and a gate electrode connected to the second driving node.

In addition, the connection control unit is connected between the first node and the first driving node, and a gate electrode is connected between the 18th transistor receiving the display-on signal and the second node and the second driving node. The gate electrode may include a 19th transistor receiving the display-on signal.

In addition, the display device according to an exemplary embodiment of the present invention supplies scanning signals and sensing signals to the plurality of pixels, the scanning lines, and the lead-out lines, respectively, which are connected to the scanning lines, the lead-out lines, and the data lines, respectively. In order to do this, a scan driver including a plurality of stages is provided, wherein the nth stage (where n is a natural number) among the plurality of stages is configured to set the voltage of the first node and the voltage of the second node in response to a previous carry signal. The voltage of the first driving node connected to the first node is controlled based on the first driving control unit, the sensing on signal, the carry signal, the voltage of the first power supply, the voltage of the first node, and the voltage of the sampling node. A second driving control unit controlling and controlling the voltage of the second driving node based on the voltage of the sampling node and the sensing clock signal, in response to the voltage of the first node and the voltage of the second node (k, k is a natural number) a first output buffer unit outputting a clock signal as a carry signal, a second outputting a k scan clock signal as the scan signal in response to the voltage of the first drive node and the voltage of the second drive node In response to an output buffer unit and a display on signal, an output buffer unit and a third output buffer unit to output the k-th sensing clock signal as a sensing signal in response to the voltage of the first driving node and the voltage of the second driving node Thus, it may be characterized in that it comprises a connection control unit for electrically connecting each of the first node and the first driving node and the second node and the second driving node.

In addition, the k-th scan clock signal and the k-th sensing clock signal may have the same waveform synchronized with the k-th clock signal.

Further, one frame period includes a display period and a vertical blank period, and in the display period, the sensing-on signal is supplied to at least k stages of the stages, wherein the at least k stages continue to the display period In the vertical blank period, the scan signal may be output in response to the k-th scan clock signal, and the sensing signal may be output in response to the k-th sensing clock signal.

In addition, a sensing voltage may be supplied to pixel rows corresponding to the at least k stages during a period in which the scanning signal and the sensing signal overlap within the vertical blank period.

In addition, a sensing current may be supplied to pixel rows corresponding to the at least k stages in a period in which the scan signal and the sensing signal do not overlap within the vertical blank period.

The scan driver according to embodiments of the present invention can sense a plurality of pixel rows during a vertical blank period by outputting a scan signal and a sensing signal using respective clock signals for generating a scan signal, a sensing signal, and a carry signal. To make.

In addition, the reliability of the display device is improved by including the scan driver in the display device according to embodiments of the present invention, and a problem of insufficient data voltage charging rate of a high resolution display device having a 4k UHD quality or higher can be improved.

However, the effects of the present invention are not limited to the above-described effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a display device according to some example embodiments of the present invention.
2 is a view showing a scan driver according to embodiments of the present invention.
3 is a circuit diagram illustrating a first embodiment of a stage included in the scan driver of FIG. 2.
4 is a timing diagram showing an example of driving of the stage of FIG. 3.
5 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1.
6 is a circuit diagram illustrating a second embodiment of a stage included in the scan driver of FIG. 2.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and in the following description, when a part is connected to another part, this is not only a case where it is directly connected. It also includes a case in which the other elements are electrically connected with another element therebetween. In addition, in the drawings, parts not related to the present invention have been omitted in order to clarify the description of the present invention, and like reference numerals have been assigned to similar parts throughout the specification.

1 is a block diagram illustrating a display device according to some example embodiments of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display unit 100 including a plurality of pixels PX, a scan driving unit 210, a data driving unit 220, a sensing unit 230, and Timing control unit 240 may be included.

The timing controller 240 may generate a scan driving control signal and a data driving control signal based on signals input from the outside. The scan driving control signal generated by the timing control unit 240 may be supplied to the scan driving unit 210, and the data driving control signal DCS may be supplied to the data driving unit 220.

The scan driving control signal may include a plurality of clock signals CLK1 to CLK4, SC_CLK1 to SC_CLK4, SS_CLK1 to SS_CLK4 and a scan start signal STV. The scan start signal STV may control the output timing of the first scan signal.

The plurality of clock signals CLK1 to CLK4, SC_CLK1 to SC_CLK4, and SS_CLK1 to SS_CLK4 supplied to the scan driver 210 include first to fourth clock signals CLK1 to CLK4, and first to fourth scan clock signals SC_CLK1 to SC_CLK4) and first to fourth sensing clock signals SS_CLK1 to SS_CLK4. The first to fourth clock signals CLK1 to CLK4 may be used to shift the scan start signal STV. The first to fourth scan clock signals SC_CLK1 to SC_CLK4 may be used to output a scan signal corresponding to at least one of the scan start signal STV and the first to fourth clock signals CLK1 to CLK4. The first to fourth sensing clock signals SS_CLK1 to SS_CLK4 may be used to output a sensing signal in response to at least one of the scan start signal STV and the first to fourth clock signals CLK1 to CLK4. In addition, the scan driver 210 may be provided with other clock signals in addition to the above-described clock signals CLK1 to CLK4, SC_CLK1 to SC_CLK4, and SS_CLK1 to SS_CLK4.

The data start control signal may include source start pulse and clock signals. The source start pulse controls the start time of data sampling, and clock signals can be used to control the sampling operation.

The scan driver 210 may output scan signals corresponding to the scan drive control signal. The scan driver 210 may sequentially supply scan signals to the first scan lines SC1 to SCn. Here, the scan signal may be set to a gate-on voltage (eg, a high level voltage) so that the transistor included in the pixels PX can be turned on.

The scan driver 210 may output sensing signals in response to the scan drive control signal. The scan driver 210 may supply a sensing signal to at least one of the second scan lines SS1 to SS2. Here, the sensing signal may be set to a gate-on voltage (eg, a high level voltage) so that the transistor included in the pixels PX can be turned on.

The data driver 220 may supply data signals to the data lines D1 to Dm in response to the data driving control signal. The data signal supplied to the data lines D1 to Dm may be supplied to the pixels PX to which the scan signal is supplied. To this end, the data driver 220 may supply data signals to the data lines D1 to Dm to be synchronized with the scan signal.

The sensing unit 230 may supply initialization power to the pixels PX to which sensing signals are supplied to the sensing lines SL1 to SLm, and measure deterioration information of the pixels PX. In FIG. 1, although the sensing unit 230 is illustrated as having a separate configuration, the sensing unit 230 may be included in the data driving unit 220.

The display unit 100 includes a plurality of pixels PX connected to the data lines D1 to Dm, the first scan lines SC1 to SCn, the second scan lines SS1 to SSn, and the sensing lines SL1 to SLm. It can contain.

The pixels PX may receive first power ELVDD and second power ELVSS from the outside.

Each of the pixels PX may receive a data signal from the data lines D1 to Dm when the scan signal is supplied to the first scan lines SC1 to SCn connected to itself. The pixel PX supplied with the data signal may control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the light emitting device (not shown) in response to the data signal.

At this time, the light emitting device may generate light having a predetermined luminance corresponding to the amount of current. Additionally, the first power supply ELVDD may be set to a higher voltage than the second power supply ELVSS.

Meanwhile, in FIG. 1, although the pixel PX is illustrated as being connected to one first scanning line SCi and one data line Dj, the present invention is not limited thereto. In other words, the number of first scan lines SC1 to SCn connected to the pixel PX may correspond to the circuit structure of the pixel PX.

In addition, in some cases, the pixel PX may be connected to the emission control line in addition to the first scan lines SC1 to SCn and the data lines D1 to Dm. In this case, the emission driver for outputting the emission control signal is further provided. It may be provided.

2 is a view showing a scan driver according to embodiments of the present invention.

Referring to FIG. 2, the scan driver 210 may include a plurality of stages ST1, ST2, ST3, ST4, ??.

Each of the stages ST1, ST2, ST3, ST4, ... is scanned signals SC(1), SC(2) with first scan lines SC1 to SCn in response to the scan start signal STV, SC(3), SC(4), ...), and sensing signals SS(1), SS(2), SS(3), SS(4) with second scan lines SS1 to SSn ), ...). For example, the n-th stage may output the n-th scan signal through the n-th scan line SCn. The scan start signal STV for controlling the timing of the first scan signal may be supplied to the first stage ST1.

Each of the stages ST1, ST2, ST3, ST4, ... is a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, a first 1 clock terminal (CK1), second clock terminal (CK2), sensing mode activation clock terminal (S_CK), sensing clock terminal (SSCK), scan clock terminal (SCCK), first power terminal (V1), second power terminal (V2), a third power terminal V3, a carry output terminal CR, a first output terminal OUT1, and a second output terminal OUT2.

The first input terminal IN1 may receive a scan start signal STV or a previous carry signal. In one embodiment, the scan start signal STV is supplied to the first input terminal IN1 of the first stage ST1, and to the stages other than the first stage ST1, the first input terminal IN1 is provided. The carry signal of the previous stage can be applied. In one embodiment, the n-2 carry signal may be applied to the first input terminal IN1 of the n-th stage (where n is a natural number of 3 or more).

The second input terminal IN2 may receive a sensing on signal SEN_ON signal. The sensing on signal SEN_ON is a control signal for outputting a scan signal during a sensing period in which the mobility, threshold voltage, and current characteristics of the organic light emitting diode (OLED) included in the pixel can be sensed. For example, the gate-on voltage may be stored in the sampling node included in the stage by the sensing-on signal SEN_ON. In one embodiment, the sensing period may be included within the vertical blank period.

The third input terminal IN3 may receive the display on signal DIS_ON. The display-on signal DIS_ON may have a gate-on voltage in the display period and a gate-off voltage in the sensing period.

The fourth input terminal IN4 may then receive a carry signal. Thereafter, the carry signal may be one of carry signals supplied a predetermined time after the output of the carry signal of the current stage. In one embodiment, an n+2 carry signal may be applied to the fourth input terminal IN4 of the n-th stage. In an embodiment, an n+3 carry signal may be applied to the fourth input terminal IN4 of the n-th stage.

Clock signals having a half-period difference, for example, first and third clock signals CLK1 and CLK3 may be applied to the first clock terminal CK1 and the second clock terminal CK2 of the n-th stage. Second and fourth clock signals CLK2 and CLK4 may be applied to the first clock terminal CK1 and the second clock terminal CK2 of the n+1 stage.

In one embodiment, the gate-on voltage period of the clock signals CLK1 to CLK4 may be 2 horizontal periods 2H. Also, the gate-on voltage period of the first clock signal CLK1 and the gate-on voltage period of the second clock signal CLK2 may overlap for one horizontal period 1H.

However, this is an example, and the waveform relationships of the clock signals CLK1 to CLK4 are not limited thereto. In addition, the number of clock signals supplied to one stage is not limited thereto.

The first to fourth clock signals CLK1 to CLK4 may be set as a square wave signal repeating a logic high level and a logic low level. Here, the logic high level may correspond to the gate-on voltage, and the logic low level may correspond to the gate-off voltage. For example, the logic high level can be a voltage value between about 10V and about 30V, and the logic low level can be a voltage value between about -16V and about -3V.

The sensing mode activation clock terminal S_CK may receive the sensing mode activation clock signal S_CLK. The sensing mode activation clock signal S_CLK has a gate-on voltage during a sensing period and may charge a gate-on voltage to the first driving node.

The sensing clock terminal SSCK may receive any one of the sensing clock signals SS_CLK1 to SS_CLK4. For example, the sensing clock terminal SSCK may receive a sensing clock signal having the same waveform as the clock signal input to the second clock terminal CK2.

The sensing clock signal SS_CLK may have a gate-on voltage during a mobility, threshold voltage, and current characteristic sensing period of the organic light emitting diode OLED included in the pixel. The sensing clock signals SS_CLK1 to SS_CLK4 may have a gate-on voltage synchronized with the output of the sensing signal SS(k). In one embodiment, the sensing clock signals SS_CLK1 to SS_CLK4 may be configured to have a difference of half a period or more. In various embodiments of the present invention, the sensing clock signals SS_CLK1 to SS_CLK4 may be set to have the same waveform synchronized with the clock signals CLK1 to CLK4, respectively.

In one embodiment, the first sensing clock signal SS_CLK1 having the same waveform synchronized with the first clock signal CLK1 is applied to the sensing clock terminal SSCK of the n-th stage, and the sensing clock of the n+1 stage is applied. The second sensing clock signal SS_CLK2 having the same waveform synchronized with the second clock signal CLK2 may be applied to the terminal SSCK. Also, a third sensing clock signal SS_CLK3 having the same waveform synchronized with the third clock signal CLK3 is applied to the sensing clock terminal SSCK of the n+2 stage, and a sensing clock terminal of the n+3 stage. The fourth sensing clock signal SS_CLK4 having the same waveform synchronized with the fourth clock signal CLK4 may be applied to the SSCK.

In one embodiment, the gate-on voltage period of the first to fourth sensing clock signals SS_CLK1 to SS_CLK4 may be 2 horizontal periods 2H. Further, the gate-on voltage period of the first sensing clock signal SS_CLK1 and the gate-on voltage period of the second sensing clock signal SS_CLK2 may overlap for one horizontal period 1H. However, this is an example, and the waveform relationship of the sensing clock signals SS_CLK1 to SS_CLK4 is not limited thereto.

The scan clock terminal SCCK may receive any one of the scan clock signals SC_CLK1 to SC_CLK4. For example, the scan clock terminal SCCK may receive a scan clock signal having the same waveform as the clock signal input to the second clock terminal CK2.

The scan clock signal SC_CLK may have a gate-on voltage during the mobility and threshold voltage sensing period of the driving transistor.

The scan clock signals SC_CLK1 to SC_CLK4 may have a gate-on voltage synchronized with the output of the scan signal SC(k). In one embodiment, the scan clock signals SC_CLK1 to SC_CLK4 may be configured to have a difference of half a period or more. In various embodiments of the present invention, the scan clock signals SC_CLK1 to SC_CLK4 may be set to have the same waveform synchronized with the clock signals CLK1 to CLK4, respectively.

In one embodiment, the first scan clock signal SC_CLK1 having the same waveform synchronized with the first clock signal CLK1 is applied to the scan clock terminal SCCK of the n-th stage, and the scan clock of the n+1 stage The second scan clock signal SC_CLK2 having the same waveform synchronized with the second clock signal CLK2 may be applied to the terminal SCCK. Further, a third scan clock signal SC_CLK3 having the same waveform synchronized with the third clock signal CLK3 is applied to the scan clock terminal SCCK of the n+2 stage, and a scan clock terminal of the n+3 stage The fourth scan clock signal SC_CLK4 having the same waveform synchronized with the fourth clock signal CLK4 may be applied to the SCCK.

In one embodiment, the gate-on voltage period of the first to fourth scan clock signals SC_CLK1 to SC_CLK4 may be 2 horizontal periods (2H). Also, the gate-on voltage period of the first scan clock signal SC_CLK1 and the gate-on voltage period of the second scan clock signal SC_CLK2 may overlap for one horizontal period 1H. However, this is an example, and the waveform relationship of the scan clock signals SC_CLK1 to SC_CLK4 is not limited thereto.

The first power terminal V1 receives the voltage of the first power source VGH, the second power terminal V2 receives the voltage of the second power source VGL1, and the third power source terminal V3 is the third power terminal V1. The voltage of the power supply VGL2 can be received. The first power source VGH may be set to a gate-on voltage. The second and third power sources VGL1 and VGL2 may be set to a gate-off voltage.

In one embodiment, the second and third power sources VGL1 and VGL2 may be the same. Also, in one embodiment, the voltage level of the second power source VGL1 may be smaller than the voltage level of the third power source VGL2. For example, the second power supply VGL1 may be set to about -9V, and the third power supply VGL2 may be set to about -6V.

The carry output terminal CR may output a carry signal. The first output terminal OUT1 may output the scan signal SC(k). The second output terminal OUT2 may output a sensing signal SS(k).

3 is a circuit diagram illustrating a first embodiment of a stage included in the scan driver of FIG. 2.

1 to 3, the k-th stage (STk, where k is a natural number) includes a first driving control unit 110, a second driving control unit 120, an output buffer unit 130A, 1330B, 130C, and a connection control unit It may include (140).

In an embodiment, the transistors included in the k-th stage STk may be oxide semiconductor transistors. That is, the semiconductor layer (active pattern) of the transistors may be formed of an oxide semiconductor.

The first driving control unit 110 may control the voltage of the first node N1 and the voltage of the second node N2 in response to the previous carry signal CR(k-2). In one embodiment, the previous carry signal CR(k-2) may be the k-2 carry signal CR(k-2). However, this is an example, and the previous carry signal is not limited to the k-2 carry signal CR(k-2). For example, the previous carry signal may be a k-1 carry signal.

The output of the k-th carry signal CR(k) may be controlled based on the voltage of the first node N1 and the voltage of the second node N2. For example, the voltage of the first node N1 is a voltage for controlling the output of the k-th carry signal CR(k).

Meanwhile, in an embodiment, the voltage of the first driving node QN1 is determined by the voltage of the first node N1 during the display period, and the second driving node QN2 is determined by the voltage of the second node N2. The voltage of can be determined. Therefore, in the display period, the output of the k-th scan signal SC(k) may be controlled by the voltage of the first node N1 and the voltage of the second node N2.

In other words, the first driving control unit 110 may perform an operation for output control of the carry signal CR(k) and the scan signal SC(k) based on the plurality of input signals in the display period. have.

In one embodiment, the first driving control unit 110 controls the voltages of the first to fourth transistors T1 to T4 and the second node N2 to control the voltage of the first node N1. It may include to the seventh transistor (T5 to T7).

The first transistor T1 may be connected between the first power terminal V1 to which the first power VGH is applied and the first node N1. The first transistor T1 may include a gate electrode receiving the k-2 carry signal CR(k-2) or the scan start signal STV. The first transistor T1 may precharge the voltage of the first node N1 to the voltage of the first power supply VGH in response to the k-2 carry signal CR(k-2). .

The second transistor T2 and the third transistor T3 may be connected between the first node N1 and the carry output terminal CR. The second transistor T2 may include a gate electrode receiving the third clock signal CLK3. The third transistor T3 may include a gate electrode connected to the second node N2. The second and third transistors T2 and T3 may hold the voltage of the first node N1.

The fourth transistor T4 may be connected between the first node N1 and the carry output terminal CR. The fourth transistor T4 may include a fourth transistor that receives the k+2 carry signal CR(k+2). The fourth transistor T4 may discharge the voltage charged in the first node N1. For example, the voltage of the first node N1 may be discharged in synchronization with the turn-on of the fourth transistor T4, that is, the rising time of the k+2 carry signal CR(k+2). .

The fifth transistor T5 may be connected between the first clock terminal CK1 to which the first clock signal CLK1 is applied and the second node N2. The fifth transistor T5 may include a gate electrode connected to the first node N1. The sixth transistor T6 may be connected between the second node N2 and the first power terminal V1. The sixth transistor T6 may further include a gate electrode receiving the first clock signal CLK1. The seventh transistor T7 may be diode-connected between the first power terminal V1 and the second node N2.

The fifth to seventh transistors T5 to T7 may control the voltage of the second node N2 based on the first clock signal CLK1.

The second driving control unit 120 includes a sensing on signal SEN_ON, a carry signal CR(k+2), a voltage of the first power source VGH, a voltage of the first node N1, and a sampling node SN ) Controls the voltage of the first driving node QN1 connected to the first node N1 based on the voltage of ), and drives the second based on the voltage of the sampling node SN and the sensing mode activation clock signal S_CLK. The voltage of the node QN2 can be controlled.

The second driving control unit 120 may control the voltage of the first driving node QN1 and the voltage of the second driving node QN2 during the sensing period. In the sensing period, the output of the scan signal CS(k) may be controlled by the voltage of the first driving node QN1 and the voltage of the second driving node QN2. In one embodiment, the sensing period may be a sensing period for sensing the mobility, threshold voltage, and current characteristics of the organic light emitting diode (OLED) included in the pixel.

In one embodiment, the second driving control unit 120 controls the voltages of the eighth and eleventh transistors T8 to T11 and the second driving node QN2 controlling the voltage of the first driving node QN1. The twelfth and thirteenth transistors T12 and T13 may be included. The second driving control unit 120 may further include a third capacitor C3.

The eighth transistor T8 may then be connected between the fourth input terminal IN4 to which the carry signal is applied and the sampling node SN. The eighth transistor T8 may include a gate electrode receiving the sensing on signal SEN_ON. In one embodiment, the carry signal may be a k+2 carry signal CR(k+2). In one embodiment, the sensing on signal SEN_ON may have a gate-on voltage at least once during the display period. In various embodiments of the present invention, the sensing on signal SEN_ON may have the gate-on voltage 4 during the display period.

The eighth transistor T8 may charge the sampling node SN of the gate-on voltage of the k+2 carry signal CR(k+2) in response to the sensing on signal SEN_ON. The sensing on signal SEN_ON may have a gate-on voltage in synchronization with the k+2 carry signal CR(k+2).

The third capacitor C3 may be connected between the second power terminal V2 receiving the second power source VGL1 and the sampling node SN. The gate-on voltage charged in the sampling node SN may be maintained by the third capacitor C3 in response to the sensing-on signal SEN_ON during the display period.

The ninth transistor T9 and the tenth transistor T10 may be connected in series between the sensing mode activation clock terminal S_CK to which the sensing mode activation clock signal S_CLK is applied and the first driving node QN1. A node between the ninth transistor T9 and the tenth transistor T10 may be defined as a third node N3.

The ninth and tenth transistors T9 and T10 may include gate electrodes commonly connected to the sampling node SN. The ninth and tenth transistors T9 and T10 may transmit the sensing mode activation clock signal S_CLK to the first driving node QN1 based on the voltage of the sampling node SN. In one embodiment, the sensing mode activation clock signal S_CLK may have a gate-on voltage during the sensing period.

The eleventh transistor T11 may be connected between the third node N3 and the carry output terminal CR to which the k-th carry signal CR(k) is output. The eleventh transistor T11 may include a gate electrode connected to the first driving node QN1.

The ninth to eleventh transistors T9 to T11 hold the voltage of the third node N3 as the voltage of the carry signal CR(k) in response to the voltage of the first driving node QN1. The unnecessary drain-source voltage rise of the transistor T9 can be prevented. Therefore, the output of the stable scan signal SC(k) is guaranteed, and the reliability of the display device can be improved.

The twelfth transistor T12 and the thirteenth transistor T13 may be connected in series between the third power terminal V3 to which the third power source VGL2 is applied and the second driving node QN2. The twelfth transistor T12 may include a gate electrode receiving the sensing mode activation clock signal S_CLK, and the thirteenth transistor T13 may include a gate electrode connected to the sampling node SN. In the sensing period, the twelfth and thirteenth transistors T12 and T13 are turned on, and the voltage of the third power source VGL2 may be applied to the second driving node QN2.

The output buffer units 130A, 130B, and 130C output a carry signal CR(k) in response to the voltage of the first node N1 and the voltage of the second node N2, and the first driving node QN1 The scan signal SC(k) and the sensing signal SS(k) applied to the same pixel may be output in response to the voltage of and the voltage of the second driving node QN2.

The output buffer units 130A, 130B, and 130C may include 14th to 17th transistors T14 to T17. The output buffer units 130A, 130B, and 130C may further include 21st and 22nd transistors T21 and T22 for sensing signal output. Also, the output buffer units 130A, 130B, and 130C may further include first and second capacitors C1 and C2.

The fourteenth transistor T14 may be connected between the second clock terminal CK2 to which the third clock signal CLK3 is applied and the carry output terminal CR. The fourteenth transistor T14 may include a gate electrode connected to the first node N1. The fourteenth transistor T14 may supply a gate-on voltage to the carry output terminal CR in response to the voltage of the first node N1. For example, the fourteenth transistor T14 may function as a pull-up buffer.

The fifteenth transistor T15 may be connected between the carry output terminal CR and the second power terminal V2 to which the second power source VGL1 is applied. The fifteenth transistor T15 may include a gate electrode connected to the second node N2. The fifteenth transistor T15 may supply a gate-off voltage to the carry output terminal CR in response to the voltage of the second node N2. For example, the fifteenth transistor T15 may maintain the voltage of the carry output terminal CR at the gate-off voltage level (ie, the logic low level).

The first capacitor C1 may be connected between the first node N1 and the carry output terminal CR. The first capacitor C1 may function as a boosting capacitor. Accordingly, the 14th transistor T14 can stably maintain the turn-on state for a predetermined period. The second capacitor C2 may be connected between the second node N2 and the carry output terminal CR.

The sixteenth transistor T16 may be connected between the scan clock terminal SCCK to which the third scan clock signal SC_CLK3 is applied and the first output terminal OUT1. The sixteenth transistor T16 may include a gate electrode connected to the first driving node QN1. The sixteenth transistor T16 may supply a gate-on voltage to the first output terminal OUT1 in response to the voltage of the first driving node QN1.

The 17th transistor T17 may be connected between the first output terminal OUT1 and the third power terminal V3 to which the third power source VGL2 is applied. The seventeenth transistor T17 may include a gate electrode connected to the second driving node QN2. The 17th transistor T17 may supply a gate-off voltage to the output terminal OUT in response to the voltage of the second driving node QN2.

The 21st transistor T21 may be connected between the sensing clock terminal SSCK to which the third sensing clock signal SS_CLK3 is applied and the second output terminal OUT2. The twenty-first transistor T21 may include a gate electrode connected to the first driving node QN1. The twenty-first transistor T21 may supply a gate-on voltage to the second output terminal OUT2 in response to the voltage of the first driving node QN1. For example, the twenty-first transistor T21 may function as a pull-up buffer.

The 22nd transistor T22 may be connected between the first power terminal V1 and the second output terminal OUT2. The 22nd transistor T22 may include a gate electrode connected to the second driving node QN2. The second transistor T22 may supply a gate-off voltage to the second output terminal OUT2 in response to the voltage of the second driving node QN2.

In one embodiment, since the k-th carry signal CR(k) is used as an input signal of another stage, the voltage of the second power supply VGL1 is lower than the voltage of the third power supply VGL2 for stable scan signal output. Can be.

The connection control unit 140 electrically connects the first node N1 and the first driving node QN1 and the second node N2 and the second driving node QN2 in response to the display-on signal DIS_ON. Can be. The display-on signal DIS_ON may have a gate-on voltage in the display period and a gate-off voltage in the sensing period.

In an embodiment, the output buffer units 130A, 130B, and 130C are carried by the connection control unit 140 according to the operation of the first driving control unit 110 during the display period, and the carry signal CR(k) and the scan signal ( SC(k)) and a sensing signal SS(k) may be output. That is, during the display period, the second driving control unit 120 does not affect the output of the output buffer units 130A, 130B, and 130C. Similarly, by the connection control unit 140, during the sensing period, the output buffer units 130A, 130B, and 130C according to the operation of the second driving control unit 120 carry signals CR(k) and scan signals SC(k). ) And the sensing signal SS(k), that is, during the sensing period, the first driving control unit 110 does not affect the output of the output buffer units 130A, 130B, and 130C.

In one embodiment, the connection control unit 140 may include 18th and 19th transistors T18 and T19.

The eighteenth transistor T18 may be connected between the first node N1 and the first driving node QN1. The eighteenth transistor T18 may include a gate electrode receiving the display on signal DIS_ON.

The 19th transistor T19 may be connected between the second node N2 and the second driving node QN2. The 19th transistor T19 may include a gate electrode receiving the display on signal DIS_ON.

As described above, the scan driver 210 according to embodiments of the present invention includes a clock signal (in the above, a third clock signal CLK3) for output of a carry signal CR(k), and a scan signal SC( k)) of the scan clock signal (SC_CLK) (in the above, the third scan clock signal (SC_CLK3)) and the sensing clock signal (SS (k)) for the output of the sensing clock signal (SS_CLK) (in the above, the 3 Each sensing clock signal (SS_CLK3) is supplied. Accordingly, the scan driver 210 according to embodiments of the present invention independently controls the outputs of the scan signal SC(k) and the sensing signal SS(k), and of the driving transistor included in the pixel during the sensing period. The current characteristics of the organic light emitting diode (OLED) as well as mobility and threshold voltage may be sensed. In addition, the plurality of scan clock signals SC_CLK and the plurality of sensing clock signals SS_CLK of the scan driver 210 according to embodiments of the present invention are used to output a plurality of scan signals and sensing signals in one sensing period. In this way, multiple pixel rows can be sensed in one sensing period.

4 is a timing diagram showing an example of driving of the stage of FIG. 3. In FIG. 4, the operation of the k-th to k+3 stages STk to STk+3 will be mainly described. In addition, the position, width, height, and the like of the waveform shown in FIG. 4 are exemplary only, and are not limited thereto.

1 to 4, the scan driver 210 including the k-th to k+3 stages STk to STk+3 may sequentially output a scan signal.

In one embodiment, one frame period may include a display period DP and a vertical blank period VBP. In the display period DP, scan signals may be sequentially provided to pixel lines. In the display period DP, the sensing-on signal SEN_ON may be supplied to at least one selected stage among the plurality of stages. Only the stage receiving the sensing on signal SEN_ON may output the scanning signal and the sensing signal in the subsequent sensing period SP. During the sensing period SP, sensing may be performed on pixels receiving the scanning signal and the sensing signal output from the selected at least one stage.

In one embodiment, at least one stage may be selected as stages receiving different sensing clock signals SS_CLK and different scan clock signals SC_CLK. For example, the at least one stage includes a first stage receiving a first sensing clock signal SS_CLK1 and a first scan clock signal SC_CLK1, a second sensing clock signal SS_CLK2 and a second scan clock signal SC_CLK2. ), the third stage receiving the third sensing clock signal SS_CLK3 and the third stage receiving the third scanning clock signal SC_CLK3, the fourth sensing clock signal SS_CLK4 and the fourth scanning clock signal SC_CLK4. It may be a fourth stage to receive.

In the present specification, since the scan driver 210 is configured to receive four clock signals CLK, four scan clock signals SC_CLK, and four sensing clock signals SS_CLK, the sensing on signal during the display period DP SEN_ON) is described in an example in which four stages are supplied. However, the technical idea of the present invention is not limited to this, and the scan driver 210 is configured to receive more or fewer clock signals CLK, scan clock signals SC_CLK, and sensing clock signals SS_CLK. , The sensing on signal SEN_ON may be supplied to a number of stages corresponding to the number of the clock signal CLK, the scan clock signal SC_CLK, and the sensing clock signal SS_CLK.

The vertical blank period VBP may include a sensing period SP and a reset period RP. However, this is an example, and the reset period RP may be included in the display period DP. In one embodiment, the sensing period SP is a current characteristic of the first sensing period SP1 in which mobility and a threshold voltage are sensed, and an organic light emitting diode OLED for each of at least one stage selected during the display period DP. The second sensing period SP2 that is sensed may be included. Also, the sensing period SP may include a pixel reset period PRP.

In the display period DP, the display-on signal DIS_ON may have a gate-on voltage and the sensing mode activation clock signal S_CLK may have a gate-off signal. In the sensing period SP, the display-on signal DIS_ON may have a gate-off voltage and the sensing mode activation clock signal S_CLK may have a gate-off signal.

2 to 4, when the k-2 carry signal CR(k-2) is applied in synchronization with the first clock signal CLK1 applied to the first clock terminal CK1, the The voltage of one node N1 may be precharged. However, this is an example, and the k-1 carry signal CR(k-1) may be applied in place of the k-2 carry signal CR(k-2). That is, before the output of the k-th scan signal SC(k), the voltages of the first node N1 and the first driving node QN1 may be precharged.

Thereafter, when the third clock signal CLK3 and the third scan clock signal SC_CLK3 have a gate-on voltage, the voltages of the first node N1 and the first driving node QN1 are caused by the first capacitor C1. It can be boosted. In addition, the k-th carry signal CR(k) is output in synchronization with the third clock signal CLK3, and the k-th carry signal CR(k) and kth synchronization in synchronization with the third scan clock signal SC_CLK3. The scanning signal SC(k) may be output.

Thereafter, the k+2 carry signal CR(k+2) and the sensing on signal SEN_ON may be simultaneously applied. The at least one stage that has received the sensing-on signal SEN_ON may then output the scanning signal SC(k) in the vertical blank period VBP. The voltages of the first node N1 and the first driving node QN1 are discharged in response to the k+2 carry signal CR(k+2), and the sampling node SN in response to the sensing on signal SEN_ON. ), the gate-on voltage may be charged and maintained.

When the sensing mode activation clock signal S_CLK has a gate-on voltage and the display on signal DIS_ON has a gate-off voltage, the voltage of the first driving node QN1 is charged by the sensing mode activation clock signal S_CLK. Can be.

Thereafter, the k-th stage STk may output the scan signal SC(k) in synchronization with the third scan clock signal SC_CLK3 applied to the scan clock terminal SCCK. In one embodiment, during the vertical blank period VBP, the scan signal SC(k) may be output at least twice. The first scan signal SC(k) is output in the first sensing period SP1, and when the first scan signal SC(k) is output, the mobility and threshold voltage of the driving transistor provided in the pixel are sensed. The voltage for the pixel can be applied to the pixel. The second scan signal SC(k) is output in the pixel reset period PRP, and when the second scan signal SC(k) is output, the data voltage applied to the pixel in the previous display period DP is Can be re-applied.

Also, the k-th stage STk may output the sensing signal SS(k) in synchronization with the third sensing clock signal SS_CLK3 applied to the sensing clock terminal SSCK. In one embodiment, the sensing signal SS(k) may be output in the first sensing period SP1, the second sensing period SP2, and the pixel reset period PRP. While the sensing signal SS(k) is output in the first sensing period SP1, a sensing current for sensing the mobility and threshold voltage of the driving transistor provided in the pixel may be applied to the pixel. While the sensing signal SS(k) is output in the second sensing period SP2, a sensing current for sensing the current characteristic of the organic light emitting diode OLED provided in the pixel may be applied to the pixel.

The mobility of the driving transistor based on the voltage supplied to the pixel by the first scan signal SC(k) and the sensing current supplied to the pixel by the sensing signal SS(k) in the first sensing period SP1 And a threshold voltage can be sensed. In addition, the current characteristic of the organic light emitting diode OLED may be sensed based on the sensing current supplied to the pixel by the sensing signal SS(k) in the second sensing period SP2.

At least one stage that has received the sensing-on signal SEN_ON during the display period DP sequentially performs operations in the above-described sensing period SP. That is, during the vertical blank period VBP, the first to fourth scan clock signals SC_CLK1 to SC_CLK4 and the first to fourth sensing clock signals SS_CLK1 to SS_CLK4 are sequentially output as illustrated in FIG. 4, Scan signals and sensing signals are sequentially supplied to the k-th stage STk, the k+1 stage STk+1, the k+2 stage STk+2, and the k+3 stage STk+3. , Sensing for a pixel may be performed.

Thereafter, in the reset period RP, the sensing on voltage SEN_ON may have a gate on voltage. At this time, since the k+2 carry signal CR(k+2) has a gate-off voltage, the voltage of the sampling node SN may be reset.

5 is a circuit diagram illustrating an example of a pixel included in the display device of FIG. 1. In FIG. 5, for convenience of description, a pixel PX connected to the i-th first scan line SCi and the j-th data line Dj is illustrated.

The pixel PX may include a driving transistor M1, a switching transistor M2, a sensing transistor M3, a storage capacitor Cst, and a light emitting device OLED.

The switching transistor M2 may include a first electrode connected to the j-th data line Dj, a gate electrode connected to the i-th first scan line SCi, and a second electrode connected to the first node Na. .

The switching transistor M2 is turned on when the scan signal is supplied from the i-th first scan line SCi to supply the data signal received from the j-th data line Dj to the storage capacitor Cst. Alternatively, the potential of the first node Na can be controlled.

In this case, the storage capacitor Cst including the first electrode connected to the first node Na and the second electrode connected to the second node Nb may charge a voltage corresponding to the data signal.

The driving transistor M1 may include a first electrode connected to the first power supply ELVDD, a second electrode connected to the light emitting device OLED, and a gate electrode connected to the first node Na.

The driving transistor M1 may control the amount of current flowing through the light emitting device OLED in response to the voltage value between the gate and the source.

The sensing transistor M3 may include a first electrode connected to the j-th sensing line SLj, a second electrode connected to the second node Nb, and a gate electrode connected to the i-th second scan line SSi. When the sensing signal is supplied to the i-th second scan line SSi, the sensing transistor M3 is turned on to control the potential of the second node Nb. Alternatively, when the sensing signal is supplied to the i-th second scan line SSi, the sensing transistor M3 is turned on to measure the current flowing through the light emitting device OLED.

The light emitting device OLED may include a first electrode (anode electrode) connected to the second electrode of the driving transistor M1 and a second electrode (cathode electrode) connected to the second power supply ELVSS. The light emitting device OLED may generate light corresponding to the amount of current supplied from the driving transistor M1.

In FIG. 5, the first electrodes of the transistors M1 to M3 may be set to one of the source electrode and the drain electrode, and the second electrodes of the transistors M1 to M3 may be set to electrodes different from the first electrode. . For example, when the first electrode is set as the source electrode, the second electrode may be set as the drain electrode.

Also, the transistors M1 to M3 may be NMOS transistors as illustrated in FIG. 5.

While sensing the mobility of the driving transistor M1, the scan signal activated by the first scan line SCi is supplied and the sensing signal activated by the second scan line SSi is supplied. However, it is necessary to turn off the driving transistor M1 and turn on the sensing transistor M3 to sense deterioration information by sensing the current flowing through the light emitting device OLED. That is, while sensing the current flowing through the light emitting device OLED, an inactive signal must be applied to the first scan line SCi and an activated signal must be applied to the second scan line SSi. Therefore, it is necessary to separately supply the scanning signal supplied to the first scanning line SCi and the sensing signal supplied to the second scanning line SSi.

6 is a circuit diagram illustrating a second embodiment of a stage included in the scan driver of FIG. 2.

Referring to FIG. 6, the k-th stage STk according to the second embodiment of the present invention is compared to the first embodiment of FIG. 3, with a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor (C6) may be further included.

Specifically, the second driving control unit 120 according to the second embodiment of the present invention may further include a fourth capacitor C4. The fourth capacitor C4 may be connected between the gate electrode of the eighth transistor T8 and the sampling node SN.

In addition, the second output buffer unit 130B according to the second embodiment of the present invention may further include a fifth capacitor C5. The fifth capacitor C5 may be connected between the first driving node QN1 and the first output terminal OUT1.

Meanwhile, the third output buffer unit 130C according to the second embodiment of the present invention may further include a sixth capacitor C6. The sixth capacitor C6 may be connected between the first driving node QN1 and the second output terminal OUT2.

In the second embodiment of the present invention, as the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are provided, the stage STk may be more robust to the threshold voltage negative condition.

Those of ordinary skill in the art to which the present invention pertains will appreciate that the present invention may be implemented in other specific forms without changing its technical spirit or essential features. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims, which will be described later, rather than the detailed description, and all the modified or modified forms derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted.

PX: Pixel 100: Display
210: scan driver 220: data driver
230: sensing unit 240: timing control unit

Claims (20)

It includes a plurality of stages for outputting each of the scanning signal,
The nth (where n is a natural number) stage,
A first driving control unit controlling the voltage of the first node and the voltage of the second node in response to the previous carry signal;
The voltage of the first driving node is controlled based on the sensing on signal, the carry signal afterwards, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node, and is based on the voltage of the sampling node and the sensing clock signal. A second driving control unit controlling the voltage of the second driving node;
A first output buffer unit for outputting a k (where k is a natural number) clock signal as a carry signal in response to the voltage of the first node and the voltage of the second node, the voltage of the first driving node and the second The second output buffer unit outputs a k-th scan clock signal as the scan signal in response to the voltage of the driving node, and a k-th sensing clock signal in response to the voltage of the first driving node and the voltage of the second driving node. An output buffer unit including a third output buffer unit outputting a sensing signal; And
And a connection control unit electrically connecting the first node, the first driving node, and the second node and the second driving node, respectively, in response to the display-on signal. According to claim 1, The k-th scan clock signal and the k-th sensing clock signal,
And a scan waveform having the same waveform synchronized with the k-th clock signal. The method of claim 2, wherein one frame period includes a display period and a vertical blank period,
In the display period, the sensing-on signal is supplied to at least k stages of the stages. The method of claim 3, wherein the at least k stages,
And a scan driver outputting the scan signal in response to the kth scan clock signal and outputting the sensing signal in response to the kth scan clock signal in the vertical blank period following the display period. The method of claim 4, wherein the at least k stages,
And a scanning driver outputting the scanning signal at least twice during the vertical blank period. The method of claim 5, wherein the at least k stages,
And scanning outputting the sensing signal at least once during the vertical blank period. 7. The scan driver according to claim 6, wherein the output of the scan signal overlaps the output of the sensing signal. The method of claim 1, wherein the first driving control unit,
A first transistor connected between a first power terminal to which the first power is applied and the first node, and a gate electrode receiving the previous carry signal or a scan start signal;
Second and third transistors connected in series between the first node and the carry output terminal;
A fourth transistor connected between the first node and the carry output terminal, the gate electrode receiving the carry signal after the gate electrode;
A fifth transistor connected between a first clock terminal to which a clock signal different from the k-th clock signal is applied, and the second node, and a gate electrode connected to the first node;
A sixth transistor connected between the first power terminal to which the first power is applied and the second node, and a gate electrode connected to the first clock terminal; And
And a seventh transistor diode-connected between the first power terminal and the second node. The method of claim 1, wherein the second driving control unit,
An eighth transistor connected between a first input terminal to which the carry signal is applied and the sampling node, and a gate electrode receiving the sensing on signal;
Ninth and tenth transistors connected in series between the sensing clock terminal to which the sensing clock signal is applied and the first driving node, wherein gate electrodes are commonly connected to the sampling node; And
And a third node between the ninth and ten transistors and an output terminal of the carry signal, wherein the gate electrode includes eleven transistors connected to the first driving node. 10. The scan driver of claim 9, wherein when the sensing clock signal is supplied, the eleventh transistor supplies the voltage of the first power supply to the third node in response to the voltage of the first driving node. . The method of claim 2, wherein the second driving control unit,
A capacitor connected between a second power terminal to which a second power is applied and the sampling node; And
Further comprising twelfth and thirteenth transistors connected in series between the third power terminal to which the third power is applied and the second driving node,
The twelfth transistor includes a gate electrode receiving the sensing clock signal,
The thirteenth transistor includes a gate electrode connected to the sampling node. The method of claim 1, wherein the first output buffer unit,
A 14th transistor connected between a second clock terminal to which the kth clock signal is applied and a carry output terminal, and a gate electrode connected to the first node; And
And a fifteenth transistor connected between the carry output terminal and a second power terminal to which a second power is applied, and a gate electrode connected to the second node. The method of claim 12, wherein the second output buffer unit,
A sixteenth transistor connected between a scan clock terminal to which the kth scan clock signal is applied and a first output terminal, and a gate electrode connected to the first driving node; And
And a 17th transistor connected between a third power terminal to which a third power source is applied and the first output terminal, and a gate electrode connected to the second driving node. The method of claim 13, wherein the third output buffer unit,
A twenty-first transistor connected between a sensing clock terminal to which the kth sensing clock signal is applied and a second output terminal, and a gate electrode connected to the first driving node; And
And a second transistor connected between the third power terminal to which the third power is applied and the second output terminal, and a gate electrode connected to the second driving node. According to claim 1, wherein the connection control unit,
An 18th transistor connected between the first node and the first driving node, the gate electrode receiving the display-on signal; And
And a 19th transistor connected between the second node and the second driving node and having a gate electrode receiving the display-on signal. A plurality of pixels respectively connected to the scan lines, lead-out lines, and data lines;
A scan driver including a plurality of stages to supply a scan signal and a sensing signal to the scan lines and the lead-out lines, respectively, is included,
The n (where n is a natural number) stage among the plurality of stages,
A first driving control unit controlling the voltage of the first node and the voltage of the second node in response to the previous carry signal;
The voltage of the first driving node connected to the first node is controlled based on the sensing on signal, the carry signal, the voltage of the first power source, the voltage of the first node, and the voltage of the sampling node. A second driving control unit controlling the voltage of the second driving node based on the voltage and the sensing clock signal;
A first output buffer unit for outputting a k (where k is a natural number) clock signal as a carry signal in response to the voltage of the first node and the voltage of the second node, the voltage of the first driving node and the second The second output buffer unit outputs a k-th scan clock signal as the scan signal in response to the voltage of the driving node, and a k-th sensing clock signal in response to the voltage of the first driving node and the voltage of the second driving node. An output buffer unit including a third output buffer unit outputting a sensing signal; And
And a connection control unit electrically connecting the first node, the first driving node, and the second node and the second driving node, respectively, in response to the display-on signal. The method of claim 16, wherein the k th º clock signal and the k th sensing clock signal are:
And the same waveform synchronized with the k-th clock signal. 18. The method of claim 17, wherein one frame period includes a display period and a vertical blank period,
In the display period, the sensing-on signal is supplied to at least k stages among the stages,
The at least k stages,
And outputting the scan signal in response to the kth scan clock signal and outputting the sensing signal in response to the kth scan clock signal in the vertical blank period following the display period. The display device according to claim 18, wherein a sensing voltage is supplied to pixel rows corresponding to the at least k stages during a period in which the scanning signal and the sensing signal overlap within the vertical blank period. 19. The display device of claim 18, wherein a sensing current is supplied to pixel rows corresponding to the at least k stages during a period in which the scanning signal and the sensing signal do not overlap within the vertical blank period.

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