CN111435810A

CN111435810A - Alternator and rectifier device

Info

Publication number: CN111435810A
Application number: CN201910034763.0A
Authority: CN
Inventors: 陈维忠; 锺尚书; 陈宴毅; 王惠琪
Original assignee: Actron Technology Corp
Current assignee: Actron Technology Corp
Priority date: 2019-01-15
Filing date: 2019-01-15
Publication date: 2020-07-21
Anticipated expiration: 2039-01-15
Also published as: CN111435810B

Abstract

The invention provides an AC generator and a rectifying device. The rectifying device comprises a transistor and a gate drive circuit. The control terminal of the transistor receives the gate voltage. The gate driving circuit generates a gate voltage according to a voltage difference between the rectified voltage and the input voltage. The gate driving circuit detects an initial time point when the voltage difference is smaller than a first preset threshold voltage, provides a gate voltage to turn on the transistor in a first time interval after the initial time point, and makes the voltage difference equal to a first reference voltage. The grid driving circuit adjusts the grid voltage to enable the voltage difference to be equal to the second reference voltage in a second time interval after the first time interval.

Description

Alternator and rectifier device

Technical Field

The present invention relates to an ac generator and a rectifier, and more particularly, to an ac generator and a rectifier that can reduce power loss.

Background

In an alternator, a rectifier device is often used to rectify an ac input voltage and generate a rectified voltage that can be considered a dc voltage. In the prior art, a diode or a transistor is often used to rectify an input voltage. Ideally, the rectified voltage should be maintained at a voltage value equal to the reference voltage (e.g., 0 volts) during the negative half cycle, but in practical cases, as shown in the waveform diagram of the known rectified voltage shown in fig. 1, the rectified voltage having a peak value of the voltage VP, and during the negative half cycle TN, the rectified voltage may have a voltage value lower than the reference voltage V0. That is, in the negative half period TN of the rectified voltage, a power loss (power loss) phenomenon occurs, which reduces the operating efficiency of the system.

Disclosure of Invention

The invention provides an AC generator and a rectifying device, which can reduce power loss.

The rectifying device of the invention comprises a transistor and a gate drive circuit. The transistor has a first terminal receiving an input voltage, a second terminal generating a rectified voltage, and a control terminal receiving a gate voltage. The gate driving circuit is coupled to the transistor and generates a gate voltage according to a voltage difference between the rectified voltage and the input voltage. The grid driving circuit detects an initial time point when the voltage difference is smaller than a first preset critical voltage, provides a grid voltage in a first time interval after the initial time point to turn on the transistor, and enables the voltage difference to be equal to a first reference voltage; the grid driving circuit adjusts the grid voltage to enable the voltage difference to be equal to the second reference voltage in a second time interval after the first time interval.

In an embodiment of the invention, the first reference voltage may be greater than, less than or equal to the second reference voltage.

In an embodiment of the invention, the first reference voltage is equal to a product of an on-resistance of the transistor and a current flowing through the transistor.

In an embodiment of the invention, the gate driving circuit detects a second time point when the voltage difference increases from the second reference voltage to the second predetermined threshold voltage in a third time interval after the second time interval, and adjusts the gate voltage to turn off the transistor after the second time point.

In an embodiment of the invention, the gate driving circuit includes an operational amplifier, a first switch and a second switch. The operational amplifier receives the voltage difference and the adjustment voltage, and generates a gate voltage at an output end according to the control signal. The first switch is connected in series between the first voltage and the output end and is switched on or off according to a second control signal. The second switch is connected in series between the second voltage and the output end and is switched on or off according to a third control signal.

In an embodiment of the invention, the gate driving circuit further includes a control signal generator. The control signal generator compares the voltage difference with the first preset threshold voltage or the second preset threshold voltage to generate a comparison result, and generates a first control signal, a second control signal and a third control signal according to the comparison result.

In an embodiment of the invention, the control signal generator includes a comparator, a selector, and a counter. The comparator receives the voltage difference and the selected voltage and generates a comparison result. The counter is coupled to the comparator, performs a counting operation according to the comparison result, and generates a first control signal, a second control signal and a third control signal.

In an embodiment of the invention, the counter performs a counting operation between a first time point and a second time point to generate a counting value, wherein the counting value is a first time interval when the counting value is smaller than the reference value, and is a second interval when the counting value is between the reference value and the maximum counting value.

In an embodiment of the invention, the gate driving circuit further includes a voltage generator. The voltage generator generates a second voltage, a second reference voltage, a first predetermined threshold voltage and a second predetermined threshold voltage according to the operating power.

In an embodiment of the invention, the voltage generator includes a voltage regulator and a reference voltage generator. The voltage regulator generates a first voltage according to the operation power supply and generates a first power supply and a second power supply of the operational amplifier and the counter. The reference voltage generator generates a first preset threshold voltage, a second preset threshold voltage and an adjustment voltage according to an operation power supply.

In an embodiment of the invention, the rectifying device further includes a diode and a capacitor. The anode of the diode is coupled to the first end of the transistor, and the cathode of the diode is coupled to the end point of the grid drive circuit receiving the operation power supply. The capacitor is coupled between the cathode of the diode and the second end of the transistor.

The alternator of the present invention comprises a rotor, a stator and a plurality of rectifying means as previously described. Each rectifying device receives a corresponding alternating current input voltage as an input voltage, and the rectifying devices jointly generate a rectified voltage.

In view of the above, the rectifying device of the present invention maintains a voltage difference across the transistor equal to a first reference voltage during a first time interval of the negative half cycle, the first reference voltage being generated as a product of an equivalent resistance of the pass transistor and a current flowing through the pass transistor, and maintains equal to a second reference voltage during a second time interval, wherein the first reference voltage may be greater than or less than or equal to the second reference voltage. Therefore, the power loss in the rectifying device can be reduced, and the working efficiency is improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 illustrates a waveform of a known rectified voltage;

FIG. 2 illustrates a schematic view of a fairing according to an embodiment of the invention;

FIG. 3A is a waveform diagram illustrating a voltage difference according to an embodiment of the invention;

FIGS. 3B and 3C are schematic diagrams illustrating voltage difference waveforms according to various embodiments of the present invention;

FIG. 4A is a waveform diagram illustrating voltage difference, transistor current, and gate voltage according to an embodiment of the present invention;

FIG. 4B is a partial enlarged waveform diagram of the voltage difference and the gate voltage in FIG. 4A;

FIG. 4C is a schematic diagram showing waveforms of the voltage difference, the transistor current and the gate voltage according to another embodiment of the present invention;

FIG. 4D is a partial enlarged waveform diagram of the voltage difference and the gate voltage in FIG. 4C;

FIG. 5 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;

FIG. 6 illustrates an implementation of a control signal generator according to an embodiment of the invention;

FIG. 7 shows a schematic diagram of an implementation of the counting action of the counter of an embodiment of the present invention;

FIG. 8 illustrates an implementation of a voltage generator according to an embodiment of the invention;

FIG. 9 shows a schematic view of a fairing of another embodiment of the invention;

fig. 10 shows a schematic view of an alternator according to an embodiment of the present invention.

The reference numbers illustrate:

200: rectifying device

210: gate drive circuit

500: gate drive circuit

600: control signal generator

610: selector device

620: counter with a memory

800: voltage generator

810: voltage regulator

820: reference voltage generator

900: rectifying device

910: gate drive circuit

1000: AC generator

1010. 1020, 1030: rectifying circuit

1011 to 1032: rectifying device

VP: voltage of

V0: reference voltage

TN: negative half cycle

TD 1: transistor with a metal gate electrode

VS: input voltage

VD: rectified voltage

VG: grid voltage

VDS: voltage difference

t1, t2, t 0: point in time

VDS _ ON: first predetermined threshold voltage

VDS _ OFF: second predetermined threshold voltage

TP 1: initial point in time

TP 2: second point in time

VDS _ SW 2: a first reference voltage

VDS _ REG: second reference voltage

TZ 1: a first time interval

TZ 2: second time interval

TZ 3: third time interval

IDS: transistor current

EN _ OPA, EN _ SW1, EN _ SW 2: control signal

VH: voltage of

OT: output end

OP 1: operational amplifier

SW1, SW 2: switch with a switch body

CMP 1: comparator with a comparator circuit

VCMP: comparison results

REFV: reference value

C (n): maximum count value

a 1: ratio value

VA and VC: power supply

VHH: operating power supply

DP: diode with a high-voltage source

CP, C1: capacitor with a capacitor element

RT: rotor

ST: stator

VU, VV, VW: phase voltage

R1: resistance (RC)

Detailed Description

Referring to fig. 2, fig. 2 is a schematic diagram of a rectifying device according to an embodiment of the invention. The rectifying device 200 includes a transistor TD1 and a gate driving circuit 210. The transistor TD1 has a first terminal receiving the input voltage VS, a second terminal of the transistor TD1 generating the rectified voltage VD, and a control terminal of the transistor TD1 receiving the gate voltage VG. In the present embodiment, the operation of the transistor TD1 is equivalent to a diode through the gate voltage VG, the first terminal of the transistor TD1 is equivalent to the cathode of the diode, and the second terminal of the transistor TD1 is equivalent to the anode of the diode.

The gate driving circuit 210 is coupled to the transistor TD1 and is used for providing a gate voltage VG. The gate driving circuit 210 receives a voltage difference VDs between the rectified voltage VD and the input voltage VS, and generates a gate voltage VG according to the voltage difference VDs. Regarding the generation details of the gate voltage VG, the gate driving circuit 210 detects the variation of the voltage difference VDS. The gate driving circuit 210 detects an initial time point when the voltage difference VDS is less than the first predetermined threshold voltage, and provides the gate voltage VG to turn on the transistor TD1 in a first time interval after the initial time point. Also, the voltage difference VDS may be equal to the first reference voltage under the condition that the transistor TD1 is turned on according to the gate voltage VG.

Then, the gate driving circuit 210 adjusts the equivalent resistance value provided by the transistor TD1 by adjusting the gate voltage VG in a second time interval after the first time interval, and makes the voltage difference VDS equal to a second reference voltage, wherein the first reference voltage may be greater than, less than or equal to the second reference voltage.

It should be noted that in the first time interval, the gate driving circuit 210, which is exemplified by the transistor TD1 being an N-type transistor, can provide the relatively high-voltage gate voltage VG to the control terminal of the transistor TD1 and make the transistor TD1 be fully turned on. In this case, the first reference voltage may be equal to the product of the on-resistance of the transistor TD1 that is fully turned on or not fully turned on and the current flowing through the transistor TD 1. If the transistor TD1 is in the fully turned-on state, the on-resistance of the transistor TD1 is very small, so the voltage difference VDS can be maintained to be equal to the first reference voltage close to 0 v. In a second time interval after the first time interval, the gate driving circuit 210 may decrease the voltage value of the gate voltage VG and increase the resistance of the transistor TD1 in the on state. At this time, the gate voltage VG provided by the gate driving circuit 210 can make the voltage difference VDS be the second reference voltage greater than, less than or equal to the first reference voltage. In one exemplary embodiment, the second reference voltage may be equal to about-70 millivolts (mV).

On the other hand, the gate driving circuit 210 determines the initial time point by detecting whether the voltage difference VDS is less than the first predetermined threshold voltage. In an embodiment of the invention, the first predetermined threshold voltage may be smaller than the first reference voltage and the second reference voltage. When the voltage difference VDS decreases to be lower than the first predetermined threshold voltage, the gate driving circuit 210 may determine an initial time point and start an adjustment mechanism of the gate voltage VG. In one embodiment, the first predetermined threshold voltage may be equal to-300 millivolts.

As can be seen from the above description, in the rectifying device 200 according to the embodiment of the invention, the gate driving circuit 210 adjusts the gate voltage VG to control the voltage value range of the voltage difference VDS lower than 0V, so as to effectively reduce the unnecessary power loss.

In continuation of the above embodiment, after the second time interval, the current flowing through the transistor TD1 becomes smaller as the input voltage changes. The voltage difference VDS starts to rise in a third time interval after the second time interval along with the adjustment of the gate voltage VG. The gate driving circuit 210 may also detect whether the voltage difference VDS increases from the second reference voltage to be equal to the second predetermined threshold voltage in a third time interval, and set a second time point when the voltage difference VDS increases to be equal to the second predetermined threshold voltage. Further, the gate driving circuit 210 turns off the transistor TD1 by adjusting the gate voltage VG after the second time point.

Referring to fig. 2 and fig. 3A, fig. 3A is a schematic diagram of waveforms of voltage differences according to an embodiment of the invention. The voltage difference VDS has a peak value of the voltage VP and has a reference voltage V0. The positive half cycle of the voltage difference VDS is between the time points t0 and t1, and the negative half cycle of the voltage difference VDS is between the time points t1 and t 2. After the time point t1, the gate driving circuit 210 detects whether the voltage difference VDS is lower than the first preset threshold voltage VDS _ ON, and sets an initial time point TP1 when the voltage difference VDS is lower than the first preset threshold voltage VDS _ ON.

In a first time interval TZ1 after the initial time point TP1, the gate driving circuit 210 may turn on the transistor TD1 by providing the gate voltage VG, and maintain the voltage difference VDS substantially equal to the first reference voltage VDS _ SW 2; here, the first reference voltage VDS _ SW2 is a product of an on-resistance of the transistor and a current flowing through the transistor.

Then, the gate driving circuit 210 may adjust the gate voltage VG to maintain the voltage difference VDS equal to the second reference voltage VDS _ REG in a second time interval TZ2 after the first time interval TZ 1.

In a third time zone TZ3 after the second time zone TZ2, the voltage difference VDS starts to rise as the current passing through the transistor TD1 decreases and the gate voltage VG is adjusted. Also, the gate driving circuit 210 may detect whether the voltage difference VDS is greater than the second preset threshold voltage VDS _ OFF, and set the second time point TP2 when the voltage difference VDS is greater than the second preset threshold voltage VDS _ OFF. The gate driving circuit 210 turns off the transistor TD1 by adjusting the gate voltage VG after the second time point TP 2.

In the embodiment, the second predetermined threshold voltage VDS _ OFF is greater than the first reference voltage VDS _ SW2, the first reference voltage VDS _ SW2 is greater than the second reference voltage VDS _ REG, and the second reference voltage VDS _ REG is greater than the first predetermined threshold voltage VDS _ ON.

In addition, referring to fig. 3B and 3C, fig. 3B and 3C show waveforms of the voltage difference according to different embodiments of the invention. Unlike the embodiment of fig. 3A, in fig. 3B, the first reference voltage VDS _ SW2 is smaller than the second reference voltage VDS _ REG. In fig. 3C, the first reference voltage VDS _ SW2 is equal to the second reference voltage VDS _ REG.

Referring to fig. 4A and 4B, fig. 4A is a schematic diagram illustrating waveforms of the voltage difference, the transistor current and the gate voltage according to the embodiment of the invention, and fig. 4B is a partial enlarged waveform diagram illustrating the voltage difference and the gate voltage in fig. 4A. In fig. 4A, in the first time interval TZ1, the gate voltage generator circuit adjusts the gate voltage VG to have a relatively high voltage value, and thereby the transistor is fully turned on and the voltage difference VDS is maintained to be substantially equal to the first reference voltage. During the second time interval TZ2 and the third time interval TZ3, the gate voltage generating circuit adjusts the gate voltage VG so that the voltage difference VDS is equal to the second reference voltage during the second time interval TZ2 and starts to slightly increase during the third time interval TZ 3. The gate voltage generating circuit provides the gate voltage VG with a relatively low voltage after the third time interval TZ3 is over, so that the transistor is turned off. In fig. 4A, the transistor current IDS varies periodically.

Regarding the relationship between the first reference voltage and the second reference voltage, fig. 4B may be referred to. In fig. 4, the voltage difference VDS may be equal to the first reference voltage VDS _ SW2 in the first time interval TZ1 by the gate voltage VG having a relatively high voltage. It should be noted that in fig. 4B, the voltage difference VDS is not rapidly equal to the first reference voltage VDS _ SW2 in the first time interval TZ1, but gradually approaches the first reference voltage VDS _ SW2 due to parasitic capacitance effects in circuit elements. Basically, the voltage difference VDS may be substantially equal to the first reference voltage VDS _ SW2 in the first time interval TZ 1.

During the second time interval TZ2, the gate driving circuit provides the gate voltage VG that gradually decreases, and the voltage difference VDS may be substantially equal to the second reference voltage VDS _ REG during the second time interval TZ 1.

In fig. 4A and 4B, the length of the third time zone TZ3 is short relative to the length of the second time zone TZ 2.

Referring to fig. 4C and fig. 4D, fig. 4C is a schematic diagram showing waveforms of the voltage difference, the transistor current and the gate voltage according to another embodiment of the invention, and fig. 4D is a partial enlarged waveform diagram of the voltage difference and the gate voltage shown in fig. 4C. In fig. 4C, in the first time interval TZ1, the gate voltage generator circuit adjusts the gate voltage VG to have a relatively low voltage value (relative to the second time interval TZ2), and thereby the transistor is partially turned on and the voltage difference VDS is substantially equal to the first reference voltage. During the second time interval TZ2 and the third time interval TZ3, the gate voltage generating circuit increases the gate voltage VG to make the voltage difference VDS equal to the second reference voltage during the second time interval TZ2 and to start to slightly increase during the third time interval TZ 3. As can be clearly seen from fig. 4D, the voltage difference VDS is substantially equal to the first reference voltage VDS _ SW2 in the first time interval TZ1, and is substantially equal to the second reference voltage VDS _ REG in the second time interval TZ2, wherein the first reference voltage VDS _ SW2 is smaller than the second reference voltage VDS _ REG.

Similarly, in fig. 4D, the voltage difference VDS is not quickly equal to the first reference voltage VDS _ SW2 in the first time interval TZ1, but gradually approaches the first reference voltage VDS _ SW2 due to parasitic capacitance effects in circuit elements. Basically, the voltage difference VDS may be substantially equal to the first reference voltage VDS _ SW2 in the first time interval TZ 1. The voltage difference VDS is not quickly equal to the second reference voltage VDS _ REG in the second time interval TZ2, but gradually approaches the second reference voltage VDS _ REG due to parasitic capacitance effects in circuit elements. Basically, the voltage difference VDS may be substantially equal to the second reference voltage VDS _ REG in the second time interval TZ 2.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating a gate driving circuit according to an embodiment of the invention. The gate driving circuit 500 includes an operational amplifier OP1, a switch SW1, and a switch SW 2. The operational amplifier OP1 receives the voltage difference VDS and an adjustment voltage as the second reference voltage VDS _ REG, and generates the gate voltage VG at the output terminal OT according to the control signal EN _ OPA. In addition, the operational amplifier OP1 receives the power supply VA as an operating power supply and receives the voltage VS as a ground reference voltage. The switch SW2 is connected in series between the voltage VH and the output terminal OT. The switch SW2 is turned on or off according to the control signal EN _ SW 2. The switch SW1 is connected in series between the voltage VS and the output terminal OT. The switch SW1 is turned on or off according to the control signal EN _ SW 1.

In detail, the gate driving circuit 500 disables the operational amplifier OP1 by the control signal EN _ OPA and turns on the switch SW2 by the control signal EN _ SW2 to pull up the gate voltage VG to the voltage VH after the initial time point (in the first time interval) when the voltage difference VDS is smaller than the first predetermined threshold voltage. At the same time, the switch SW1 is turned off according to the control signal EN _ SW 1. Then, in a second time interval after the first time interval, the gate driving circuit 500 turns off the switches SW2 and SW1 by the control signals EN _ SW2 and EN _ SW1, respectively, and turns on the operational amplifier OP1 by the control signal EN _ OPA. In the second time interval, the operational amplifier OP1 provides the gate voltage VG at the output terminal OT by controlling the voltage difference VDS to be equal to the second reference voltage VDS _ REG. Next, in a third time interval, the gate driving circuit 500 turns off the switch SW2 and disables the operational amplifier OP1 by controlling the signals EN _ SW2 and EN _ OPA, respectively. In the third time interval, the gate driving circuit 500 turns on the switch SW1 by the control signal EN _ SW 1. With switch SW1 turned on, gate voltage VG is pulled low to equal voltage VS and the transistor is turned off.

In the above embodiments, the control signals EN _ OPA, EN _ SW1 and EN _ SW2 can be generated by providing a control signal generator in the gate driving circuit 500. For an embodiment of the control signal generator, please refer to fig. 6. In fig. 6, the control signal generator 600 includes a selector 610, a comparator CMP1, and a counter 620. The selector 610 receives the first predetermined threshold voltage VDS _ ON and the second predetermined threshold voltage VDS _ OFF and is configured to select the first predetermined threshold voltage VDS _ ON or the second predetermined threshold voltage VDS _ OFF to be provided to the comparator CMP 1. The comparator CMP1 is coupled to the selector 610, and compares the voltage difference VDS with one of the first predetermined threshold voltage VDS _ ON and the second predetermined threshold voltage VDS _ OFF to generate the comparison result VCMP. It is noted that the comparison result VCMP can be fed back to the selector 610, so that the selector 610 can select one of the first predetermined threshold voltage VDS _ ON and the second predetermined threshold voltage VDS _ OFF to output according to the comparison result VCMP. To explain in detail, in the initial state, the selector 610 selects the first preset threshold voltage VDS _ ON to be output to the comparator CMP 1. The comparator CMP1 compares the voltage difference VDS with the first predetermined threshold voltage VDS _ ON, and adjusts the comparison result VCMP to make the selector 610 select the second predetermined threshold voltage VDS _ OFF to output to the comparator CMP1 when the voltage difference VDS is smaller than the first predetermined threshold voltage VDS _ ON (initial time).

Continuing with the above embodiment, the comparator CMP1 compares the voltage difference VDS with the second predetermined threshold voltage VDS _ OFF, and when the voltage difference VDS is greater than the second predetermined threshold voltage VDS _ OFF (the second time point), the selector 610 is changed to reselect the first predetermined threshold voltage VDS _ ON by adjusting the comparison result VCMP to output the first predetermined threshold voltage VDS _ ON to the comparator CMP 1.

On the other hand, please refer to fig. 6 and fig. 7 synchronously for the counting operation of the counter 620, wherein fig. 7 illustrates a schematic diagram of an implementation of the counting operation of the counter according to the embodiment of the present invention. The counter 620 is coupled to the comparator CMP1 and performs a counting operation according to the comparison result VCMP. The counting action of the counter 620 starts at an initial point in time TP1 and ends at a second point in time TP 2. The counting operation of the counter 620 may generate a gradually changing (increasing or decreasing) count value. Taking the count up operation as an example, the counter 620 may set the gate driving circuit to operate in the first time interval TZ1 when the count value is smaller than a reference value REFV, and set the gate driving circuit to operate in the second time interval TZ2 or the third time interval TZ3 when the count value is between the reference value REFV and the maximum count value c (n). The counter 620 generates the corresponding control signals EN _ OPA, EN _ SW1 and EN _ SW2 according to the operation of the gate driving circuit in the first time interval TZ1, the second time interval TZ2 or the third time interval TZ 3.

Regarding the setting of the above-mentioned reference value REFV, the product of the maximum count value C (n) of the counting operation and a proportional value a1, wherein the proportional value a1 is greater than or equal to 0 and less than or equal to 1, wherein C (n-1) in the figure is the length from the initial time point TP1 to the second time point TP2 in the previous cycle.

ON the other hand, in the embodiment of fig. 5, the voltage VH, the second reference voltage VDS _ REG, the first predetermined threshold voltage VDS _ ON, the second predetermined threshold voltage VDS _ OFF, the power supply VA and the power supply VC can be generated by providing a voltage generator in the gate driving circuit 500. For an embodiment of the voltage generator, please refer to fig. 8. In fig. 8, a voltage generator 800 includes a voltage regulator 810 and a reference voltage generator 820. The voltage regulator 810 receives the operating power VHH and performs a voltage regulation operation according to the operating power VHH to generate a voltage VH, a power VA, and a power VC. The reference voltage generator 820 also receives the operating power VHH and is configured to generate a second reference voltage VDS _ REG, a first predetermined threshold voltage VDS _ ON, and a second predetermined threshold voltage VDS _ OFF.

The hardware architecture of the voltage regulator 810 and the reference voltage generator 820 can be implemented by any voltage generation circuit known to those skilled in the art, and is not limited in any way.

Referring to fig. 9, fig. 9 is a schematic view of a rectifying device according to another embodiment of the invention. The rectifying device 900 includes a transistor TD1, a gate driving circuit 910, a diode DP, and a capacitor CP. The gate driving circuit 910 can be implemented by using the gate driving circuit 500 described above. The anode of the diode DP is coupled to the first terminal of the transistor TD1, and the cathode of the diode DP is coupled to the terminal of the gate driving circuit 910 receiving the operation power VHH. The capacitor CP is coupled between the cathode of the diode DP and the second terminal of the transistor TD 1.

Referring to fig. 10, fig. 10 is a schematic diagram of an alternator according to an embodiment of the present invention. The alternator 1000 includes a rotor RT, a stator ST, and a plurality of rectifying devices 1011 to 1032. In the present embodiment, the stator ST generates a plurality of phase voltages VU, VV and VW. The phase voltages VU, VV, and VW are supplied to a plurality of

rectifier circuits

1010, 1020, and 1030 of different phases, respectively. The rectifying circuit 1010 includes rectifying devices 1011 and 1012 coupled in series, the rectifying circuit 1020 includes rectifying

devices

1021 and 1022 coupled in series, and the rectifying circuit 1030 includes rectifying

devices

1031 and 1032 coupled in series. In the present embodiment, the alternator 1000 further includes a resistor R1 (equivalent resistance of an equivalent load or a charging battery) and a capacitor C1 (equivalent charging capacitor) coupled in parallel to generate a rectified output voltage close to dc.

In summary, the gate driving circuit generates the gate voltage, and the voltage value of the voltage difference of the controller is controlled by the gate voltage in the negative half cycle of the voltage difference between the two ends of the transistor. Therefore, the power loss possibly generated by the rectifying device can be reduced, and the working efficiency is improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A fairing, comprising:

a transistor having a first terminal receiving an input voltage, a second terminal generating a rectified voltage, and a control terminal receiving a gate voltage; and

a gate driving circuit coupled to the transistor for generating the gate voltage according to a voltage difference between the rectified voltage and the input voltage,

the gate driving circuit detects an initial time point when the voltage difference is smaller than a first preset threshold voltage, provides the gate voltage to turn on the transistor in a first time interval after the initial time point, and enables the voltage difference to be substantially equal to a first reference voltage; the gate driving circuit adjusts the gate voltage to make the voltage difference substantially equal to a second reference voltage in a second time interval after the first time interval.

2. The rectifying device of claim 1, wherein the first reference voltage is greater than, less than, or equal to the second reference voltage.

3. The rectifying device of claim 1, wherein the first reference voltage is equal to a product of an on-resistance of the transistor and a current flowing through the transistor.

4. The rectifying device according to claim 1, wherein the gate driving circuit detects a second time point when the voltage difference rises from the second reference voltage to a second predetermined threshold voltage in a third time interval after the second time interval, and adjusts the gate voltage to turn off the transistor after the second time point.

5. The rectifying device of claim 4, wherein the gate drive circuit comprises:

the operational amplifier receives the voltage difference and the adjusting voltage and generates the grid voltage at an output end according to a first control signal;

the first switch is connected between the first voltage and the output end in series and is switched on or off according to a second control signal; and

a second switch connected in series between the second voltage and the output terminal and turned on or off according to a third control signal,

wherein the adjustment voltage is equal to the second reference voltage.

6. The rectifying device of claim 5, wherein the gate drive circuit further comprises:

the control signal generator compares the voltage difference with the first preset threshold voltage or the second preset threshold voltage to generate a comparison result, and generates the first control signal, the second control signal and the third control signal according to the comparison result.

7. The rectification apparatus according to claim 6, wherein said control signal generator comprises:

the comparator receives the voltage difference and the selected voltage and generates a comparison result;

a selector coupled to the comparator for selecting the first predetermined threshold voltage or the second predetermined threshold voltage to generate the selected voltage; and

the counter is coupled to the comparator, performs a counting operation according to the comparison result, and generates the first control signal, the second control signal and the third control signal.

8. The rectification device of claim 7, wherein the counter performs the counting action between the first point in time and the second point in time to generate a count value,

the counting value is a first time interval when the counting value is smaller than a reference value, and the counting value is a second interval or a third time interval when the counting value is between the reference value and a maximum counting value.

9. The rectifying device of claim 7, wherein the gate drive circuit further comprises:

the voltage generator generates the second voltage, the second reference voltage, the first predetermined threshold voltage and the second predetermined threshold voltage according to an operating power.

10. The rectifying device of claim 9, wherein the voltage generator comprises:

a voltage regulator for generating the second voltage according to the operation power supply and generating a first power supply and a second power supply for the operational amplifier and the counter; and

the reference voltage generator generates the first preset threshold voltage, the second preset threshold voltage and the adjusting voltage according to the operating power supply.

11. The fairing as recited in claim 1, further comprising:

a diode having an anode coupled to the first terminal of the transistor and a cathode coupled to a terminal of the gate driving circuit receiving an operating power; and

and the capacitor is coupled between the cathode of the diode and the second end of the transistor.

12. An alternator comprising:

a rotor;

a stator coupled to the rotor and generating a plurality of ac input voltages; and

a plurality of rectifying devices according to any one of claims 1 to 11, each of said rectifying devices receiving a corresponding ac input voltage as said input voltage, said plurality of rectifying devices collectively generating said rectified voltage.