CN114499112A - Alternating-current generator and rectifying device thereof - Google Patents

Abstract

The invention provides a rectifying device capable of preventing reverse current. The rectifying device comprises a transistor and a grid voltage control circuit. The control terminal of the transistor receives the gate voltage. The grid voltage control circuit generates a grid voltage according to the voltage difference of the input voltage and the rectified voltage. The gate voltage control circuit detects a first time point when the voltage difference is smaller than a first default threshold voltage, provides a gate voltage to turn on the transistor in a first time interval after the first time point, and makes the voltage difference equal to a first reference voltage. The grid voltage control circuit adjusts the grid voltage to enable the voltage difference to be equal to a second reference voltage in a second time interval after the first time interval, wherein the first time interval is independent of the period of the input voltage. The invention also provides an alternating current generator.

Description

Alternating-current generator and rectifying device thereof

Technical Field

The present invention relates to an ac generator and a rectifying device thereof, and more particularly, to a rectifying device capable of preventing generation of a reverse current.

Background

In an alternator, a rectifier device is often used to rectify an ac input voltage and generate a rectified voltage that can be considered a dc voltage. In the prior art, a diode or a transistor is often used to perform an operation of rectifying an input voltage. Ideally, the rectified voltage should be maintained at a voltage equal to the reference voltage (e.g., 0 volts) during the negative half cycle, but in practical cases, as shown in the waveform diagram of the conventional rectified voltage shown in fig. 1, the rectified voltage having a peak value of the voltage VP may be lower than the reference voltage V0 during the negative half cycle TN. That is, in the negative half period TN of the rectified voltage, a power loss (power loss) phenomenon occurs, which reduces the operating efficiency of the system.

In the prior art, a rectifier device can be implemented by using a transistor, and achieves a rectifying action by actively turning on and off the transistor. However, when the time points of the transistors being turned on and off are not well set, a reverse current phenomenon may occur, so that the performance of the system is degraded.

Disclosure of Invention

The invention aims at an alternating current generator and a rectifying device thereof, which can prevent the generation of a reverse current phenomenon.

According to an embodiment of the present invention, the rectifying means includes a transistor to communicate with the gate voltage control circuit. The transistor has a first terminal receiving an alternating input voltage, a second terminal generating a rectified voltage, and a control terminal receiving a gate voltage. The gate voltage control circuit is coupled to the transistor and generates a gate voltage according to a voltage difference between the input voltage and the rectified voltage. The grid voltage control circuit detects a first time point when the voltage difference is smaller than a first default critical voltage, provides a grid voltage to turn on the transistor in a first time interval after the first time point, and enables the voltage difference to be substantially equal to a first reference voltage; the grid voltage control circuit adjusts the grid voltage to enable the voltage difference to be substantially equal to the second reference voltage in a second time interval after the first time interval, wherein the first time interval is independent of the period of the input voltage.

The alternator of the present invention comprises a rotor, a stator and a plurality of rectifying devices as described above. The stator is coupled to the rotor. Each rectifying device receives each corresponding input voltage. The rectifying devices collectively generate the rectified voltage.

According to the above, the gate voltage control circuit of the present invention turns on the transistor rapidly when the voltage difference between the two ends of the transistor is smaller than the first default threshold voltage, and maintains the on state in a fixed first time interval. By adjusting the conduction mechanism of the transistor, the rectifying device can prevent the reverse current phenomenon generated in the rectifying process.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 shows a waveform diagram of a prior art rectified voltage;

FIG. 2 illustrates a schematic view of a fairing according to an embodiment of the invention;

FIG. 3 illustrates a waveform of operation of an embodiment of a rectifier device according to an embodiment of the present invention;

FIG. 4 shows a circuit schematic of an implementation of a gate voltage control circuit of an embodiment of the present invention;

FIG. 5 is a schematic diagram of another circuit of the gate voltage control circuit according to the embodiment of the invention;

FIG. 6 illustrates a waveform of an operation of another embodiment of a rectifier device in accordance with an embodiment of the present invention;

FIG. 7 is a circuit diagram illustrating an implementation of a gate voltage control circuit according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of another circuit portion of a gate voltage control circuit according to an embodiment of the present invention;

FIG. 9 is a waveform diagram illustrating a rectified voltage difference according to an embodiment of the present invention;

fig. 10 shows a schematic view of an alternator according to an embodiment of the present invention.

Description of the reference numerals

1000: an alternator;

1010. 1020, 1030: a rectifying circuit;

1011 to 1032: a rectifying device;

200: a rectifying device;

210. 400 and 700: a gate voltage control circuit;

810. 510: a comparator;

820. 520, the method comprises the following steps: a counter;

c1: a capacitor;

CM 1-CM 3: comparing the results;

EN _ OPA, EN _ SW1, EN _ SW2, EN _ SW 3: a control signal;

OP 1: an operational amplifier;

OT: an output end;

RT: a rotor;

ST: a stator;

SW1, SW2, SW 3: a switch;

t1, t2, t3, TP1 to TP 3: a point in time;

TD 1: a transistor;

TN: negative half cycle;

TZ 1-TZ 6: a time interval;

v0: a reference voltage;

VA: a power source;

VD: rectifying the voltage;

VDS: a voltage difference;

VDS _ CLP, VG _ CLP: clamping a voltage;

VDS _ ON, VDS _ OFF: a default threshold voltage;

VDS _ SW2, VDS _ REG, VH: a reference voltage;

VG: a gate voltage;

VGND, VP: a voltage;

VS: inputting a voltage;

VU, VV, VW: phase voltages.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 2, fig. 2 is a schematic diagram of a rectifying device according to an embodiment of the invention. The rectifying device 200 includes a transistor TD1 and a gate voltage control circuit 210. The transistor TD1 has a first terminal receiving the input voltage VS, a second terminal of the transistor TD1 generating the rectified voltage VD, and a control terminal of the transistor TD1 receiving the gate voltage VG. In the present embodiment, the operation of the transistor TD1 is equivalent to a diode through the gate voltage VG, the first terminal of the transistor TD1 is equivalent to the cathode of the diode, and the second terminal of the transistor TD1 is equivalent to the anode of the diode.

The gate voltage control circuit 210 is coupled to the transistor TD1 and is used for providing a gate voltage VG. The gate voltage control circuit 210 receives a voltage difference VDs between the input voltage VS and the rectified voltage VD and generates a gate voltage VG according to the voltage difference VDs. For details of generation of the gate voltage VG, please refer to fig. 2 and fig. 3 synchronously, wherein fig. 3 illustrates an operation waveform diagram of an embodiment of the rectifying device according to the present invention. In fig. 3, the voltage difference VDS has a peak value of the voltage VP and has the reference voltage V0. The positive half cycle of the voltage difference VDS is between time points t0 and t1, and the negative half cycle of the voltage difference VDS is between time points t1 and t 2. After the time point t1, the gate driving circuit 210 detects whether the voltage difference VDS is lower than the first default threshold voltage VDS _ ON, and sets the first time point TP1 when the voltage difference VDS is lower than the first default threshold voltage VDS _ ON.

When the first time point TP1 is detected, the gate voltage control circuit 210 can continuously provide the gate voltage VG capable of turning on the transistor TD1 during the first time interval TZ1 with the first time point TP1 as a starting point. The voltage difference VDS may be substantially equal to the first reference voltage VDS _ SW2 by the conductive state of the transistor TD 1. Here, the first reference voltage VDS _ SW2 may be a product of an on-resistance of the transistor TD1 and a current flowing through the transistor TD 1.

Then, in a second time interval TZ2 after the first time interval TZ1 ends, the gate voltage control circuit 210 may adjust the gate voltage VG so that the voltage difference VDS is maintained to be equal to the second reference voltage VDS _ REG. In the present embodiment, the second reference voltage VDS _ REG may be lower than the first reference voltage VDS _ SW 2. In other embodiments of the present invention, the second reference voltage VDS _ REG may be equal to or higher than the first reference voltage VDS _ SW2 without limitation.

Note that the length of the first time interval TZ1 is fixed. To be further explained, the first time interval TZ1 is independent of the period of the input voltage VS, and has no relation. The length of the first time interval TZ1 can be set by a designer, and when the period of the input voltage VS varies, the first time interval TZ1 does not vary accordingly.

Incidentally, in some implementations of the invention, the time length of the first time interval TZ1 may be equal to 0 second.

In a third time interval t3 after the second time interval TZ2, the voltage difference VDS begins to rise due to the rapid decrease of the current flowing through the transistor TD1 and the adjustment operation of the gate voltage VG. The gate voltage control circuit 210 detects a second time point TP2 when the voltage difference VDS rises to be equal to the second default threshold voltage VDS _ OFF. The gate voltage control circuit 210 adjusts the gate voltage VG after the second time point TP2 to turn off the transistor TD 1.

In the present embodiment, the second default threshold voltage VDS _ OFF is greater than the first reference voltage VDS _ SW 2. In addition, both the first reference voltage VDS _ SW2 and the second reference voltage VDS _ REG in the present embodiment may be less than 0 volt, and achieve the effect of a negative current protection level.

Regarding the hardware architecture of the gate voltage control circuit 210, reference may be made to fig. 4, where fig. 4 shows a circuit schematic diagram of an implementation of the gate voltage control circuit according to an embodiment of the present invention. The gate voltage control circuit 400 includes an operational amplifier OP1, switches SW1 and SW 2. The operational amplifier OP1 receives the voltage difference VDS and an adjustment voltage as the second reference voltage VDS _ REG, and generates the gate voltage VG at the output terminal OT according to the control signal EN _ OPA. In addition, the operational amplifier OP1 receives the power supply VA as an operating power supply and receives the ground voltage VGND as a reference ground voltage. The switch SW2 is connected in series between the third reference voltage VH and the output terminal OT. The switch SW2 is turned on or off according to the control signal EN _ SW 2. The switch SW1 is connected in series between the ground voltage VGND and the output terminal OT. The switch SW1 is turned on or off according to the control signal EN _ SW 1. The positive and negative input terminals of the operational amplifier OP1 respectively receive the second reference voltage (i.e. the regulated voltage) VDS _ REG and the voltage difference VDS.

Corresponding to the embodiment of fig. 3, the gate voltage control circuit 400 generates the control signal EN _ SW2 to maintain the switch SW2 turned ON during the first time interval TZ1 at the first time point TP1 when detecting that the voltage difference VDS is lower than the first default threshold voltage VDS _ ON. At the same time, the switch SW1 is turned off according to the control signal EN _ SW1, and the operational amplifier OP1 is deactivated (disabled) according to the control signal EN _ OPA. The gate voltage VG at the output terminal OT of the gate voltage control circuit 400 is equal to a third reference voltage VH having a voltage value larger than the turn-on voltage of the transistor TD1 according to the turned-on switch SW 2. At this time, the gate voltage VG may cause the transistor TD1 to be turned on (e.g., fully turned on), and the voltage difference VDS is limited to be equal to the first reference voltage VDS _ SW 2.

The gate voltage control circuit 400 turns off the switches SW1 and SW2 by the generated control signals EN _ SW1 and EN _ SW2 respectively in the second time interval TZ2 after the first time interval TZ1 is maintained for a fixed time length, and turns on (enables) the operational amplifier OP1 by the control signal EN _ OPA. At this time, the gate voltage VG is dominated by the operational amplifier OP 1. The operational amplifier OP1 adjusts the voltage difference VDS according to the second reference voltage VDS _ REG, so that the voltage difference VDS may be equal to the second reference voltage VDS _ REG.

In the time interval TZ3, the voltage difference VDS gradually increases as the current through the transistor TD1 decreases and the gate voltage VG generated by the operational amplifier OP1 acts. The gate voltage control circuit 400 turns OFF the switch SW2 by the control signals EN _ SW2 and EN _ OPA respectively after the voltage difference VDS rises to a second time point TP2 equal to the second default threshold voltage VDS _ OFF, and the operational amplifier OP1 stops working; and the switch SW1 is turned on by the control signal EN _ SW 1. At this time, the gate voltage VG is pulled down to the ground voltage VGND according to the turned-on switch SW 1. The transistor TD1 is turned off according to the gate voltage VG equal to the ground voltage VGND.

The circuit of the operational amplifier OP1 in the present embodiment can be implemented by a differential amplifier known to those skilled in the art, and the switches SW1 and SW2 in the present embodiment can be implemented by electronic components (such as transistors) known in the semiconductor field, without any particular limitation.

Referring to fig. 3 to 5 synchronously, fig. 5 is a schematic diagram of another circuit portion of the gate voltage control circuit according to the embodiment of the invention. The gate voltage control circuit 400 further includes a comparator 510 and a counter 520. The comparator 510 receives the voltage difference VDS, the first default threshold voltage VDS _ ON, and the second default threshold voltage VDS _ OFF. The first default threshold voltage VDS _ ON and the second default threshold voltage VDS _ OFF may be default voltages. The comparator 510 may compare the voltage difference VDS with the first default threshold voltage VDS _ ON to generate the comparison result CM1, and compare the voltage difference VDS with the second default threshold voltage VDS _ OFF to generate the comparison result CM 2. The comparison result CM1 may be used to determine the first time point TP1, and the comparison result CM2 may be used to determine the second time point TP 2.

In another aspect, the counter 520 may perform a counting action based on a clock signal. The counter 520 may start counting according to the comparison result CM1, wherein the counter 520 may start counting when the comparison result CM1 indicates that the first time point TP1 is detected. The counter 520 may have a default counting target value, and the counting operation is stopped when the counting result of the counter 520 is equal to the counting target value. The duration of the counting operation of the counter 520 may be used to define a first time interval TZ 1.

It should be noted that the counting target value is a fixed value and is independent of the period of the input voltage VS.

Additionally, the gate voltage control circuit 400 may generate the control signal EN _ SW2 according to the first time interval TZ1 counted by the counter 520, and maintain the switch SW2 in a turned-on state in the first time interval TZ 1. The gate voltage control circuit 400 further generates a control signal EN _ SW1 to turn on the switch SW1 according to the comparison result CM 2. The gate voltage control circuit 400 further generates a control signal EN _ OPA according to the comparison results CM1 and CM2, and maintains the operational amplifier OP1 in an activated state during the second time interval TZ2 (between the end time point of the first time interval TZ1 and the second time point TP 2).

Referring to fig. 2 and fig. 6 synchronously, fig. 6 is a waveform diagram of an operation of another embodiment of a rectifying device according to an embodiment of the invention. In fig. 6, the gate voltage control circuit 210 determines that the voltage difference VDS drops to a first time point TP1 equal to the first default threshold voltage VDS _ ON, and provides the gate voltage VG to turn ON the transistor TD1 in a first time interval TZ 1. During the time interval TZ1, the voltage difference VDS can be adjusted to be substantially equal to the first reference voltage VDS _ SW 2. In the present embodiment, the first time interval TZ1 is maintained for a fixed time length, which is independent and independent from the period of the input voltage VS.

After the first time interval TZ1 is over, in the second time interval TZ2, the gate voltage control circuit 210 makes the gate voltage VG equal to the second reference voltage VDS _ REG, and controls the transistor TD1 so that the voltage difference VDS may be equal to the second reference voltage VDS _ REG in a steady state. In the third time interval TZ3, the current flowing through the transistor TD1 decreases, and the voltage difference VDS gradually increases along with the gate voltage VG. The gate voltage control circuit 210 can detect that the voltage difference VDS rises to the second time point TP2 equal to the first clamped voltage VDS _ CLP. The gate voltage control circuit 210 enters the fourth time interval TZ4 after the second time point TP 2.

In the fourth time interval TZ4, the gate voltage control circuit 210 makes the gate voltage VG equal to the second clamped voltage VG _ CLP. At this time, the transistor TD1 has a relatively high impedance and is in a state of providing only a small amount of current flow according to the gate voltage VG equal to the second clamping voltage VG _ CLP. At this time, the transistor TD1 may operate in a sub-critical region or a saturation region. The voltage difference VDS at this time is close to and slightly lower than the second reference voltage VDS _ REG based on that the transistor TD1 only provides a small amount of current to pass through at this time. In other embodiments of the present invention, the voltage difference VDS at this time may be slightly higher than the second reference voltage VDS _ REG, and there is no specific limitation.

Please note that the fourth time interval TZ4 can be maintained for a predetermined fixed time. The time length of the fourth time interval TZ4 may be determined by the designer without limitation.

In a fifth time interval TZ5 after the fourth time interval TZ4 is over, the gate voltage control circuit 210 may provide the gate voltage VG according to the difference between the second reference voltage VDS _ REG and the voltage difference VDS, and make the voltage difference VDS equal to the second reference voltage VDS _ REG in a steady state. Then, in the sixth time interval TZ6, the voltage difference VDS may rise rapidly. When the gate voltage control circuit 210 detects that the voltage difference VDS rises to the third time point TP3 equal to the second default threshold voltage VDS _ OFF, the gate voltage control circuit 210 pulls down the voltage value of the gate voltage VG and turns OFF the transistor TD 1.

Referring to fig. 6 and fig. 7 synchronously, fig. 7 is a circuit diagram of a gate voltage control circuit according to another embodiment of the invention. The gate voltage control circuit 700 includes an operational amplifier OP1, switches SW1, SW2 and SW 3. The operational amplifier OP1 receives the voltage difference VDS and an adjustment voltage as the second reference voltage VDS _ REG, and generates the gate voltage VG at the output terminal OT according to the control signal EN _ OPA. In addition, the operational amplifier OP1 receives the power supply VA as an operating power supply and receives the ground voltage VGND as a reference ground voltage. The switch SW2 is connected in series between the third reference voltage VH and the output terminal OT. The switch SW2 is turned on or off according to the control signal EN _ SW 2. The switch SW1 is connected in series between the ground voltage VGND and the output terminal OT. The switch SW1 is turned on or off according to the control signal EN _ SW 1. The switch SW3 is coupled between the output terminal OT and the second clamped voltage VG _ CLP, and is turned on or off according to the control signal EN _ SW 3. The positive and negative input terminals of the operational amplifier OP1 respectively receive the second reference voltage (i.e. the regulated voltage) VDS _ REG and the voltage difference VDS.

In accordance with the waveform diagram of fig. 6, when the first time point TP1 is detected, the gate voltage control circuit 700 turns on the switch SW2 by the control signal EN _ SW2 and turns off the switch SW1 by the control signal EN _ SW1 in the first time interval TZ 1; the operational amplifier OP1 is disabled by the control signal EN _ OPA. The gate voltage VG at this time is equal to the third reference voltage VH and has a voltage value high enough to turn on the transistor TD 1.

In a second time interval TZ2 after the first time interval TZ1 is over, the gate voltage control circuit 700 turns off the switches SW1, SW2, and SW3 by the control signals EN _ SW1, EN _ SW2, and EN _ SW3, respectively, and turns on the operational amplifier OP1 by the control signal EN _ OPA. In the second time interval TZ2, the operational amplifier OP1 generates the gate voltage VG according to the difference between the second reference voltage VDS _ REG and the voltage difference VDS, and controls the transistor TD1 to make the voltage difference VDS equal to the second reference voltage VDS _ REG in a steady state.

In the third time interval TZ3, the voltage difference VDS may gradually increase based on the current of the pass transistor TD1 decreasing. The gate voltage control circuit 700 detects a second time point TP2 when the voltage difference VDS is equal to the first clamped voltage VDS _ CLP. The gate voltage control circuit 700 further turns on the switch SW3 (switches SW1 and SW2 are turned off, and the operational amplifier OP1 is disabled) by the control signal EN _ SW3 in a fourth time interval TZ4 after the second time point TP 2. And the gate voltage VG is made equal to the second clamped voltage VG _ CLP by the turned-on switch SW 3.

In a fifth time interval TZ5 after the fourth time interval TZ4, the switches SW1 to SW3 are all turned off, and the operational amplifier OP1 is activated. In the fifth time interval TZ5, the voltage difference VDS between the two terminals of the transistor TD1 may be equal to the second reference voltage VDS _ REG by the gate voltage VG.

In the sixth time interval TZ6, the voltage difference VDS gradually rises based on the current through the transistor TD1 falling. The gate voltage control circuit 700 detects a third time point TP3 when the voltage difference VDS rises to the second threshold voltage VDS _ OFF, and generates the control signal EN _ SW1 according to the third time point TP3 to turn on the switch SW 1. At the same time, switches SW2, SW3 are open and operational amplifier OP1 is disabled. In this way, the transistor TD1 is turned off.

Referring to fig. 6, fig. 7 and fig. 8 synchronously, fig. 8 is a schematic diagram of another circuit portion of the gate voltage control circuit according to the embodiment of the invention. In fig. 8, the gate voltage control circuit 700 further includes a comparator 810 and a counter 820. The comparator 810 receives the first default threshold voltage VDS _ ON, the second default threshold voltage VDS _ OFF, the first clamping voltage VDS _ CLP and the voltage difference VDS. The comparator 810 compares the voltage difference VDS with a first default threshold voltage VDS _ ON, a second default threshold voltage VDS _ OFF, and a first clamped voltage VDS _ CLP, which are preset, and generates comparison results CM1, CM3, and CM2, respectively. The comparison results CM1, CM3, and CM2 may be used to determine the first time point TP1, the third time point TP3, and the second time point TP2, respectively.

The counter 820 receives the comparison results CM1 and CM2, and performs a counting operation of a first time interval TZ1 after the first time point TP1, and performs a counting operation of a fourth time interval TZ4 after the second time point TP 2. In addition, the gate voltage control circuit 700 may generate the control signals EN _ SW1, EN _ SW2, EN _ SW3 and EN _ OPA according to the first time interval TZ1, the fourth time interval TZ4 and the comparison result CM 3.

Similarly, the circuit of the operational amplifier OP1 in the present embodiment can be implemented by a differential amplifier known to those skilled in the art, and the switches SW1, SW2 and SW3 in the present embodiment can be implemented by electronic components (such as transistors) known in the semiconductor field, without any particular limitation.

Fig. 9 is a schematic diagram of waveforms of rectified voltage differences according to an embodiment of the present invention. In this embodiment, the rectifying device can maintain the rectified voltage difference VDS at a voltage value lower than 0 volt during the negative half cycle. In detail, the waveform of fig. 3 is taken as an example, wherein the voltage value of the voltage difference VDS may be a negative voltage in the first time interval TZ1 and the second time interval TZ 2. Therefore, the effect of negative current protection level can be achieved.

Referring to fig. 10, fig. 10 is a schematic diagram of an alternator according to an embodiment of the present invention. The alternator 1000 includes a rotor RT, a stator ST, and a plurality of rectifying devices 1011 to 1032. In the present embodiment, the stator ST generates a plurality of phase voltages VU, VV and VW. The phase voltages VU, VV, and VW are supplied to a plurality of rectifier circuits 1010, 1020, and 1030 of different phases, respectively. The rectifying circuit 1010 includes rectifying devices 1011 and 1012 coupled in series, the rectifying circuit 1020 includes rectifying devices 1021 and 1022 coupled in series, and the rectifying circuit 1030 includes rectifying devices 1031 and 1032 coupled in series. In the present embodiment, the alternator 1000 further includes a resistor R1 (equivalent resistance of an equivalent load or a charging battery) and a capacitor C1 (equivalent charging capacitor) coupled in parallel to generate a rectified output voltage close to dc. The rectifying devices 1011 to 1032 in the present embodiment can be implemented by applying any one of the rectifying devices 200, 400, and 700 of the foregoing embodiments. The details of the foregoing embodiments have been described in detail, and are not repeated herein.

In summary, the rectifying device of the present invention enables the transistor to be turned on quickly and maintain the turned-on state in a fixed first time interval after the first time point when the voltage difference is smaller than the first default threshold voltage, so as to prevent the transistor from being turned on too slowly to generate a poor efficiency state. In addition, in another embodiment of the present invention, the rectifying device compares the voltage difference with the first clamping voltage, and the time point when the transistor is turned off is slowed down, so that the reverse current generated by the transistor being turned off too slowly can be effectively prevented. Based on the above, the present invention can effectively adjust the on/off time of the transistor, prevent the reverse current generated in the rectification process, and maintain the system performance.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (11)

1. A fairing, comprising:

a transistor having a first terminal receiving an alternating input voltage, a second terminal generating a rectified voltage, and a control terminal receiving a gate voltage; and

a gate voltage control circuit coupled to the transistor for generating the gate voltage according to a voltage difference between the input voltage and the rectified voltage,

the grid voltage control circuit detects a first time point when the voltage difference is smaller than a first default critical voltage, provides the grid voltage to turn on the transistor in a first time interval after the first time point, and enables the voltage difference to be substantially equal to a first reference voltage; the grid voltage control circuit adjusts the grid voltage to enable the voltage difference to be substantially equal to a second reference voltage in a second time interval after the first time interval, wherein the first time interval is independent of the period of the input voltage.

2. The rectifying device of claim 1, wherein the first reference voltage is less than 0 volts.

3. The rectifying device as claimed in claim 1, wherein the gate voltage control circuit detects a second time point when the voltage difference rises from the second reference voltage to the second default threshold voltage in a third time interval after the second time interval, and adjusts the gate voltage to turn off the transistor after the second time point.

4. The rectifying device of claim 3, wherein the gate voltage control circuit comprises:

the operational amplifier receives the voltage difference and an adjusting voltage, and is started in the second time interval to generate the grid voltage according to the voltage difference and the adjusting voltage;

a first switch connected in series between a ground voltage and an output terminal of the operational amplifier, and turned on in the third time interval; and

a second switch connected in series between a third reference voltage and the output terminal and turned on during the first time interval,

wherein the adjustment voltage is equal to the second reference voltage.

5. The fairing as recited in claim 4, further comprising:

a voltage comparator for comparing the voltage difference with the first default threshold voltage and the second default threshold voltage to generate the first time point and the second time point; and

a counter for counting the first time interval.

6. The rectifying device according to claim 5, wherein the gate voltage control circuit detects a second time point when the voltage difference rises from the second reference voltage to the first clamped voltage in a third time interval after the second time interval, and makes the gate voltage equal to the second clamped voltage in a fourth time interval after the second time point.

7. The rectifying device of claim 6, wherein the gate voltage control circuit adjusts the gate voltage to make the voltage difference substantially equal to the second reference voltage in a fifth time interval after the fourth time interval.

8. The rectifying device as claimed in claim 7, wherein the gate voltage control circuit detects a third time point when the voltage difference rises from the second reference voltage to the second default threshold voltage in a sixth time interval after the fifth time interval, and adjusts the gate voltage to turn off the transistor after the third time point.

9. The rectifying device of claim 8, wherein the gate voltage control circuit comprises:

an operational amplifier, receiving the voltage difference and an adjustment voltage, being enabled in the second time interval and the fifth time interval to generate the gate voltage according to the voltage difference and the adjustment voltage;

a first switch connected in series between a ground voltage and an output terminal of the operational amplifier, and turned on in the third time interval; and

a second switch connected in series between a third reference voltage and the output terminal and turned on during the first time interval,

a third switch connected in series between the second clamped voltage and the output terminal and turned on during the fourth time interval,

wherein the adjustment voltage is equal to the second reference voltage.

10. The rectifying device of claim 8, wherein the gate voltage control circuit further comprises:

a voltage comparator for comparing the voltage difference with the first default threshold voltage, the first clamped voltage, and the second default threshold voltage to generate the first time point, the second time point, and the third time point; and

a counter for counting the first time interval and the fourth time interval.

11. An alternator comprising:

a rotor;

a stator coupled to the rotor; and

a plurality of rectifying devices according to any one of claims 1 to 10, each of said rectifying devices receiving a corresponding ac input voltage as said input voltage, a plurality of said rectifying devices collectively generating said rectified voltage.

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