CN111433666A - Display device, electronic device, array test structure and array test method - Google Patents
Display device, electronic device, array test structure and array test method Download PDFInfo
- Publication number
- CN111433666A CN111433666A CN201780097385.XA CN201780097385A CN111433666A CN 111433666 A CN111433666 A CN 111433666A CN 201780097385 A CN201780097385 A CN 201780097385A CN 111433666 A CN111433666 A CN 111433666A
- Authority
- CN
- China
- Prior art keywords
- display panel
- thin film
- drain
- film transistor
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
A display device (10) comprises a display panel (100), a first metal wire (200), wherein the first metal wire (200) comprises a first end (210) and a second end (220), and the first end (210) of the first metal wire (200) is connected with the display panel (100); a control module (300) connected to the second end (220) of the first metal trace (200); the second metal wire (400), the second metal wire (400) includes a third end (410) and a fourth end (420), the third end (410) of the second metal wire (400) is connected with the control module (300), the fourth end (420) of the second metal wire (400) is used for receiving a first test signal, the control module (300) is used for controlling whether the first test signal is transmitted to the display panel (100) through the first metal wire (200), and when the control module (300) controls the first test signal to be transmitted to the display panel (100) through the first metal wire (200), the display panel (100) is tested. An electronic device, an array test structure and an array test method are provided. The display device (10) can prevent the display panel (100) from line corrosion and electrostatic attack.
Description
The invention relates to the technical field of display, in particular to a display device, an electronic device, an array test structure and an array test method.
The existing liquid crystal display device needs to test the picture of the liquid crystal display panel in the box forming process, after the picture test is finished, a laser cutting machine is needed to cut off the test signal point and the metal connecting wire of the liquid crystal display panel, and then the test signal point and the metal connecting wire are provided for the subsequent process or the non-array test for use. After the panel is cut, a plurality of metal sections can appear on the cutting edge, the exposed metals are directly connected with the welding pad of the chip on film and are the same layer of metal, the problems of welding pad corrosion, static electricity release and the like are easily caused, and the stability of the panel is reduced.
Disclosure of Invention
In view of the above, the present invention provides a display device for solving the above technical problems, and the specific technical solution is as follows:
a display device, the display device comprising:
a display panel;
the first metal routing comprises a first end and a second end, and the first end of the first metal routing is connected with the display panel;
the control module is connected with the second end of the first metal wire;
the second metal routing comprises a third end and a fourth end, the third end of the second metal routing is connected with the control module, the fourth end of the second metal routing is used for receiving a first test signal, the control module is used for controlling whether the first test signal is transmitted to the display panel through the first metal routing, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing, the display panel is tested.
Preferably, the display panel includes a plurality of data lines or scan lines, and the first end of the first metal trace is connected to the data lines or scan lines in the display panel.
Preferably, the control module includes a plurality of electronic control switches, and the electronic control switches are first thin film transistors.
Preferably, the first thin film transistor includes a source electrode, the third end of the second metal trace is connected to the source electrode in the first thin film transistor, and the first test signal is transmitted to the source electrode of the first thin film transistor through the second metal trace.
Preferably, the first thin film transistor further includes a drain, and the drain in the first thin film transistor is connected to the second end of the first metal trace.
Preferably, the first thin film transistor further comprises an active region through which the source and the drain are spaced.
Preferably, the first thin film transistor further includes a gate, the gate receives a control signal and controls the conduction and the cut-off between the source and the drain under the control of the control signal, and when the source and the drain are conducted under the control of the control signal, the first test signal is transmitted to the active region through the source of the first thin film transistor and reaches the drain, and is transmitted to the display panel through a first metal trace electrically connected to the drain.
Preferably, the structure type of the first thin film transistor includes a back channel etching type structure first thin film transistor, a conventional etching blocking structure first thin film transistor, or a coplanar etching structure first thin film transistor.
Preferably, the display device further includes:
the welding pad is electrically connected with the first metal wire;
the chip on film is arranged on the welding pads and used for providing second test signals, and the second test signals are transmitted to the display panel through the welding pads and first metal wires electrically connected with the welding pads so as to test the display panel.
The invention also provides an electronic device comprising the display device of any one of the above.
The present invention also provides an array test structure, comprising:
an array test module for providing a first test signal;
the second metal wire comprises a third end and a fourth end, and the fourth end of the second metal wire is connected with the array test module to receive the first test signal;
the third end of the second metal wire is connected with the control module;
the first metal routing comprises a first end and a second end, the second end of the first metal routing is connected with the control module, the first end of the first metal routing is connected with the display panel, the control module is used for controlling whether the first test signal is transmitted to the display panel through the first metal routing or not, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing, the display panel is tested.
Preferably, the control module includes a plurality of electronic control switches, and the electronic control switches are first thin film transistors.
Preferably, the first thin film transistor includes a source, a drain and an active region, a third end of the second metal trace is connected to the source in the first thin film transistor, the drain in the first thin film transistor is connected to a second end of the first metal trace, and the source and the drain are spaced by the active region.
Preferably, the first thin film transistor further includes a gate, the gate receives a control signal and controls the conduction and the cut-off between the source and the drain under the control of the control signal, and when the source and the drain are conducted under the control of the control signal, the first test signal is transmitted to the active region through the source of the first thin film transistor and reaches the drain, and is transmitted to the display panel through a first metal trace electrically connected to the drain.
Preferably, the array test module includes one or more stages of test signal circuits, each test signal circuit includes a second thin film transistor, and a fourth end of the second metal trace is connected to the second thin film transistor to connect to the array test module.
The invention also provides an array test method of the display panel, which comprises the following steps:
the array test module provides a first test signal and transmits the first test signal to the control module through the second metal wire;
the control module controls whether the first test signal is transmitted to the display panel through a first metal routing or not, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing, the display panel is tested.
Preferably, the control module includes a first thin film transistor, the first thin film transistor includes a source, a drain, a gate and an active region, the gate receives a control signal and controls on and off between the source and the drain under the control of the control signal, and when the source and the drain are on under the control of the control signal, the first test signal is transmitted to the active region through the source of the first thin film transistor and reaches the drain, and is transmitted to the display panel through a first metal wire electrically connected to the drain.
Preferably, when the source and the drain are turned off under the control of the control signal, the first test signal cannot be transmitted to the active region through the source of the first thin film transistor and reach the drain, so that the first test signal is blocked from being transmitted to the display panel through a first metal wire electrically connected to the drain.
Preferably, the first metal wire is electrically connected to a chip on film, the chip on film is configured to provide a second test signal, and the second test signal is transmitted to the display panel through the chip on film and the first metal wire electrically connected to the chip on film, so as to test the display panel.
The invention has the beneficial effects that: after the display panel in the display device is cut, if the metal exposed at the cutting edge is corroded, the corrosion can be carried out towards the interior of the panel along the metal along with the time, and when the corrosion is carried out to the control module, the metal is separated by the control module, so that the corrosion of circuits in the display panel is effectively avoided. Meanwhile, the control module increases the resistance of the lead, and when static enters from the exposed metal, the control module plays a role in protecting the internal circuit of the panel and prevents the panel from being damaged by static shock.
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a process of cutting off a second metal trace in a display device according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram illustrating a connection between a control module and an array test module in a display device according to an embodiment of the present invention.
FIG. 4 is a schematic structural diagram of a first TFT with a back channel etching structure according to an embodiment of the present invention
FIG. 5 is a schematic structural diagram of a first thin-film-transistor layer of a conventional etching stop structure according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a display device including a chip on film and a bonding pad according to an embodiment of the invention.
Fig. 7 is a schematic view of an electronic device according to an embodiment of the invention.
Fig. 8 is a schematic diagram of an array test structure according to an embodiment of the present invention.
Fig. 9 is a flowchart of an array testing method of a display panel according to an embodiment of the present invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between different objects and not necessarily for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, an embodiment of the invention provides a display device 10, where the display device 10 includes a display panel 100, a first metal trace 200, a control module 300, and a second metal trace 400. The detailed functions of the various components are described below.
The first metal trace 200 includes a first end 210 and a second end 220, and the first end 210 of the first metal trace 220 is connected to the display panel 100. The first metal trace 200 is a metal wire for electrically connecting the display panel 100 and an external device or component, and the metal material and the number of the first metal trace 200 are not limited and can be selected as needed. The number of the first metal traces 200 shown by the dotted lines in fig. 1 can be set as required.
The control module 300 is connected to the second end 220 of the first metal trace 100. That is, the display panel 100 and the control module 300 are connected by the first metal trace 100.
The second metal trace 400 includes a third end 410 and a fourth end 420, the third end 410 of the second metal trace 400 is connected to the control module 300, and the fourth end 420 of the second metal trace 400 is used for receiving a first test signal. The control module 300 is configured to control whether the first test signal is transmitted to the display panel 100 through the first metal trace 200, and when the control module 300 controls the first test signal to be transmitted to the display panel 100 through the first metal trace 200, the control module tests the display panel 100. The first test signal is an array test signal, which is derived from the array test module 500 to check the display effect of the array substrate in the display panel 100.
It can be understood that the first test signal is transmitted to the second metal trace 400, then transmitted to the control module 300 through the second metal trace 400, then transmitted to the first metal trace 200 through the control module 300, and finally reaches the display panel 100 to test the display panel 100. The first test signal is from an array test module or other array test signal points, and after the first test signal tests the display panel, the second metal trace 400 is cut off from the cutting line 430 (see fig. 2) to cut off the connection between the first test signal and the display panel, and then the cut display panel is subjected to other tests. Since the second metal trace 400 is separated from the middle of the display panel 100 by the control module 300, the second metal trace 400 exposed outside due to cutting is not directly connected to the display panel 100, and when the second metal trace 400 exposed outside is corroded, the existence of the control module 300 prevents the corroded second metal trace 400 from corroding the circuit inside the display panel 100. In addition, the control module 300 is additionally arranged between the second metal trace 400 and the display panel 100, which is equivalent to increasing the resistance before the second metal trace 400 is connected to the display panel 100, and when static electricity enters from the exposed second metal trace 400, the control module 300 plays a role in protecting the internal circuit of the panel 100, so as to prevent the static electricity from being damaged.
In a further embodiment, the display panel 100 includes a plurality of data lines or scan lines, and the first end 210 of the first metal trace 200 is connected to the data lines or the scan lines in the display panel 100. When the signal test is performed on the display panel 100, the connection between the data lines and the scan lines can be tested more comprehensively, mainly for testing abnormal display points in the display panel 100.
Referring to fig. 3, in a further embodiment, the control module 300 includes a plurality of electronic control switches, and the electronic control switches are first thin film transistors 310. The number of the first thin film transistors 310 is the same as that of the first metal traces 200 or the second metal traces 400, and each first thin film transistor 310 controls transmission of a first test signal in one metal trace.
In a further embodiment, the first thin film transistor 310 includes a source 311, the third terminal 410 of the second metal trace 400 is connected to the source 311 of the first thin film transistor 310, and the first test signal is transmitted to the source 311 of the first thin film transistor 310 through the second metal trace 400.
In a further embodiment, the first thin film transistor 310 further includes a drain 312, and the drain 312 of the first thin film transistor 310 is connected to the second end 210 of the first metal trace 200.
In a further embodiment, the first thin film transistor 310 further includes an active region 313, and the source 311 and the drain 312 are spaced apart by the active region 313. In fig. 3, the active region 313 is not shown, and please refer to fig. 4 for a detailed structure diagram of the tft.
After the second metal trace 400 connected to the source 311 is cut, and the metal exposed in the external environment is corroded, the source 311 is directly connected to the corroded metal, and after the source 311 is corroded, since the source 311 and the drain 312 are separated by the active region 313, the active region 313 is not easily corroded, so that the drain 312 is prevented from being corroded, and the first metal trace 200 connected to the drain 312 is prevented from being corroded until the display panel 100. Moreover, since the first thin film transistor 310 itself has a resistance, when static electricity enters from the exposed second metal trace 400, the first thin film transistor 310 plays a role of protecting the internal circuit of the panel, so as to prevent the panel from being damaged by the static electricity.
In a further embodiment, the first thin film transistor 310 further includes a gate 314, the gate 314 receives a control signal S2, and controls the on/off between the source 311 and the drain 312 under the control of the control signal S2, when the source 311 and the drain 312 are turned on under the control of the control signal S2, the first test signal is transmitted to the active region 313 via the source 311 of the first thin film transistor 310, reaches the drain 312, and is transmitted to the display panel 100 via the first metal trace 200 electrically connected to the drain 312. It is to be understood that the control signal S2 is represented by a line in fig. 3, and does not represent that the line is a necessary component of the first thin film transistor 310.
In further embodiments, the structure type of the first thin film transistor 310 includes a back channel etching structure first thin film transistor, a conventional etching blocking structure first thin film transistor, or a coplanar etching structure first thin film transistor.
Referring to fig. 4, a first tft with a back channel etch type structure is used as an example to illustrate the innovative solution of the present invention.
The first thin film transistor 310 of the back channel etch type structure includes:
and the grid electrode 314 is arranged on the surface of the substrate 317.
A gate insulation layer 316, the gate insulation layer 316 covering the gate 314.
An active region 313, wherein the active region 313 is disposed on a surface of the gate insulating layer 316 away from the gate 314. Preferably, the active region 313 may be any one of an oxide semiconductor layer, a low temperature polysilicon layer, an amorphous silicon type layer, and the like, and the active region 313 is not easily corroded. The gate insulating layer 240 serves to electrically insulate the gate 314 from the active region 313.
And the source electrode 311 and the drain electrode 312 are arranged on the surface of the active region 313 far away from the gate insulation layer 316, and the source electrode 311 and the drain electrode 312 are arranged at intervals. As can be seen from fig. 4, the source 311 and the drain 312 are connected through the active region 313.
The source 311 is connected to the first end 410 of the second metal trace 400, and the drain 312 is connected to the second end 220 of the first metal trace 200.
When the first tft 310 with the back channel etching structure operates, the gate 314 receives a control signal S2, the source 311 and the drain 312 are turned on under the control of the control signal S2, and the first test signal is transmitted to the active region 313 through the source 311 of the first tft 310, reaches the drain 312, and is transmitted to the display panel 100 through the first metal trace 200 electrically connected to the drain 312. After the display panel 100 is detected, the second metal wire 400 is cut, and then the exposed metal is corroded in the external environment, and when the first end 410 of the second metal wire 400 corrodes the source 311, the active region 313 directly connected with the source 311 is not corroded easily due to the material characteristics, so that the corrosion tendency is blocked, the drain 312 connected with the active region 313 is protected, and further, the corrosion of the first metal wire 200 connected with the drain 312 is avoided until the display panel 100 is protected.
Referring to fig. 5, fig. 5 shows a structure of a first tft in a conventional etching stopper structure, which is described in detail below.
The conventional etch stop structure first thin-film-transistor layer 310 includes:
and the grid electrode 314 is arranged on the surface of the substrate 317.
A gate insulating layer 316, wherein the gate insulating layer 316 is disposed on the substrate 317 and a surface of the gate 314 away from the substrate 317.
An active region 313, wherein the active region 313 is disposed on a surface of the gate insulating layer 316 away from the gate 314.
An etch stop layer 318, the etch stop layer 318 being disposed on a surface of the active region 313 remote from the gate insulation layer 316. The etch stop layer 318 is used to protect the active region 313 from being corroded by an etching solution during the preparation of the source electrode 311 and the drain electrode 312 to affect the electrical performance of the active region 313. A first via 319 and a second via 3110 are opened on the etch stop layer 318, and the first via 319 and the second via 3110 are used for exposing a portion of the active region 313.
A source 311 and a drain 312, wherein the source 311 and the drain 312 are disposed on a surface of the etch stop layer 318 away from the active region 313, the source 311 is connected to the active region 313 through the first via 319, and the drain 312 is connected to the active region 313 through the second via 3110.
It is understood that the conventional etch stop structure first thin film transistor operates in a similar manner to the back channel etch type structure first thin film transistor. It is understood that the technical effects of the present invention can be achieved regardless of whether the top gate type thin film transistor or the bottom gate type thin film transistor, in which the source and the drain are separated by the active region.
Referring again to fig. 1, and referring to fig. 6, in a further embodiment, the display device 10 further includes:
a pad 600, wherein the pad 600 is electrically connected to the first metal trace 200. Preferably, the pad 600 is connected to the first metal trace 200 by soldering.
The chip on film 700, the chip on film 700 is disposed on the pad 200, the chip on film 700 is used to provide a second test signal, and the second test signal is transmitted to the display panel 100 through the pad 600 and the first metal trace 200 electrically connected to the pad 600, so as to test the display panel 100. The second test signal is a non-array test signal, and after the display device 10 receives the first test signal to test the display panel 100, the second metal trace 400 is cut off, and the second test signal is input to the flip-chip film 700 and transmitted to the display panel 100 for other tests.
Referring to fig. 7, an embodiment of the invention further provides an electronic device 20, which includes the display device 10 described in any one of the above embodiments.
The electronic device 20 may be, but not limited to, an electronic book, a smart Phone (e.g., an Android Phone, an iOS Phone, a Windows Phone), a tablet computer, a flexible palm computer, a flexible notebook computer, a Mobile Internet device (MID, Mobile Internet Devices), or a wearable device, or may be an Organic light-Emitting Diode (O L ED) display device, an Active Matrix Organic light-Emitting Diode (AMO L ED) electronic device.
Referring to fig. 8 and 3, the present invention further provides an array test structure, where the array test structure 30 includes:
an array test module 500, the array test module 500 for providing a first test signal.
Referring to fig. 3, the second metal trace 400 includes a third end 410 and a fourth end 420, and the fourth end 420 of the second metal trace 400 is connected to the array test module 500 to receive the first test signal.
And the third end 410 of the second metal trace 400 is connected to the control module 300.
The first metal trace 200, the first metal trace 200 includes a first end 210 and a second end 220, the second end 220 of the first metal trace 200 is connected to the control module 300, the first end 210 of the first metal trace 200 is used for connecting to the display panel 100, and the control module 300 is used for controlling whether the first test signal is transmitted to the display panel 100 through the first metal trace 200. The control module 300 controls the on/off of the control module 300 through a control signal S2, and when the control module 300 controls the first test signal to be transmitted to the display panel 100 through the first metal trace 200 through a control signal S2, the control module tests the display panel 100.
In a further embodiment, the control module 300 includes a plurality of electronically controlled switches, and the electronically controlled switches are first thin film transistors 310.
In a further embodiment, the first tft 310 includes a source 311, a drain 312 and an active region 313, the third end 410 of the second metal trace 400 is connected to the source 311 of the first tft 310, the drain 312 of the first tft 310 is connected to the second end 220 of the first metal trace 200, and the source 311 and the drain 312 are separated by the active region 313.
In a further embodiment, the first thin film transistor 310 further includes a gate 314, the gate 314 receives a control signal S2, and controls the on/off between the source 311 and the drain 312 under the control of the control signal S2, when the source 311 and the drain 312 are turned on under the control of the control signal S2, the first test signal is transmitted to the active region 313 via the source 311 of the first thin film transistor 310 and reaches the drain 312, and is transmitted to the display panel 100 via a first metal trace 200 electrically connected to the drain 312.
In a further embodiment, the array test module 500 includes one or more stages of test signal circuits 510, the test signal circuits 510 include second thin film transistors 520, and the fourth ends 420 of the second metal traces 400 are connected to the second thin film transistors 520 to connect the array test module 500.
It is understood that the test signal circuit 510 can be divided into one stage or multiple stages, where the one stage means that n test signals are directly input into the control module 300 through the second metal trace 400, where n is an integer. The multi-stage test method is characterized in that n test signals are divided into m-stage signals, each stage of signals can have a plurality of test signals, m is an integer and is smaller than n, and the material cost of a lead can be saved by adopting the multi-stage test signals.
Referring to fig. 8 again, taking 20 test signals as an example, the 20 test signals are divided into 2 levels, which are the first level signal and the second level signal respectively. And the number of the first-stage signals is set to 5, which are AT1, AT2, AT3, AT4 and AT5, respectively, then 20 test signals are respectively distributed to the 5 first-stage signals, each first-stage signal obtains 4 second-stage signals, which are AT6, AT7, AT8 and AT9, respectively, wherein after the first-stage signals AT1, AT2, AT3, AT4 and AT5 obtain the first test signal S1, whether the first-stage signals are transmitted to the area of the second-stage signals under the control of the first-stage signals or not.
Taking the first-stage signal AT2 as an example, after the first-stage signal AT2 obtains the first test signal S1, the first-stage signal AT2 is transmitted to the second tft 520a of the first stage and turned on, the first test signal S1 is transmitted to the second tft 520b of the second stage through the second tft 520a of the first stage, and then whether the second tft 520b of the second stage is turned on is controlled under the control of the second-stage signals AT6, AT7, AT8, or AT 9. When the second tft 520b of the second level is turned on, the first test signal S1 is transmitted through the second tft 520b of the second level to the second metal trace 400 and transmitted to the control module 300 through the second metal trace 400, and the control module 300 controls whether the control module 300 is turned on or off under the control of the control signal S2. When the control module 300 is turned on, the first test signal is transmitted to the first metal trace 200 and finally reaches the display panel 100, so as to test the display panel 100.
It is understood that the test signal circuit 510 of the array test module 500 may have one or more stages as desired.
Referring to fig. 9, an embodiment of the present invention further provides a method for testing an array of a display panel, where the method for testing an array of a display panel includes steps S100 and S200. The detailed procedure is described below.
In step S100, the array test module 500 provides a first test signal and transmits the first test signal to the control module 300 through the second metal trace 400.
Step S200, the control module 300 controls whether the first test signal is transmitted to the display panel 100 through the first metal trace 200, and when the control module 300 controls the first test signal to be transmitted to the display panel 100 through the first metal trace 200, the display panel 100 is tested.
In a further embodiment, in the step S200, the control module 300 includes a first thin film transistor 310, the first thin film transistor 310 includes a source 311, a drain 312, a gate 314 and an active region 313, the gate 314 receives a control signal S2 and controls on and off between the source 311 and the drain 312 under the control of the control signal S2, and when the source 311 and the drain 312 are turned on under the control of the control signal S2, the first test signal is transmitted to the active region 313 via the source 311 of the first thin film transistor 310 and reaches the drain 312, and is transmitted to the display panel 100 via a first metal trace 200 electrically connected to the drain 312.
In a further embodiment, when the source 311 and the drain 312 are turned off under the control of the control signal S2, the first test signal cannot be transmitted to the active region 313 through the source 311 of the first thin film transistor 310 and reaches the drain 312, so that the first test signal is blocked from being transmitted to the display panel 100 through the first metal trace 200 electrically connected to the drain 312.
In a further embodiment, the first metal traces 310 are electrically connected to a chip on film 700, the chip on film 700 is used for providing a second test signal, and the second test signal is transmitted to the display panel 100 through the chip on film 700 and the first metal traces 200 electrically connected to the chip on film 700 to test the display panel 100.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (19)
- A display device, characterized in that the display device comprises:a display panel;the first metal routing comprises a first end and a second end, and the first end of the first metal routing is connected with the display panel;the control module is connected with the second end of the first metal wire;the second metal routing wire comprises a third end and a fourth end, the third end of the second metal routing wire is connected with the control module, the fourth end of the second metal routing wire is used for receiving a first test signal, the control module is used for controlling whether the first test signal is transmitted to the display panel through the first metal routing wire or not, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing wire, the display panel is tested.
- The display device according to claim 1, wherein the display panel includes a plurality of data lines or scan lines, and the first end of the first metal trace is connected to the data lines or the scan lines in the display panel.
- The display device according to claim 1, wherein the control module includes a plurality of electronically controlled switches therein, the electronically controlled switches being first thin film transistors.
- The display device according to claim 3, wherein the first thin film transistor comprises a source electrode, the third end of the second metal wire is connected to the source electrode of the first thin film transistor, and the first test signal is transmitted to the source electrode of the first thin film transistor through the second metal wire.
- The display device according to claim 4, wherein the first thin film transistor further comprises a drain, and the drain in the first thin film transistor is connected to the second end of the first metal trace.
- The display device of claim 5, wherein the first thin film transistor further comprises an active region through which the source and the drain are spaced.
- The display device according to claim 5, wherein the first thin film transistor further comprises a gate, the gate receives a control signal and controls on and off between the source and the drain under the control of the control signal, and when the source and the drain are turned on under the control of the control signal, the first test signal is transmitted to the active region through the source of the first thin film transistor and reaches the drain, and is transmitted to the display panel through a first metal wire electrically connected to the drain.
- The display device according to claim 3, wherein the first thin film transistor has a structure type including a back channel etch type structure first thin film transistor, a conventional etch stop structure first thin film transistor, or a coplanar etch structure first thin film transistor.
- The display device of claim 1, wherein the display device further comprises:the welding pad is electrically connected with the first metal wire;the chip on film is arranged on the welding pads and used for providing second test signals, and the second test signals are transmitted to the display panel through the welding pads and first metal wires electrically connected with the welding pads so as to test the display panel.
- An electronic device characterized in that the electronic device comprises the display device according to any one of claims 1 to 9.
- An array test structure, comprising:an array test module for providing a first test signal;the second metal wire comprises a third end and a fourth end, and the fourth end of the second metal wire is connected with the array test module to receive the first test signal;the third end of the second metal wire is connected with the control module;the first metal routing comprises a first end and a second end, the second end of the first metal routing is connected with the control module, the first end of the first metal routing is connected with the display panel, the control module is used for controlling whether the first test signal is transmitted to the display panel through the first metal routing or not, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing, the display panel is tested.
- The array test structure of claim 11, wherein the control module includes a plurality of electronically controlled switches therein, the electronically controlled switches being first thin film transistors.
- The array test structure of claim 12, wherein the first thin film transistor comprises a source, a drain, and an active region, a third end of the second metal trace connects to the source in the first thin film transistor, the drain in the first thin film transistor connects to a second end of the first metal trace, the source and the drain are spaced apart by the active region.
- The array test structure of claim 13, wherein the first thin film transistor further comprises a gate, the gate receives a control signal and controls on and off between the source and the drain under the control of the control signal, and when the source and the drain are turned on under the control of the control signal, the first test signal is transmitted to the active region and to the drain through the source of the first thin film transistor and to the display panel through a first metal trace electrically connected to the drain.
- The array test structure of claim 11, wherein the array test module comprises one or more stages of test signal circuits, the test signal circuits comprise second thin film transistors, and the fourth ends of the second metal traces are connected to the second thin film transistors for connecting to the array test module.
- The array test method of the display panel is characterized by comprising the following steps:the array test module provides a first test signal and transmits the first test signal to the control module through the second metal wire;the control module controls whether the first test signal is transmitted to the display panel through a first metal routing or not, and when the control module controls the first test signal to be transmitted to the display panel through the first metal routing, the display panel is tested.
- The array test method of the display panel according to claim 16, wherein the control module comprises a first thin film transistor, the first thin film transistor comprises a source electrode, a drain electrode, a gate electrode and an active region, the gate electrode receives a control signal and controls the on and off between the source electrode and the drain electrode under the control of the control signal, and when the source electrode and the drain electrode are turned on under the control of the control signal, the first test signal is transmitted to the active region through the source electrode of the first thin film transistor, reaches the drain electrode, and is transmitted to the display panel through a first metal wire electrically connected to the drain electrode.
- The array test method of the display panel according to claim 17, wherein when the source and the drain are turned off under the control of the control signal, the first test signal cannot be transmitted to the active region through the source of the first thin film transistor and reaches the drain, thereby blocking the first test signal from being transmitted to the display panel through a first metal wire electrically connected to the drain.
- The array testing method of the display panel according to claim 18, wherein the first metal traces are electrically connected to a chip on film, the chip on film is used for providing a second test signal, and the second test signal is transmitted to the display panel through the chip on film and the first metal traces electrically connected to the chip on film for testing the display panel.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2017/118735 WO2019127042A1 (en) | 2017-12-26 | 2017-12-26 | Display apparatus, electronic apparatus, array test structure and array test method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111433666A true CN111433666A (en) | 2020-07-17 |
Family
ID=67064241
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780097385.XA Pending CN111433666A (en) | 2017-12-26 | 2017-12-26 | Display device, electronic device, array test structure and array test method |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN111433666A (en) |
WO (1) | WO2019127042A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113889012A (en) * | 2021-11-17 | 2022-01-04 | 维信诺科技股份有限公司 | Display panel and display device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
US20020105615A1 (en) * | 2001-02-08 | 2002-08-08 | Koninklijke Philips Electronics N.V. | Display device |
US20080106835A1 (en) * | 2006-11-08 | 2008-05-08 | Chunghwa Picture Tubes, Ltd. | Active device array substrate having electrostatic discharge protection capability |
CN102789072A (en) * | 2011-05-18 | 2012-11-21 | 友达光电股份有限公司 | Three-dimensional display switchover panel and static electricity protecting method thereof |
CN105070239A (en) * | 2015-08-27 | 2015-11-18 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
CN205787501U (en) * | 2016-07-01 | 2016-12-07 | 上海天马微电子有限公司 | Liquid crystal display panel and display device |
-
2017
- 2017-12-26 WO PCT/CN2017/118735 patent/WO2019127042A1/en active Application Filing
- 2017-12-26 CN CN201780097385.XA patent/CN111433666A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1194039A (en) * | 1995-08-07 | 1998-09-23 | 株式会社日立制作所 | Active matrix type liquid crystl display device resistant to static electricity |
US20020105615A1 (en) * | 2001-02-08 | 2002-08-08 | Koninklijke Philips Electronics N.V. | Display device |
US20080106835A1 (en) * | 2006-11-08 | 2008-05-08 | Chunghwa Picture Tubes, Ltd. | Active device array substrate having electrostatic discharge protection capability |
CN102789072A (en) * | 2011-05-18 | 2012-11-21 | 友达光电股份有限公司 | Three-dimensional display switchover panel and static electricity protecting method thereof |
CN105070239A (en) * | 2015-08-27 | 2015-11-18 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
CN205787501U (en) * | 2016-07-01 | 2016-12-07 | 上海天马微电子有限公司 | Liquid crystal display panel and display device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113889012A (en) * | 2021-11-17 | 2022-01-04 | 维信诺科技股份有限公司 | Display panel and display device |
Also Published As
Publication number | Publication date |
---|---|
WO2019127042A1 (en) | 2019-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107331294B (en) | Display panel and display device | |
US10559766B2 (en) | Flexible display screen and flexible display device | |
CN110289225B (en) | Testing device and method and display device | |
CN111919164B (en) | Display panel with narrow lower frame and electronic equipment | |
US20210257267A1 (en) | Display panel and method for manufacturing same | |
CN106847774B (en) | Display panel and preparation method thereof | |
EP2770532B1 (en) | Array substrate and panel | |
US8860197B2 (en) | Integrated circuits secure from invasion and methods of manufacturing the same | |
US9570365B2 (en) | Display device and test pad thereof | |
CN105845701A (en) | Flexible display device and making method thereof | |
KR20150038842A (en) | Driver integrated circuit chip, display device having the same, and method of manufacturing a driver integrated circuit chip | |
CN103928444A (en) | TFT array substrate, display panel and display device | |
CN111433666A (en) | Display device, electronic device, array test structure and array test method | |
US10818699B2 (en) | Display panel and display device | |
US9263576B2 (en) | Semiconductor device having interconnection line | |
US20160276368A1 (en) | Thin-Film Transistor Array Substrate And Method For Manufacturing Thin-Film Transistor Array Substrate | |
KR102172786B1 (en) | Semiconductor package and method for fabricating the same | |
JP2006351664A (en) | Semiconductor device | |
CN111857435B (en) | Touch display panel, testing method thereof and display device | |
CN109671725B (en) | Display panel and display device | |
CN108319085B (en) | Array substrate, display panel and preparation method thereof | |
US11700696B2 (en) | Buried electrical debug access port | |
JP2006301135A (en) | Liquid crystal display element and flexible printed wiring board | |
US9490187B2 (en) | Semiconductor package on which semiconductor chip is mounted on substrate with window | |
US8748226B2 (en) | Method for fixing semiconductor chip on circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200717 |
|
WD01 | Invention patent application deemed withdrawn after publication |