CN111430508A - Semiconductor device metallization method and solar cell preparation method - Google Patents

Semiconductor device metallization method and solar cell preparation method Download PDF

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Publication number
CN111430508A
CN111430508A CN202010188231.5A CN202010188231A CN111430508A CN 111430508 A CN111430508 A CN 111430508A CN 202010188231 A CN202010188231 A CN 202010188231A CN 111430508 A CN111430508 A CN 111430508A
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layer
electroplating
substrate
insulating layer
etching
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梁建军
舒欣
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Changzhou Jiejiachuang Precision Machinery Co Ltd
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Changzhou Jiejiachuang Precision Machinery Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides a semiconductor device metallization method and a solar cell preparation method, wherein the semiconductor device metallization method comprises the following steps: depositing insulating layers on two sides of the substrate; arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer; etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening; arranging conductive slurry at the electroplating opening to form an electroplating seed layer; a metallization structure is formed on the plating seed layer. According to the semiconductor device metallization method provided by the invention, through the formation of the insulating layer, the insulating layer is etched based on the etching pattern to form the electroplating opening, so that the metallization structure is formed in the electroplating opening, the height-width ratio of the metallization structure is convenient to control, meanwhile, the metallization structure can be prevented from collapsing, the quality of the metallization structure is improved, and the performance of the semiconductor device is further improved.

Description

Semiconductor device metallization method and solar cell preparation method
Technical Field
The invention relates to the field of semiconductor device processing, in particular to a semiconductor device metallization method and a solar cell preparation method.
Background
The screen printing high-temperature silver paste is the conventional method for metalizing the existing crystalline silicon solar cell, but the problems of irregular printing line type collapse, lower height-to-width ratio of grid lines and the like exist, and the improvement of the solar cell efficiency is seriously restricted.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art.
To this end, the invention provides, in a first aspect, a method for metallizing a semiconductor device.
The invention provides a solar cell preparation method in a second aspect.
In view of the above, according to a first aspect of the present invention, a method for metalizing a semiconductor device is provided, including: depositing insulating layers on two sides of the substrate; arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer; etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening; arranging conductive slurry at the electroplating opening to form an electroplating seed layer; a metallization structure is formed on the plating seed layer.
The semiconductor device metallization method provided by the invention is used for forming a metallization structure on a semiconductor device, and in the working process, insulating layers are deposited on two sides of a base layer to be used as electroplating protective layers; arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer; etching the insulating layer based on the etching pattern until the substrate is exposed, forming an electroplating opening, and etching a grid line pattern; arranging conductive slurry at the electroplating opening to form an electroplating seed layer; and finally, forming a metallization structure on the electroplating seed layer. According to the semiconductor device metallization method provided by the invention, through the formation of the insulating layer, the insulating layer is further etched based on the etching pattern to form the electroplating opening, so that the metallization structure is formed in the electroplating opening, the height-width ratio of the metallization structure is convenient to control, meanwhile, the collapse of the metallization structure can be prevented, the quality of the metallization structure is improved, and the performance of the semiconductor device is further improved.
Specifically, the width of the metallization structure can be controlled by adjusting the etching pattern on the mask layer, the height of the metallization structure can be adjusted by adjusting the deposition thickness of the insulating layer and controlling the etching depth of the insulating layer, the aspect ratio of the metallization structure can be controlled, the quality of the metallization structure is improved, and the performance of the semiconductor device is improved.
Specifically, the metallization structure is formed in the electroplating opening and is limited by the electroplating opening in the process of forming the metallization structure, so that the metallization structure cannot collapse, the quality of the metallization structure can be improved, and the performance of a semiconductor device is improved.
In addition, according to the metallization method of the semiconductor device in the above embodiment provided by the present invention, the following additional technical features may also be provided:
in the above technical solution, further, the specific step of depositing the insulating layer on both sides of the substrate includes: and depositing insulating layers with the thickness of 10nm to 2000nm on the two sides of the substrate.
In the technical scheme, the deposition thickness of the insulating layer is further provided, and the insulating layer with the thickness of 10nm to 2000nm is deposited on the two sides of the base material. Can ensure that metallization structure forms in electroplating the opening, effectively avoid metallization structure to take place to sink, can ensure metallization structure's quality.
In any of the above technical solutions, further, the specific step of depositing the insulating layer on both sides of the substrate includes: and depositing at least one of silicon oxide, magnesium fluoride and aluminum oxide on the two sides of the base to form an insulating layer.
In the technical scheme, the material of the insulating layer is further provided, and the base material is not damaged in the process of forming the metallization structure by selecting at least one of silicon oxide, magnesium fluoride and aluminum oxide, so that the quality of the semiconductor device is further guaranteed.
In any of the above technical solutions, further, the step of etching the insulating layer to expose the substrate to form the plating opening includes: photoetching a part of the insulating layer to expose the substrate through a laser machine to form an electroplating opening; or forming the plated opening by plasma etching a portion of the insulating layer to expose the substrate.
In the technical scheme, the specific steps of electroplating the opening are further provided, and through laser machine photoetching, the high flexibility of one-time forming of different patterns at different angles can be realized, and the high etching yield and the good stability are realized. Etching a part of the insulating layer by plasma can ensure etching fidelity.
Specifically, when the insulating layer is photoetched by a laser machine, picosecond laser can be adopted to reduce laser damage, and other lasers or technologies can also be adopted; the width of the plated opening is typically between 2 microns and 100 microns, and can be adjusted according to the purpose of the process.
In any of the above technical solutions, further, the step of disposing a conductive paste at the plating opening to form a plating seed layer includes: printing conductive paste at the electroplating opening through a screen printer; and drying or sintering the conductive slurry to form a plating seed layer.
In the technical scheme, the specific step of forming the electroplating seed layer is further provided, the conductive slurry is printed at the electroplating opening through a screen printer, the equipment investment cost is low, the conductive slurry is dried or sintered to form the electroplating seed layer, and the subsequent metallization structure is conveniently formed on the electroplating seed layer.
In any of the above technical solutions, further, the step of forming the metallization structure on the plating seed layer includes: and depositing a copper electroplating layer and/or a tin electroplating layer on the electroplating seed layer through an electroplating process to form the metallization structure.
In the technical scheme, the specific step of forming the metallization structure on the electroplating seed layer is further provided, and the copper electroplating layer and/or the tin electroplating layer are/is deposited on the electroplating seed layer through the electroplating process, so that the production cost of the metallization structure is reduced while the excellent quality of the metallization structure is ensured.
In any of the above technical solutions, further, the method for metalizing a semiconductor device further includes: etching the mask layer; and forming a double antireflection layer structure by the part of the insulating layer which is not etched and the substrate.
In the technical scheme, the non-etched insulating layer can be reserved, the insulating layer and the base material form a double-antireflection layer structure, and the performance of the solar cell can be improved through the formation of the double-antireflection layer structure in the field of solar cell preparation.
In any of the above technical solutions, further, the method for metalizing a semiconductor device further includes: etching the mask layer; and etching to remove the insulating layer.
In the technical scheme, the insulating layer can be etched and removed after the metallization structure is formed. The insulating layer may specifically be removed by HF dip or dry etching, for example by etching by techniques such as ion etching.
According to a second aspect of the present invention, there is provided a solar cell manufacturing method, comprising:
processing the crystalline silicon substrate through a texturing process;
preparing amorphous silicon layers on two sides of the crystalline silicon substrate;
preparing a transparent conductive layer on the amorphous silicon layer to form a substrate;
and forming a metallization structure on the substrate by using the semiconductor device metallization method of any one of the technical schemes.
According to the solar cell preparation method provided by the invention, the metallization structure is formed on the base material by the semiconductor device metallization method of any technical scheme, and in the solar cell preparation process, large-scale mass production equipment in the solar industry production can be selected, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), laser, screen printing and other technologies, to form the metallization structure, so that the solar cell preparation cost is greatly reduced.
Specifically, after the metallization structure is formed, the insulating layer deposited on the substrate can be retained, and the insulating layer and the substrate form a double-antireflection-layer structure, so that the performance of the solar cell can be improved, and the use of materials required by the transparent conducting layer can be reduced.
Specifically, the material of the Transparent conductive layer is Transparent Conductive Oxide (TCO).
In the above technical solution, further, the solar cell manufacturing method includes: preparing a suede with the side length of 1um to 10um on a crystalline silicon substrate with the resistivity of 0.1 to 5ohm cm through a texturing process; preparing amorphous silicon layers with the thickness of 1nm to 30nm on the two sides of the crystalline silicon substrate; a transparent conductive layer having a thickness of 50nm to 150nm and a refractive index of 1 to 3 is prepared on the amorphous silicon layer.
In the technical scheme, parameters of the crystalline silicon substrate, the size of the textured surface, the thickness of the amorphous silicon layer, the thickness of the transparent conductive layer and the refractive index are further provided, and the performance of the solar cell can be further guaranteed. Further, in the process of forming the metallization structure, the refractive index of the deposited insulating layer is 1 to 3 so as to be adapted to the transparent conductive layer, and a double antireflection layer structure can be formed with the transparent conductive layer.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flow chart of a metallization method of a semiconductor device according to a first embodiment of the invention;
fig. 2 is a schematic flow chart of a metallization method of a semiconductor device according to a second embodiment of the invention;
fig. 3 is a schematic flow chart of a metallization method of a semiconductor device according to a third embodiment of the invention;
fig. 4 shows a schematic flow chart of a metallization method of a semiconductor device according to a fourth embodiment of the invention;
fig. 5 is a schematic flow chart illustrating a metallization method of a semiconductor device according to an embodiment of the invention;
fig. 6 shows a schematic flow chart of a metallization method of a semiconductor device according to a sixth embodiment of the invention;
fig. 7 shows a schematic flow chart of a metallization method of a semiconductor device according to a seventh embodiment of the invention;
fig. 8 shows a schematic flow chart of a metallization method of a semiconductor device according to an eighth embodiment of the invention;
FIG. 9 shows a schematic flow diagram of a method of fabricating a solar cell according to an embodiment of the invention;
fig. 10 shows a schematic flow diagram of a solar cell fabrication method according to another embodiment of the invention;
FIG. 11 shows a schematic flow diagram of a method of fabricating a solar cell according to an embodiment of the invention;
FIG. 12 shows a schematic structural view of a substrate according to one embodiment of the present invention;
FIG. 13 shows a schematic view of a substrate after deposition of an insulating layer according to one embodiment of the invention;
FIG. 14 shows a schematic structural view of a plated opening according to one embodiment of the invention;
FIG. 15 shows a schematic structural view of a plating seed layer according to an embodiment of the invention;
FIG. 16 shows a schematic structural diagram of a metallization structure according to one embodiment of the invention;
FIG. 17 is a schematic diagram of a solar cell structure in a state where an insulating layer is removed by etching according to an embodiment of the invention;
wherein, the correspondence between the reference numbers and the part names in fig. 12 to 17 is:
2 substrate, 4 insulating layer, 6 plating opening, 8 plating seed layer, 10 metallization structure, 202 crystalline silicon substrate, 204 amorphous silicon layer, 206 transparent conductive layer.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings, which are illustrated in the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as specifically described herein, and thus the scope of the present invention is not limited by the specific embodiments disclosed below.
Methods of metallization of semiconductor devices and methods of solar cell fabrication provided according to some embodiments of the present invention are described below with reference to fig. 1-17.
Example one
As shown in fig. 1, one embodiment of the present invention provides a method for metalizing a semiconductor device, comprising:
step 102: depositing insulating layers on two sides of the substrate;
step 104: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 106: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 108: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 110: a metallization structure is formed on the plating seed layer.
The semiconductor device metallization method provided by the invention is used for forming a metallization structure on a semiconductor device, and insulating layers are deposited on two sides of a base layer in the working process to be used as electroplating protective layers; arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer; etching the insulating layer based on the etching pattern until the substrate is exposed, forming an electroplating opening, and etching a grid line pattern; arranging conductive slurry at the electroplating opening to form an electroplating seed layer; and finally, forming a metallization structure on the electroplating seed layer. According to the semiconductor device metallization method provided by the invention, through the formation of the insulating layer, the insulating layer is further etched based on the etching pattern to form the electroplating opening, so that the metallization structure is formed in the electroplating opening, the height-width ratio of the metallization structure is convenient to control, meanwhile, the collapse of the metallization structure can be prevented, the quality of the metallization structure is improved, and the performance of the semiconductor device is further improved.
Specifically, the width of the metallization structure can be controlled by adjusting the etching pattern on the mask layer, the height of the metallization structure can be adjusted by adjusting the deposition thickness of the insulating layer and controlling the etching depth of the insulating layer, the aspect ratio of the metallization structure can be controlled, the quality of the metallization structure is improved, and the performance of the semiconductor device is improved.
Specifically, the metallization structure is formed in the electroplating opening and is limited by the electroplating opening in the process of forming the metallization structure, so that the metallization structure cannot collapse, the quality of the metallization structure can be improved, and the performance of a semiconductor device is improved.
Example two
As shown in fig. 2, an embodiment of the present invention provides a method for metalizing a semiconductor device, including:
step 202: depositing insulating layers with the thickness of 10nm to 2000nm on the two sides of the substrate;
step 204: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 206: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 208: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 210: a metallization structure is formed on the plating seed layer.
In the technical scheme, the deposition thickness of the insulating layer is further provided, and the insulating layer with the thickness of 10nm to 2000nm is deposited on the two sides of the base material. Can ensure that metallization structure forms in electroplating the opening, effectively avoid metallization structure to take place to sink, can ensure metallization structure's quality.
EXAMPLE III
As shown in fig. 3, an embodiment of the present invention provides a method for metalizing a semiconductor device, including:
step 302: depositing at least one of silicon oxide, magnesium fluoride and aluminum oxide on the two sides of the base to form an insulating layer;
step 304: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 306: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 308: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 310: a metallization structure is formed on the plating seed layer.
In the technical scheme, the material of the insulating layer is further provided, and the base material is not damaged in the process of forming the metallization structure by selecting at least one of silicon oxide, magnesium fluoride and aluminum oxide, so that the quality of the semiconductor device is further guaranteed.
Example four
As shown in fig. 4, an embodiment of the present invention provides a control method of a food processing apparatus, a semiconductor device metallization method, including:
step 402: depositing insulating layers on two sides of the substrate;
step 404: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 406: photoetching a part of the insulating layer to expose the substrate through a laser machine to form an electroplating opening;
step 408: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 410: a metallization structure is formed on the plating seed layer.
In the technical scheme, the specific steps of electroplating the opening are further provided, and through laser machine photoetching, the high flexibility of one-time forming of different patterns at different angles can be realized, and the high etching yield and the good stability are realized.
EXAMPLE five
As shown in fig. 5, an embodiment of the present invention provides a method for metalizing a semiconductor device, including:
step 502: depositing insulating layers on two sides of the substrate;
step 504: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 506: forming a plating opening by plasma etching a portion of the insulating layer to expose the substrate;
step 508: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 510: a metallization structure is formed on the plating seed layer.
In the technical scheme, the etching fidelity can be ensured by etching part of the insulating layer through plasma.
EXAMPLE six
As shown in fig. 6, an embodiment of the present invention provides a method for metalizing a semiconductor device, including:
step 602: depositing insulating layers on two sides of the substrate;
step 604: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 606: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 608: printing conductive paste at the electroplating opening through a screen printer; drying or sintering the conductive slurry to form a plating seed layer;
step 610: and depositing a copper electroplating layer and/or a tin electroplating layer on the electroplating seed layer through an electroplating process to form the metallization structure.
In the technical scheme, the specific step of forming the electroplating seed layer is further provided, the conductive slurry is printed at the electroplating opening through a screen printer, the equipment investment cost is low, the conductive slurry is dried or sintered to form the electroplating seed layer, and the subsequent metallization structure is conveniently formed on the electroplating seed layer.
In the technical scheme, the specific step of forming the metallization structure on the electroplating seed layer is further provided, and the copper electroplating layer and/or the tin electroplating layer are/is deposited on the electroplating seed layer through the electroplating process, so that the production cost of the metallization structure is reduced while the excellent quality of the metallization structure is ensured.
EXAMPLE seven
As shown in fig. 7, one embodiment of the present invention provides a method including:
step 702: depositing insulating layers on two sides of the substrate;
step 704: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 706: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 708: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 710: forming a metallization structure on the plating seed layer;
step 712: etching the mask layer;
step 714: and forming a double antireflection layer structure by the part of the insulating layer which is not etched and the substrate.
In the technical scheme, the non-etched insulating layer can be reserved, the insulating layer and the base material form a double-antireflection layer structure, and the performance of the solar cell can be improved through the formation of the double-antireflection layer structure in the field of solar cell preparation.
Example eight
As shown in fig. 1, one embodiment of the present invention provides a method for metalizing a semiconductor device, comprising:
step 802: depositing insulating layers on two sides of the substrate;
step 804: arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
step 806: etching the insulating layer to expose the substrate based on the etching pattern to form an electroplating opening;
step 808: arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
step 810: a metallization structure is formed on the plating seed layer.
Step 812: etching the mask layer;
step 814: and etching to remove the insulating layer.
In the technical scheme, the insulating layer can be etched and removed after the metallization structure is formed. The insulating layer may specifically be removed by HF dip or dry etching, for example by etching by techniques such as ion etching.
Example nine
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a solar cell, including:
step 902: processing the crystalline silicon substrate through a texturing process;
step 904: preparing amorphous silicon layers on two sides of the crystalline silicon substrate;
step 906: preparing a transparent conductive layer on the amorphous silicon layer to form a substrate;
step 908: and forming a metallization structure on the substrate by using the semiconductor device metallization method of any one of the technical schemes.
According to the solar cell preparation method provided by the invention, the metallization structure is formed on the base material by the semiconductor device metallization method of any technical scheme, and in the solar cell preparation process, large-scale mass production equipment in the solar industry production can be selected, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), laser, screen printing and other technologies, to form the metallization structure, so that the solar cell preparation cost is greatly reduced.
Specifically, after the metallization structure is formed, the insulating layer deposited on the substrate can be retained, and the insulating layer and the substrate form a double-antireflection-layer structure, so that the performance of the solar cell can be improved, and the use of materials required by the transparent conducting layer can be reduced.
Specifically, the material of the Transparent conductive layer is Transparent Conductive Oxide (TCO).
Example ten
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a solar cell, including:
step 1002: preparing a suede with the side length of 1um to 10um on a crystalline silicon substrate with the resistivity of 0.1 to 5ohm cm through a texturing process;
step 1004: preparing amorphous silicon layers with the thickness of 1nm to 30nm on the two sides of the crystalline silicon substrate;
step 1006: preparing a transparent conductive layer with the thickness of 50nm to 150nm and the refractive index of 1 to 3 on the amorphous silicon layer to form a substrate;
step 1008: and forming a metallization structure on the substrate by using the semiconductor device metallization method of any one of the technical schemes.
In the technical scheme, parameters of the crystalline silicon substrate, the size of the textured surface, the thickness of the amorphous silicon layer, the thickness of the transparent conductive layer and the refractive index are further provided, and the performance of the solar cell can be further guaranteed. Further, in the process of forming the metallization structure, the refractive index of the deposited insulating layer is 1 to 3 so as to be adapted to the transparent conductive layer, and a double antireflection layer structure can be formed with the transparent conductive layer.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
An embodiment of the present invention provides a method for manufacturing a solar cell, including:
step 1102: processing the crystalline silicon substrate through a texturing process;
step 1104: preparing amorphous silicon layers on two sides of the crystalline silicon substrate;
step 1106: preparing a transparent conductive layer on the amorphous silicon layer to form a substrate;
step 1108: and forming a metallization structure on the substrate by using the semiconductor device metallization method of any one of the technical schemes.
As shown in fig. 12 to 17, in this embodiment, after the front-end processes of texturing cleaning, amorphous silicon, transparent conductive layer 206(TCO), etc. are completed, the preparation of the heterostructure solar cell (Hetero junction, HJT, HIT, SHJ) utilizes the large-scale mass production equipment already in the solar industry production, such as PECVD, laser, screen printing and other technologies, a layer of SiNx insulating layer 4(SiOx, MgF, Al2O3 and the like) is deposited on the TCO surface by adopting PECVD, Physical Vapor Deposition (PVD), plasma Deposition (RPD) and other vacuum equipment, and is used as an electroplating protective layer, a gate line pattern is carved on the insulating layer 4 by adopting a laser machine (or dry etching and the like) to be used as a region of the electroplating opening 6, then, using a screen printer (or an ink jet printer or the like), a conductive paste is printed as the plating seed layer 8 in the opening area. Because the insulating layer 4 generally has an antireflection effect, the insulating layer 4 and the TCO film layer can form a double-layer antireflection layer through film layer design and process optimization, after the electroplating process is finished, the insulating layer 4 in a non-metal area can be selected not to be removed, and the double antireflection structure of the insulating layer 4 and the TCO material is helpful for improving the current of the SHJ battery and reducing the use of the TCO material.
In this embodiment, on a silicon waferThe processes prior to the completion of metallization, as shown in fig. 12, form the substrate 2 including a texturing clean, double-sided intrinsic/doped amorphous silicon deposition, and double-sided TCO film deposition. The resistivity of the crystalline silicon substrate 202 is 0.1 to 5ohm cm, the size of the suede is 1 to 5um, or the size of the suede is 4 to 10 um; the amorphous silicon layer 204 has a thickness of 1-30 nm, and the TCO film may be Indium Tin Oxide (ITO) or Indium tungsten oxide (In)2O3W, IWO) and the like, the thickness is 50 to 150nm, and the refractive index is 1 to 3.
In this embodiment, after the front-end process is completed, i.e. the metallization process is performed, the device structure varies with the process as shown in fig. 13 to 17:
as shown in fig. 13, in the first step, a SiNx film is deposited as an electroplating insulation layer 4 on the TCO films on the front and back sides of the substrate 2 by using a PECVD method. The SiNx film has a thickness of 10 to 2000nm and a refractive index of 1.0 to 3.0. The SiNx and TCO thin films form a double antireflection layer structure through design and process debugging of thickness, refractive index and the like, and the insulating layer 4 is not removed after electroplating.
As shown in fig. 14, in the second step, a plating opening 6 is etched on the insulating layer 4 by using laser, the insulating layer 4 is removed, and the TCO film layer is exposed, where the opening pattern is a metallization pattern, and a picosecond laser is generally used to reduce laser damage, or other lasers or technologies may be used; the width of the opening is generally between 2 microns and 100 microns, and the width of the opening is appropriately adjusted according to the purpose of the process.
As shown in fig. 15, in the third step, a screen printer is used to print conductive paste at the plating openings 6, and a drying or sintering process is selected according to different conductive material characteristics, so as to complete the preparation of the selective plating seed layer 8.
As shown in fig. 16, in the fourth step, a copper plating layer and a tin plating layer are grown on the selective plating seed layer 8 by a plating process as the metallized structure 10 of the SHJ. By controlling the parameters of the electroplating process, the height and the width of the metal grid line can be adjusted.
As shown in fig. 17, in a fifth step, the SiNx insulating layer 4 is removed by wet etching, such as HF dip, or other dry etching, such as plasma etching, to form an SHJ solar cell structure.
In the description of the present invention, the terms "plurality" or "a plurality" refer to two or more, and unless otherwise specifically limited, the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention; the terms "connected," "mounted," "secured," and the like are to be construed broadly and include, for example, fixed connections, removable connections, or integral connections; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, the description of the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method for metallization of a semiconductor device, comprising:
depositing insulating layers on two sides of the substrate;
arranging a mask layer on the insulating layer, and forming an etching pattern on the mask layer;
etching the insulating layer based on the etching pattern until the substrate is exposed, and forming an electroplating opening;
arranging conductive slurry at the electroplating opening to form an electroplating seed layer;
and forming a metallization structure on the electroplating seed layer.
2. The method of claim 1, wherein the step of depositing the insulating layer on both sides of the substrate comprises:
and depositing insulating layers with the thickness of 10nm to 2000nm on the two sides of the substrate.
3. The method of claim 1, wherein the step of depositing the insulating layer on both sides of the substrate comprises:
and depositing at least one of silicon oxide, magnesium fluoride and aluminum oxide on the two sides of the base to form the insulating layer.
4. The method of claim 1, wherein the step of etching the insulating layer to expose the substrate and form the plated opening comprises:
photoetching a part of the insulating layer by a laser machine until the substrate is exposed to form a plating opening; or
And forming a plating opening by plasma etching part of the insulating layer until the substrate is exposed.
5. The method of claim 1, wherein the step of disposing a conductive paste at the plating opening and forming a plating seed layer comprises:
printing conductive paste at the electroplating opening through a screen printer;
and drying or sintering the conductive slurry to form the electroplating seed layer.
6. The method of claim 1, wherein the step of forming the metallization structure on the plating seed layer comprises:
and depositing a copper electroplating layer and/or a tin electroplating layer on the electroplating seed layer through an electroplating process to form the metallization structure.
7. The semiconductor device metallization method of any one of claims 1 to 6, further comprising:
etching the mask layer;
and forming a double anti-reflection layer structure by the part of the insulating layer which is not etched and the substrate.
8. The semiconductor device metallization method of any one of claims 1 to 6, further comprising:
etching the mask layer;
and etching to remove the insulating layer.
9. A method for manufacturing a solar cell, comprising:
processing the crystalline silicon substrate through a texturing process;
preparing amorphous silicon layers on two sides of the crystalline silicon substrate;
preparing a transparent conductive layer on the amorphous silicon layer to form a substrate;
forming a metallization structure on the substrate by the semiconductor device metallization method of any one of claims 1 to 8.
10. The method for preparing a solar cell according to claim 9, comprising:
preparing a suede with the side length of 1um to 10um on a crystalline silicon substrate with the resistivity of 0.1 to 5ohm cm through a texturing process;
preparing amorphous silicon layers with the thickness of 1nm to 30nm on the two sides of the crystalline silicon substrate;
a transparent conductive layer having a thickness of 50nm to 150nm and a refractive index of 1 to 3 is prepared on the amorphous silicon layer.
CN202010188231.5A 2020-03-17 2020-03-17 Semiconductor device metallization method and solar cell preparation method Pending CN111430508A (en)

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Application publication date: 20200717