CN111427565B

CN111427565B - Formal verification method

Info

Publication number: CN111427565B
Application number: CN202010113863.5A
Authority: CN
Inventors: 黄滟鸿; 杨秀丽; 史建琦; 曹桂涛; 郭欣
Original assignee: East China Normal University
Current assignee: East China Normal University
Priority date: 2020-02-24
Filing date: 2020-02-24
Publication date: 2022-04-05
Anticipated expiration: 2040-02-24
Also published as: CN111427565A

Abstract

The invention discloses a formal verification method, which comprises an SEDS modeling step, a format verification step and a format verification step, wherein the SEDS modeling step is used for establishing an SEDS model according to an electronic data form specification file; the model conversion step is used for converting the SEDS model into a formal model suitable for model checking; the property specification step is used for formally describing the property of the functional logic of the SEDS model; and the formal verification step is used for performing formal verification on the formal model and the described functional logic properties to obtain a verification result. The method converts the SEDS model into the formal model, carries out the formal description on the property of the functional logic of the SEDS model, carries out the formal verification on the formal model and the property description, realizes the check on the functional logic of the SEDS from the aspect of mathematical reasoning, further ensures the correctness and the reliability of the software, and simultaneously, a user can find the conflict or the defect in the functional logic according to the verification result and correct the error in the SEDS model.

Description

Formal verification method

Technical Field

The invention mainly relates to the field of formal verification, in particular to a formal verification method.

Background

With the continuous adjustment of military strategy and the continuous progress of aerospace technology, SEDS (Space Electronic Data Sheet) becomes the work focus in the field of soss (Space on board interface services). Aiming at the requirements of the rapid integration and the test of the satellite-borne software realized at present, the SEDS can automatically generate the satellite-borne software, the test cases and the related documents through a tool, so that the integration, the test and the maintenance time of the satellite-borne software are reduced, the consistency of data in each development stage is ensured, and once the SEDS is formed, the application of the SEDS usually runs through each stage of the development and the operation of a project. Therefore, the functional logic consistency and completeness of the SEDS are important.

At present, the testing method is mainly adopted to verify the correctness of the functional logic of the SEDS. However, the testing method can only test whether the functional logic of the SEDS is correct in an enumeration manner, and cannot cover all states of the SEDS, so that the correctness and reliability of the software cannot be guaranteed.

Disclosure of Invention

The object of the present invention is to provide a formal verification method for the above-mentioned deficiencies of the prior art, and the object is achieved by the following technical solution.

Specifically, the invention provides a formal verification method, which comprises the following steps:

an SEDS modeling step, namely establishing an SEDS model according to an SEDS schema file specified by the electronic data form;

a model conversion step, converting the SEDS model into a formal model suitable for model checking;

a property specification step, wherein the properties of the functional logic of the SEDS model are described in a formalized mode;

and a formal verification step, namely performing formal verification on the formal model and the described functional logic properties to obtain a verification result.

Preferably, in the formal verification method, the SEDS modeling step specifically reads the SEDS schema file through an Eclipse modeling framework to establish the SEDS model.

Preferably, in the formal verification method, the model conversion step specifically removes information irrelevant to the nature of the functional logic from the SEDS model by using a language analysis tool, and then converts the information into the formal model by using a conversion rule.

Preferably, the formal verification method as described above, the property specification step comprises a consistency specification step and a completeness specification step;

the consistency specification step is to describe the consistency of the functional logic of the SEDS model in a formalized mode by using a preset property description language;

and the completeness specification step describes the completeness of the functional logic of the SEDS model in a formalized mode by using a preset property description language.

Preferably, the formal verification system of the above-mentioned formal verification, the formal description of consistency is used to check whether there is a contradiction in the functional logic of the SEDS model.

Preferably, the formal verification method of completeness, as described above, describes formally whether the functional logic used to check the SEDS model is able to completely and exhaustively characterize the function to be described.

Preferably, in the formal verification method, the formal verification step inputs the formal model and the described functional logic property into a model detection tool, so that the model detection tool performs formal verification on the formal model and the described functional logic property and outputs a verification result.

Preferably, the formal verification method as described above, the verification result comprising a result that the model satisfies the property and a result that the model does not satisfy the property;

when the verification result is that the model does not meet the property, the model detection tool also outputs a counter example result, and a user can correct and improve the SEDS model according to the counter example result.

The formal verification method described in the first aspect converts the established SEDS model into a formal model suitable for model checking, describes the properties of the functional logic of the SEDS model in a formal manner, and then verifies the formal model and the described properties of the functional logic in a formal manner, so as to accurately check the functional logic of the SEDS from the viewpoint of mathematical reasoning, thereby ensuring the correctness and reliability of software, and simultaneously, a user can find conflicts or defects in the functional logic according to the verification result and correct errors in the SEDS model.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 shows a flow diagram of a formal verification method according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The invention adopts formal verification technology to accurately check the functional logic of the SEDS so as to ensure the correctness and reliability of software.

Based on this, the invention proposes a formal verification method for checking the SEDS functional logic, which can be run on an electronic device (such as a PC).

Fig. 1 is a flowchart of a formal verification method according to the present invention, as shown in fig. 1, the formal verification method including the steps of:

an SEDS modeling step 110, namely establishing an SEDS model according to an SEDS schema file of the electronic data form specification;

a model conversion step 120 of converting the SEDS model into a formal model suitable for model checking;

a property specification step 130, which describes the properties of the functional logic of the SEDS model in a formal manner;

and a formal verification step 140, performing formal verification on the formal model and the described functional logic properties to obtain a verification result.

It will be understood by those skilled in the art that the present invention does not limit the order in which the model conversion step 120 and the property specification step 130 are executed in sequence.

In this embodiment, the established SEDS model is converted into a formal model suitable for model checking, the properties of the functional logic of the SEDS model are described in a formal manner, and then the formal model and the described functional logic properties are verified in a formal manner, so that the functional logic of the SEDS is accurately checked from the mathematical reasoning perspective, thereby ensuring the correctness and reliability of software.

In an embodiment, the SEDS modeling step 110 specifically reads the SEDS schema file through an Eclipse modeling framework to establish a SEDS model.

The Eclipse Modeling Framework (EMF) belongs to an Eclipse plug-in tool, and the SEDS model is expressed in an XML format and used for describing a system, equipment, a software interface and the like. SEDS content is divided into three parts: interface descriptions, protocols, and descriptions of programs, documents.

In one embodiment, the model conversion step 120 specifically removes information irrelevant to the property of the functional logic from the SEDS model through a language parsing tool, and then converts the information into a formal model by using a conversion rule.

The method comprises the steps of analyzing behaviors and attributes of each class and each key object in the SEDS model by using a language analysis tool, extracting key information and removing information irrelevant to the property of functional logic so as to ensure the simplicity and integrity of the model, and finally converting the model into a proper formal model by using a conversion rule.

Illustratively, the formal model may be a finite state system, a time automaton, or the like.

In one embodiment, with continued reference to fig. 1, the property specification step 130 includes a consistency specification step and a completeness specification step; the consistency specification step utilizes a preset property description language to formally describe the consistency of the functional logic of the SEDS model; the completeness specification step 132 formally describes the completeness of the functional logic of the SEDS model using a preset property description language.

Wherein the formalized description of consistency is used for checking whether functional logic of the SEDS model has contradiction. A formal description of completeness is used to check whether the functional logic of the SEDS model is able to completely delineate the function to be described.

Illustratively, the property description language may be an LTL (Linear Temporal Logic) language. Linear Temporal Logic (LTL) is widely used today in the field of Computer Science (CS). It is often used as a property language for describing system behavior and used in the research directions of program verification, program synthesis, Artificial Intelligence (AI), and the like.

In one embodiment, the formal verification step 140 inputs the formal model and the described functional logic property into a model detection tool to cause the model detection tool to formally verify the formal model and the described functional logic property and output a verification result.

The model detection tool (such as PAT tool) performs search traversal through a model detection algorithm to obtain a formal verification result. The verification result comprises a result that the model satisfies the property and a result that the model does not satisfy the property, and when the verification result is that the model does not satisfy the property, the model detection tool also outputs a counter-example result.

It should be noted that, when the verification result is that the model does not satisfy the property, the user may modify and improve the SEDS model according to the counter-example result output by the model detection tool, so as to continuously improve the specific details through model refinement, and gradually mature and perfect the model.

That is, the model is modified and improved by analyzing the counterexample result, and then the model conversion step 120, the property reduction step 130, and the formal verification step 140 are performed until the output model satisfies the property result, that is, the SEDS model reaches the ideal state.

It should be noted that:

the algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose devices may be used with the teachings herein. The required structure for constructing such a device will be apparent from the description above. Moreover, the present invention is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known systems, structures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed system should not be interpreted to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the devices of the embodiments may be adaptively changed and disposed in one or more devices other than the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component, and further, may be divided into a plurality of units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any system or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the creation apparatus of a virtual machine according to embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the system described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or modules not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A formal verification method, comprising:

formal verification, namely performing formal verification on the formal model and the described functional logic properties to obtain a verification result; the formal verification is correctness verification;

wherein the property specification step comprises a consistency specification step and a completeness specification step;

the consistency specification step utilizes a preset property description language to formally describe the consistency of the functional logic of the SEDS model;

the completeness specification step formally describes the completeness of the functional logic of the SEDS model by using a preset property description language.

2. The formal verification method of claim 1 wherein the SEDS modeling step, in particular reading the SEDS schema file through an Eclipse modeling framework, builds a SEDS model.

3. The formal verification method of claim 1 wherein the model transformation step, after removing information that is not related to the nature of functional logic from the SEDS model, in particular by means of a language parsing tool, transforms it into a formal model using transformation rules.

4. The formal verification method of claim 1 wherein the formal description of consistency is used to check whether there are inconsistencies in the functional logic of the SEDS model.

5. The formal verification method of claim 1 wherein the formal description of completeness is used to check whether the functional logic of the SEDS model is able to completely delineate the function to be described without omission.

6. The formal verification method of claim 1 wherein the formal verification step specifically inputs the formal model and the described functional logic properties into a model detection tool to cause the model detection tool to formally verify the formal model and the described functional logic properties and output a verification result.

7. The formal verification method of claim 6 wherein the verification results include results that the model satisfies the property and results that the model does not satisfy the property;