CN111426929A - Method, apparatus and storage medium for performing dynamic and static testing of semiconductors - Google Patents
Method, apparatus and storage medium for performing dynamic and static testing of semiconductors Download PDFInfo
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- CN111426929A CN111426929A CN202010200347.6A CN202010200347A CN111426929A CN 111426929 A CN111426929 A CN 111426929A CN 202010200347 A CN202010200347 A CN 202010200347A CN 111426929 A CN111426929 A CN 111426929A
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- 238000012360 testing method Methods 0.000 title claims abstract description 200
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 238000005070 sampling Methods 0.000 claims description 13
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Abstract
The embodiment of the invention provides a method, a device and a storage medium for executing dynamic and static tests of a semiconductor, belonging to the technical field of testing of semiconductors. The device comprises: a bus capacitor; a first controllable switch; a load inductance switching module; a second controllable switch; a first signal enabling module; a second signal enabling module; and the upper computer is connected with the first signal enabling module and the second signal enabling module and is used for controlling the work of the first signal enabling module and the second signal enabling module so as to complete the dynamic and static tests. The method, the device and the storage medium simultaneously realize the dynamic test and the static test operation of the semiconductor by adopting the same set of equipment, solve the technical problem that two sets of equipment are required for executing the dynamic test and the static test in the prior art, and improve the efficiency of the semiconductor test.
Description
Technical Field
The present invention relates to the field of semiconductor testing technologies, and in particular, to a method, an apparatus, and a storage medium for performing dynamic and static testing of a semiconductor.
Background
The performance test of a Semiconductor power device, such as an Insulated Gate Bipolar Transistor (IGBT), a Metal-Oxide-Semiconductor Field effect Transistor (MOSFET), and the like, is generally divided into two parts, namely a dynamic test and a static test, wherein the former performs test evaluation on the switching characteristics of the power device and the reverse recovery characteristics of an internal freewheeling diode or a parasitic diode, and the latter performs test evaluation on various static parameters of the power device, such as the conduction voltage drop and the threshold voltage. The original power device test system scheme has the following two problems:
(1) the automation degree of the test process and the data processing process is low, and the test working points need to be manually switched, so that the test efficiency is greatly reduced;
(2) the complete performance test of the device needs to adopt two systems of static test and dynamic test, namely different hardware circuits and software systems are needed to test the device, thereby causing the problems of higher equipment cost, larger volume, lower test efficiency and the like.
Disclosure of Invention
The invention aims to provide a method, a device and a storage medium for executing semiconductor dynamic and static tests. The method, the device and the storage medium can simultaneously realize the dynamic test and the static test of the semiconductor.
In order to achieve the above object, an embodiment of the present invention provides an apparatus for performing dynamic and static tests of a semiconductor, the apparatus including:
the bus capacitor is used for connecting one end with the drain electrode of a first device under test, and the other end with the source electrode of a second device under test, and the source electrode of the first device under test is connected with the drain electrode of the second device under test;
one end of the first controllable switch is connected with one end of the bus capacitor;
a load inductance switching module, one end of which is used for connecting to the source electrode of the first tested device, and the other end of which is connected with the other end of the first controllable switch;
one end of the second controllable switch is connected with the other end of the load inductance switching module, and the other end of the second controllable switch is used for being connected with a source electrode of the second tested device;
a first signal enabling module for collecting a current of a node between the drain of the first device under test and the bus capacitor, a voltage between the gate of the first device under test and the source of the first device under test, and a voltage between the source of the first device under test and the drain of the first device under test;
a second signal enabling module, configured to collect a current of a node between a drain of the second device under test and the bus capacitor, a voltage between a gate of the second device under test and a source of the second device under test, and a voltage between the source of the second device under test and the drain of the second device under test;
and the upper computer is connected with the first signal enabling module and the second signal enabling module and is used for controlling the work of the first signal enabling module and the second signal enabling module so as to complete the dynamic and static tests.
Optionally, at least one of the first signal enabling module and the second signal enabling module comprises:
a high-speed sampling board card for collecting the current of a node between the drain of the first device under test/the second device under test and the bus capacitor, the voltage between the gate of the first device under test/the second device under test and the source of the first device under test/the second device under test, and the voltage between the source of the first device under test/the second device under test and the drain of the first device under test/the second device under test;
the first clamping circuit is connected with the first end of the high-speed sampling board card;
the second clamping circuit is connected with the second end of the high-speed sampling board card;
and one end of the isolation circuit is connected with the third end of the high-speed sampling board card, and the other end of the isolation circuit is used for outputting a sampling signal or receiving a test signal input by an upper computer.
Optionally, the apparatus further comprises a first diode, an anode for connecting with the source of the first device under test, and a cathode for connecting with the drain of the first device under test.
Optionally, the apparatus further comprises a second diode, an anode for the source connection of the second device under test, and a cathode for the drain connection of the second device under test.
Optionally, the load inductance switching module includes:
at least two inductors connected in series, wherein one end of the first inductor is used for being connected with the source electrode of the first tested device;
and each inductor is connected with the other end of the first controllable switch through the corresponding third controllable switch.
Optionally, the apparatus further includes a temperature adjustment module, connected to the upper computer, for adjusting the temperature of the first device under test/the second device under test.
In another aspect, the present invention also provides a method of performing dynamic and static testing of a semiconductor, the method comprising:
obtaining a DoE parameter;
selecting a test point from the DoE parameters in sequence;
inputting the test point into a first signal enabling module/a second signal enabling module of the device to execute the test;
receiving results of selected test points from the first signal enabling module/the second signal enabling module;
judging whether the selected test point is the last test point or not;
under the condition that the selected test point is judged not to be the last test point, selecting one test point from the DoE parameters again according to the sequence until the selected test point is judged to be the last test point;
under the condition that the selected test point is judged to be the last test point, performing data batch processing operation on all the results, and extracting the static characteristic parameters/dynamic characteristic parameters of the device;
outputting the first device under test/second device under test static characteristic parameters/dynamic characteristic parameters.
Optionally, the receiving the result of the selected test point from the first signal enabling module/the second signal enabling module specifically includes:
and storing the results in a uniform format.
Optionally, the DoE parameter includes at least one of a gate voltage, a test current, and a test temperature.
In yet another aspect, the present invention also provides a storage medium storing instructions for reading by a machine to cause the machine to perform a method as claimed in any one of the above.
By adopting the technical scheme, the method, the device and the storage medium for executing the dynamic and static tests of the semiconductor provided by the invention realize the dynamic test and the static test operation of the semiconductor at the same time by adopting the same set of equipment, thereby solving the technical problem that two sets of equipment are required for executing the dynamic test and the static test in the prior art and improving the efficiency of the semiconductor test.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a circuit diagram of an apparatus for performing dynamic and static testing of a semiconductor provided in accordance with the present invention;
FIG. 2 is a circuit diagram of an apparatus for performing dynamic and static testing of a semiconductor provided in accordance with the present invention; and
FIG. 3 is a flow chart of a method of performing semiconductor dynamic and static testing provided in accordance with the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
In the embodiments of the present invention, unless otherwise specified, the use of directional terms such as "upper, lower, top, and bottom" is generally used with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, or gravitational direction.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between the various embodiments can be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not be within the protection scope of the present invention.
In FIG. 1, the apparatus may include a bus capacitor C1, a first device-under-test Q1, a second device-under-test Q2, a first controllable switch S1, a second controllable switch S2, a load inductance switching module L, a first signal enable module 01, and a second signal enable module 02.
One end of the bus capacitor C1 may be used to connect with the drain of the first device under test Q1, the other end may be used to connect with the source of the second device under test Q2, and the source of the first device under test Q1 may be connected with the drain of the second device under test Q2.
One end of the first controllable switch S1 may be connected to one end of the bus capacitor C1, one end of the load inductor switching module L may be used to connect to the source of the first device under test Q1, and the other end may be connected to the other end of the first controllable switch S1.
One end of the second controllable switch S2 may be connected to the other end of the load inductance switching module L, and the other end may be used to connect to the source of the second device under test Q2.
The first signal enable module 01 may be used to collect the current (I) at the node between the drain of the first device under test Q1 and the bus capacitance C1D1、ID2) Voltage (V) between the gate of the first device under test Q1 and the source of the first device under test Q1GS1、VGS2) And the voltage between the source of the first device under test Q1 and the drain of the first device under test Q1.
The second signal enable module 02 may be used to collect the current at the node between the drain of the second device under test Q2 and the bus capacitance C1, the voltage between the gate of the second device under test Q2 and the source of the second device under test Q2, and the voltage between the source of the second device under test Q2 and the drain of the second device under test Q2.
The upper computer 03 (not shown in fig. 1) may be connected to the first signal enabling module 01 and the second signal enabling module 02, and is configured to control operations of the first signal enabling module 01 and the second signal enabling module 02 to perform dynamic and static tests on the semiconductor.
As for the specific form of the first signal enable module 01 and the second signal enable module 02, various forms known to those skilled in the art may be possible. In a preferred example of the present invention, at least one of the first and second signal enabling modules 01 and 02 may include a high speed sample board 023, a first clamp 021, a second clamp 022, and an isolation circuit 024.
The high-speed sampling board 023 can be used for sampling the current (I) of a node between the drain of the first device under test Q1/the second device under test Q2 and the bus capacitor C1D1、ID2) Voltage (V) between the gate of the first device under test Q1/second device under test Q2 and the source of the first device under test Q1/second device under test Q2GS1、VGS2) And the voltage between the source of the first device under test Q1/second device under test Q2 and the drain of the first device under test Q1/second device under test Q2. The first clamp 021 may be coupled to a first terminal of the high speed sample board 023. A second clamp 022 may be connected to a second terminal of the high speed sample board 023. One end of the isolating circuit 024 can be connected with the third end of the high-speed sampling board card 023, and the other end of the isolating circuit 024 is used for outputting a collecting signal or receiving a test signal input by the upper computer 03.
In one embodiment of the present invention, the apparatus may further include a first diode Q1. The first diode Q1 may have a positive terminal for connection to the source of the first device under test Q1 and a negative terminal for connection to the drain of the first device under test Q1.
In one embodiment of the present invention, the apparatus may further include a second diode Q2, with an anode for the source connection of the second device-under-test Q2 and a cathode for the drain connection of the second device-under-test Q2.
In a preferred example of the present invention, the load inductance switching module L may include at least two inductors L connected in series and third controllable switches S3 corresponding to the inductors L one to one, wherein one end of a first inductor L0 may be used to connect to the source of the first device under test Q1, each inductor 5630 may be connected to the other end of the first controllable switch S1 through a corresponding third controllable switch S3, and the upper computer 03 may adjust the load inductance by controlling different third controllable switches S3, thereby implementing a test on the semiconductor device.
In one embodiment of the invention, dynamic and static testing of a portion of a semiconductor is considered to involve changes in temperature conditions. Therefore, as shown in fig. 2, the apparatus may further include a temperature adjustment module 04. The temperature adjustment module 04 may be connected to the upper computer 03 for adjusting the temperature of the first device under test Q1/the second device under test Q2.
In this embodiment, the control method for the apparatus as shown in fig. 1 or fig. 2 may be in various forms known to those skilled in the art. In one embodiment of the invention, the method may include the steps illustrated in fig. 3, for example. In fig. 3, the method may include:
in step S10, the DoE parameter is acquired. Wherein the DoE parameter may include at least one of a gate voltage, a test current, and a test temperature.
In step S11, a test point is selected from the DoE parameters in order;
in step S12, a test point is input into a first/second signal enable block of the apparatus as shown in fig. 1 or fig. 2 to perform a test. Further, to facilitate statistics of the results, the results may be stored in a uniform format.
In step S13, receiving the result of the selected test point from the first/second signal enabling modules;
in step S14, it is determined whether the selected test point is the last test point;
under the condition that the selected test point is judged not to be the last test point, selecting one test point from the DoE parameters again according to the sequence until the selected test point is judged to be the last test point;
in step S15, under the condition that the selected test point is determined to be the last test point, performing data batch processing operation on all the results, and extracting device static characteristic parameters/dynamic characteristic parameters;
in step S16, the first device under test Q1/second device under test Q2 static feature parameters/dynamic feature parameters are output.
In yet another aspect, the present invention also provides a storage medium that may store instructions for reading by a machine to cause the machine to perform a method as illustrated in fig. 3.
By adopting the technical scheme, the method, the device and the storage medium for executing the dynamic and static tests of the semiconductor provided by the invention realize the dynamic test and the static test operation of the semiconductor at the same time by adopting the same set of equipment, thereby solving the technical problem that two sets of equipment are required for executing the dynamic test and the static test in the prior art and improving the efficiency of the semiconductor test.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
Those skilled in the art can understand that all or part of the steps in the method for implementing the above embodiments may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, various different embodiments of the present invention may be arbitrarily combined with each other, and the embodiments of the present invention should be considered as disclosed in the disclosure of the embodiments of the present invention as long as the embodiments do not depart from the spirit of the embodiments of the present invention.
Claims (10)
1. An apparatus for performing dynamic and static testing of a semiconductor, the apparatus comprising:
the bus capacitor is used for connecting one end with the drain electrode of a first device under test, and the other end with the source electrode of a second device under test, and the source electrode of the first device under test is connected with the drain electrode of the second device under test;
one end of the first controllable switch is connected with one end of the bus capacitor;
a load inductance switching module, one end of which is used for connecting to the source electrode of the first tested device, and the other end of which is connected with the other end of the first controllable switch;
one end of the second controllable switch is connected with the other end of the load inductance switching module, and the other end of the second controllable switch is used for being connected with a source electrode of the second tested device;
a first signal enabling module for collecting a current of a node between the drain of the first device under test and the bus capacitor, a voltage between the gate of the first device under test and the source of the first device under test, and a voltage between the source of the first device under test and the drain of the first device under test;
a second signal enabling module, configured to collect a current of a node between a drain of the second device under test and the bus capacitor, a voltage between a gate of the second device under test and a source of the second device under test, and a voltage between the source of the second device under test and the drain of the second device under test;
and the upper computer is connected with the first signal enabling module and the second signal enabling module and is used for controlling the work of the first signal enabling module and the second signal enabling module so as to complete the dynamic and static tests.
2. The apparatus of claim 1, wherein at least one of the first signal enabling module and the second signal enabling module comprises:
a high-speed sampling board card for collecting the current of a node between the drain of the first device under test/the second device under test and the bus capacitor, the voltage between the gate of the first device under test/the second device under test and the source of the first device under test/the second device under test, and the voltage between the source of the first device under test/the second device under test and the drain of the first device under test/the second device under test;
the first clamping circuit is connected with the first end of the high-speed sampling board card;
the second clamping circuit is connected with the second end of the high-speed sampling board card;
and one end of the isolation circuit is connected with the third end of the high-speed sampling board card, and the other end of the isolation circuit is used for outputting a sampling signal or receiving a test signal input by an upper computer.
3. The apparatus of claim 1, further comprising a first diode having an anode for connection to the source of the first device under test and a cathode for connection to the drain of the first device under test.
4. The apparatus of claim 1, further comprising a second diode having an anode for source connection of the second device under test and a cathode for drain connection of the second device under test.
5. The apparatus of claim 1, wherein the load inductance switching module comprises:
at least two inductors connected in series, wherein one end of the first inductor is used for being connected with the source electrode of the first tested device;
and each inductor is connected with the other end of the first controllable switch through the corresponding third controllable switch.
6. The apparatus of claim 1, further comprising a temperature adjustment module connected to the upper computer for adjusting the temperature of the first/second dut.
7. A method of performing semiconductor dynamic and static testing, the method comprising:
obtaining a DoE parameter;
selecting a test point from the DoE parameters in sequence;
inputting the test point into a first/second signal enabling module of the apparatus of any one of claims 1 to 6 to perform a test;
receiving results of selected test points from the first signal enabling module/the second signal enabling module;
judging whether the selected test point is the last test point or not;
under the condition that the selected test point is judged not to be the last test point, selecting one test point from the DoE parameters again according to the sequence until the selected test point is judged to be the last test point;
under the condition that the selected test point is judged to be the last test point, performing data batch processing operation on all the results, and extracting the static characteristic parameters/dynamic characteristic parameters of the device;
outputting the first device under test/second device under test static characteristic parameters/dynamic characteristic parameters.
8. The method of claim 7, wherein receiving the results of the selected test points from the first/second signal enabling modules specifically comprises:
and storing the results in a uniform format.
9. The method of claim 7, wherein the DoE parameter comprises at least one of a gate voltage, a test current, and a test temperature.
10. A storage medium storing instructions for reading by a machine to cause the machine to perform a method according to any one of claims 7 to 9.
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| CN202010200347.6A CN111426929A (en) | 2020-03-20 | 2020-03-20 | Method, apparatus and storage medium for performing dynamic and static testing of semiconductors |
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