CN111416622A - Clock signal recovery circuit and method, interface circuit and signal synchronization method - Google Patents
Clock signal recovery circuit and method, interface circuit and signal synchronization method Download PDFInfo
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Abstract
The invention discloses a clock signal recovery circuit and method, an interface circuit and a signal synchronization method, relates to the technical field of digital-to-analog conversion, and can ensure that an input digital signal is synchronous with an internal clock signal of a digital-to-analog converter. The clock signal recovery circuit comprises a phase discriminator, wherein the input end of the phase discriminator is in communication connection with the output end of the latch. And the input end of the decoder is in communication connection with the output end of the phase discriminator. And the input end of the phase adjuster is in communication connection with the output end of the decoder, and the output end of the phase adjuster is in communication connection with the input end of the latch. The phase adjuster is used for adjusting the phase of the sampling clock signal according to the control signal and acquiring the adjusted sampling clock signal. When the adjusted sampling clock signal is synchronized with the digital signal, a clock recovery signal is obtained. The invention also provides an interface circuit and a synchronous signal method.
Description
Technical Field
The present invention relates to the field of digital-to-analog conversion technologies, and in particular, to a clock signal recovery circuit and method, an interface circuit, and a signal synchronization method.
Background
A digital-to-analog converter (DAC) is a circuit that converts a digital signal to an analog signal. With the development of integrated circuit technology, the digital-to-analog converter with high speed and high performance can simplify the structure of the integrated circuit and improve the flexibility and portability of the design of the integrated circuit.
Digital-to-analog converters in practical applications, it is necessary to transmit digital signals to the data converter through a data interface. In order to ensure that the digital-to-analog converter can meet the requirements of the development of integrated circuit technology, higher requirements are put on the data transmission quality of a data interface.
In practical applications, the digital signal may be offset from the sampling clock signal in the data interface with time and working environment changes, so that the transmission quality of the digital signal is reduced.
Disclosure of Invention
The invention aims to provide a clock signal recovery circuit and method, an interface circuit and a signal synchronization method which can ensure that an input digital signal is synchronized with an internal clock signal of a digital-to-analog converter.
In order to achieve the above object, the present invention provides a clock signal recovery circuit, which is applied in a digital-to-analog converter, the clock signal recovery circuit comprising: and the latch is used for receiving the digital signal and sampling the digital signal by using the sampling clock signal to obtain a digital signal sample.
The input end of the phase discriminator is in communication connection with the output end of the latch and is used for obtaining a signal containing a phase error according to the phase difference between the digital signal sample and the internal clock signal; the internal clock signal is a clock signal of the digital-to-analog converter.
And the input end of the decoder is in communication connection with the output end of the phase discriminator and is used for converting the signal containing the phase error into a control signal.
And the input end of the phase adjuster is in communication connection with the output end of the decoder, and the output end of the phase adjuster is in communication connection with the input end of the latch. The phase adjuster is used for adjusting the phase of the sampling clock signal according to the control signal and acquiring the adjusted sampling clock signal. When the adjusted sampling clock signal is synchronized with the digital signal, a clock recovery signal is obtained.
Compared with the prior art, the clock signal recovery circuit provided by the invention has the advantages that after the latch receives the digital signal, the amplitude and the frequency of the digital signal are fixed, so that the distortion of the digital signal in the latch is avoided. At the same time, the latch is provided with a sampling clock signal to sample the digital signal that is being true in the latch with the sampling clock signal, at which time a digital signal sample can be obtained. The obtained digital signal sample can be sent to the phase discriminator through any existing communication mode, an internal clock signal is provided for the phase discriminator, the phase discriminator can determine the phase difference between the digital signal sample and the internal clock signal, and a signal containing a phase error can be obtained according to the determined phase difference. The obtained signal containing the phase error may be transmitted to a decoder through any conventional communication method, and the decoder may convert the signal containing the phase error into a control signal. The phase adjuster adjusts the sampling clock signal provided for the latch under the control of the control signal, resamples the digital signal by using the adjusted sampling clock signal, redetermines the signal containing the phase error by using the phase discriminator to the digital signal sample obtained again, redetermines the control signal by using the decoder based on the redetermined signal containing the phase error, and readjusts the phase of the sampling clock signal by using the phase adjuster under the control of the redetermined control signal, taking the phase as a cycle until the phase difference between the adjusted sampling clock signal and the digital signal and the internal clock signal does not change any more, namely when the signal containing the phase error determined by the phase discriminator is 0, the clock signal is recovered and finished to obtain a clock recovery signal. When the clock recovery circuit provided by the invention is applied to an interface circuit used by a digital-to-analog converter, the clock recovery signal can be used for sampling the input digital signal, the current situation that the digital signal is not resampled or missed in sampling is ensured, the correctness and the integrity of the obtained sampling signal are finally ensured, and the transmission quality of the signal in the interface circuit is improved.
The invention also provides a clock signal recovery method, which is applied to the clock signal recovery circuit provided by the invention and comprises the following steps: and acquiring a digital signal, and sampling the digital signal by using a sampling clock signal to obtain a digital signal sample.
Obtaining a signal containing a phase error according to a phase difference between the digital signal sample and the internal clock signal; the internal clock signal is a clock signal of the digital-to-analog converter.
The signal containing the phase error is converted into a control signal.
And adjusting the phase of the sampling clock signal by using the control signal to obtain the adjusted sampling clock signal. When the adjusted sampling clock signal is synchronized with the digital signal, a clock recovery signal is obtained.
Compared with the prior art, the clock data recovery method provided by the invention has the same technical effect as the clock data recovery circuit in the technical scheme, and is not described herein again.
The present invention also provides an interface circuit comprising: the device comprises a signal sampling module, a signal synchronization module, a synchronization detection module and a synchronization signal output module.
The signal sampling module comprises a clock recovery circuit, and the digital signal is sampled by using a clock recovery signal provided by the clock recovery circuit to obtain a first sampling signal. The clock recovery circuit is the clock recovery circuit provided by the invention.
The signal synchronization module is in communication connection with the signal sampling module and is used for synchronizing the first sampling signal with the test signal to obtain a first synchronization signal.
The synchronous detection module is in communication connection with the signal synchronization module and is used for detecting the synchronous state of the first synchronous signal and the synchronous test signal.
The synchronous signal output module is respectively in communication connection with the signal synchronous module and the synchronous detection module; when the synchronous detection module detects that the synchronous detection module is synchronous, the synchronous signal output module outputs a first synchronous signal.
Compared with the prior art, the interface circuit provided by the invention has the same technical effect as the clock signal recovery circuit in the technical scheme, and is not described herein again.
The invention also provides a signal synchronization method which is applied to the interface circuit provided by the invention. The signal synchronization method comprises the following steps:
and providing a clock recovery signal, and sampling the digital signal by using the clock recovery signal to obtain a first sampling signal.
And providing a test signal, and synchronizing the first sampling signal with the test signal to obtain a first synchronization signal.
And detecting the synchronization state of the first synchronization signal and the synchronization test signal.
When the synchronization state is synchronous, a first synchronization signal is output.
Compared with the prior art, the beneficial effects of the signal synchronization method provided by the invention are the same as those of the interface circuit in the technical scheme, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a block diagram of a digital-to-analog converter using a data interface according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock recovery circuit according to an embodiment of the present invention;
FIG. 4 is a flowchart of a clock signal recovery method according to an embodiment of the present invention
Fig. 5 is a flowchart of a signal synchronization method according to an embodiment of the present invention.
Wherein: 1. digital-to-analog converter, 2, interface circuit, 3, FPGA;
20. the circuit comprises a signal sampling module, a clock recovery circuit, a latch 2000, a phase discriminator 2001, a decoder 2002, a phase adjuster 2003, a first trigger 201; 21. signal synchronization module, 210, signal memory, 211, first exclusive or logic gate; 22. a synchronous detection module, 220, a second flip-flop, 221, a second exclusive-or logic gate, 222, a third flip-flop; 23. and a synchronous signal output module 230, selecting a logic gate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In addition, in the present invention, directional terms such as "upper" and "lower" are defined with respect to a schematically placed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the orientation in which the components are placed in the drawings.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
Fig. 1 is a block diagram illustrating a digital-to-analog converter using a data interface according to an embodiment of the present invention. As shown in fig. 1, an interface circuit 2 is disposed between an input end of a digital signal and a digital-to-analog converter 1, and during transmission of the digital signal in the interface circuit 2, a sampling clock signal and an internal clock signal of the digital-to-analog converter 1 can be automatically synchronized through the interface circuit 2, and the sampling clock signal synchronized with the internal clock signal is synchronized with the digital signal, so as to improve transmission quality of the digital signal in the interface circuit 2. Meanwhile, the interface circuit 2 may also be directly connected to a Field Programmable Gate Array (FPGA) 3 (abbreviated as FPGA) in a communication manner, and configured to send a synchronization signal to the FPGA3, and receive a command signal from the FPGA 3.
In order to improve the transmission quality of the digital signal, embodiments of the present invention provide an interface circuit, which can transmit the digital signal to a digital-to-analog converter. Fig. 2 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention. As shown in fig. 2, the interface circuit includes a signal sampling module 20, a signal synchronization module 21, a synchronization detection module 22, and a synchronization signal output module 23.
The output end of the signal sampling module 20 is in communication connection with the input end of the signal synchronization module 21, the output end of the signal synchronization module 21 is in communication connection with the input end of the synchronization signal output module 23, the output end of the signal synchronization module 21 is also in communication connection with the input end of the synchronization detection module 22, and the output end of the synchronization detection module 22 is in communication connection with the input end of the synchronization signal output module 23.
The signal sampling module 20 may include a clock recovery circuit 200 and a first flip-flop 201. Clock recovery circuit 200 may receive the digital signal and provide a clock recovery signal that may avoid resampling or missing samples of the digital signal, among other things. The first flip-flop 201 may receive the digital signal and may further sample the digital signal with a clock recovery signal generated by the clock recovery circuit 200 to obtain a first sampled signal. It should be understood that the first Flip-Flop 201 may be a D Flip-Flop (DFF), that is, a digital signal is sampled when the clock recovery signal is at a rising edge.
To more clearly understand how the clock recovery circuit 200 is utilized to provide a clock recovery signal that can avoid resampling or missing samples of a digital signal, embodiments of the present invention also provide a clock recovery circuit. Fig. 3 illustrates a clock signal recovery circuit according to an embodiment of the present invention. As shown in fig. 3, the clock recovery circuit 20 includes a latch 2000, a phase detector 2001, a decoder 2002, and a phase adjuster 2003. The output terminal of the latch 2000 is communicatively connected to the input terminal of the phase detector 2001, the output terminal of the phase detector 2001 is communicatively connected to the input terminal of the decoder 2002, the output terminal of the decoder 2002 is communicatively connected to the input terminal of the phase adjuster 2003, and the output terminal of the phase adjuster 2003 is communicatively connected to the input terminal of the latch 2000. That is, the latch 2000, the phase detector 2001, the decoder 2002, and the phase adjuster 2003 constitute a closed-loop clock signal recovery circuit.
The latch 2000 may receive the digital signal and fix the amplitude and frequency of the digital signal to avoid distortion of the digital signal in the latch 2000. At the same time, a sampling clock signal is provided to the latch 2000, with which the digital signal that is true in the latch 2000 is sampled, at which time the digital signal samples can be obtained.
The obtained digital signal samples may be transmitted to the phase detector 2001 through any conventional communication method, and an internal clock signal is provided to the phase detector 2001, where the internal clock signal refers to a clock signal of a digital-to-analog converter. The digital signal samples are converted by the phase detector 2001 into a binary code, which may characterize the phase of the digital signal samples. The phase detector 2001 is used to compare the phase of the digital signal sample with the phase of the internal clock signal to obtain a signal containing a phase error.
The obtained signal containing the phase error may be transmitted to the decoder 2002 by any communication method, and the control signal is obtained after decoding by the decoder 2002, and at this time, the control signal is also a binary code.
The obtained control signal may be transmitted to the phase adjuster 2003 through any conventional communication method, and the phase adjuster adjusts the sampling clock signal provided to the latch 2000 under the control of the control signal, and resamples the digital signal using the adjusted sampling clock signal.
The digital signal sample obtained by resampling is used again to obtain a signal containing a phase error by the phase detector 2001, the signal containing the phase error obtained by resampling is decoded again by the decoder 2002 to obtain a control signal, under the control of the control signal obtained again, the phase adjuster 2003 adjusts the phase of the sampling clock again, and the cycle is performed in sequence until the adjusted phase of the sampling clock signal and the digital signal is not changed, the clock signal recovery is completed, and the clock recovery signal is obtained. It should be understood that the phase of the adjusted sampling clock signal and the internal clock signal are also the same at this time, that is, the adjusted sampling clock signal and the internal clock signal are also synchronized.
When the clock signal recovery circuit is applied to the interface circuit, the clock recovery signal synchronous with both the digital signal and the internal clock is used for completing sampling of the input digital signal, at the moment, resampling or sampling missing can be avoided for sampling of the digital signal, and therefore correctness and integrity of the obtained sampling signal are ensured, and transmission quality of the signal in the interface circuit is provided.
With continued reference to fig. 2, the signal synchronization module 21 may be configured to synchronize the first sampling signal obtained by the signal sampling module 20 with the test signal to obtain a first synchronization signal.
To obtain the first synchronization signal, the signal synchronization module 21 may comprise a signal memory 210 and a first exclusive-or logic gate 211 in series communication with the signal memory 210.
Specifically, an input of signal memory 210 is communicatively coupled to an output of first flip-flop 201, and an output of signal memory 210 is communicatively coupled to an input of first exclusive-or logic gate 211. The signal memory 210 may be a FIFO (First Input First Output, abbreviated as FIFO) memory.
The first flip-flop 201 transmits the first sampling signal to the signal storage 210, and at the same time, provides the clock recovery signal and the internal clock signal to the signal storage 210. The first sampling signal is synchronized to the internal clock domain in the signal memory 210 by the action of the clock recovery signal and the internal clock signal. When the signal memory 210 is a FIFO memory, the execution sequence of the first sampling signal in the FIFO memory is first-in first-out. That is, the first sampling signal is synchronized with the clock recovery signal and then synchronized with the internal clock signal. The synchronization mode can ensure that the clock recovery signal and the clock domain where the internal clock signal is located are isolated, and no cross occurs.
The first sampling signal synchronized with the internal clock signal is transferred from the memory to the first exclusive or logic gate 211 while the test signal is input to the first exclusive or logic gate 211. The test signal may be a Pseudo-Random Binary code test signal (PRBS) from a digital-to-analog converter. The first sampling signal synchronized with the internal clock signal and the test signal are exclusive-ored in the first exclusive-or logic gate 211, and when the first sampling signal synchronized with the internal clock signal and the test signal are synchronized, the output of the first exclusive-or logic gate 211 is 0, otherwise, the output of the first exclusive-or logic gate 211 is 1. When the output of the first xor logic gate 211 is 1, that is, the first sampling signal synchronized with the internal clock signal is not synchronized with the test signal, the delay of the test signal is adjusted until the output of the first xor logic gate 211 is 0, and at this time, the first sampling signal synchronized with the internal clock signal is synchronized with the test signal. After the synchronization is completed, the first exclusive-or logic gate 211 can also be used as a device for descrambling. That is, when the test signal is the PRBS, since the PRBS is a pseudo random binary test signal, it is a kind of scrambling code for the first sampling signal, and the second xor logic gate 211 can remove the PRBS and only retain the synchronized first synchronization signal.
In order to implement the synchronous state detection of the first sampling signal synchronized with the internal clock signal, the synchronous detection module 22 provided in the embodiment of the present invention may include a second flip-flop 220, a second or logic gate 221, and a third flip-flop 222. An input of the second flip-flop 220 is communicatively coupled to an output of the first exclusive-or gate 211, an output of the second flip-flop 220 is communicatively coupled to an input of the second exclusive-or gate 221, an output of the second exclusive-or gate 221 is communicatively coupled to an input of the third flip-flop 222, and an output of the third flip-flop 222 is communicatively coupled to an input of the second or gate 221. That is, the second exclusive or gate 221 and the third flip-flop 222 constitute a feedback circuit. It should be understood that the second Flip-Flop 220 and the third Flip-Flop 222 may be D Flip-flops (DFFs), that is, the signal to be sampled is resampled when the internal clock signal is at a rising edge.
After the first sampling signal synchronized with the internal clock signal is synchronized with the test signal in the first exclusive-or logic gate 211, the first sampling signal is transmitted to the second flip-flop 220, the second sampling signal is transmitted to the second exclusive-or logic gate 221, the synchronous test signal is input to the second exclusive-or logic gate 221, the second sampling signal and the synchronous test signal are subjected to exclusive-or logic operation in the second exclusive-or logic gate 221, the operation result is transmitted to the third flip-flop 222, the operation result is resampled under the action of the internal clock signal to obtain a third sampling signal, the third sampling signal is fed back to the second exclusive-or logic gate 221, and is subjected to logic operation with the second sampling signal again, and the operation result is circulated until the operation result of the second exclusive-or logic gate 221 is 0, and at this time, the second sampling signal and the synchronous test signal are synchronized. It should be appreciated that to ensure the accuracy of the third sampled signal, the third flip-flop 222 is cleared with a synchronous clear signal provided to the third flip-flop 222 each time a sample is completed and output.
In order to output the first synchronization signal, the synchronization signal output module 23 according to the embodiment of the present invention includes a selection logic gate 230. Specifically, an input of the selection logic gate 230 is communicatively coupled to an output of the second flip-flop 220, while an input of the selection logic gate 230 is also communicatively coupled to an output of the synchronous test module.
When the second sampling signal and the synchronous test signal are synchronized, the selection logic gate 230 is set to 1, and the first synchronous signal is output to the dac. When the second sampling signal is not synchronized with the synchronous test signal, the selection logic gate 230 is set to 0, and no first synchronous signal is output.
Based on the clock signal recovery circuit provided by the embodiment of the invention, the embodiment of the invention also provides a clock signal recovery method. Fig. 4 is a flowchart illustrating a clock signal recovery method according to an embodiment of the present invention. As shown in fig. 4, the clock signal recovery method includes:
and S10, acquiring the digital signal, and sampling the digital signal by using the sampling clock signal to obtain a digital signal sample. The digital signal may be acquired by a latch provided in the clock recovery circuit, and the latch may be provided with a sampling clock signal in order to acquire the digital signal sample.
And S11, obtaining a signal containing phase errors according to the phase difference between the digital signal samples and the internal clock signal. The digital signal sample obtained in step S10 is transmitted to the phase detector of the clock signal recovery circuit, and the internal clock signal is supplied to the phase detector. The phase detector converts the digital signal samples into a binary code, which may characterize the phase of the digital signal samples. The phase discriminator is used to compare the phase of the digital signal sample with the phase of the internal clock to obtain a signal containing a phase error.
And S12, converting the signal containing the phase error into a control signal. The signal containing the phase error obtained in step S11 may be transmitted to a decoder of the clock recovery circuit, and the control signal is obtained after decoding by the decoder, where the control signal is also a binary code.
And S13, adjusting the phase of the sampling clock signal by using the control signal to obtain the adjusted sampling clock signal. When the adjusted sampling clock signal is synchronized with the digital signal, a clock recovery signal is obtained. The control signal obtained in step S12 is transmitted to a phase adjuster provided in the clock recovery circuit, the phase adjustment adjusts the phase of the sampling clock signal supplied to the latch under the control of the control signal, and the digital signal is resampled using the adjusted sampling clock signal.
And under the control of the reacquired control signal, the phase adjuster readjusts the phase of the sampling clock, and the cycle is performed in sequence until the phases of the adjusted sampling clock signal and the digital signal are not changed, so that the clock signal recovery is completed, and the clock recovery signal is obtained. It should be understood that the phase of the adjusted sampling clock signal and the internal clock signal are also the same at this time, that is, the adjusted sampling clock signal and the internal clock signal are also synchronized.
Based on the interface circuit provided by the embodiment of the invention, the embodiment of the invention also provides a signal synchronization method. Fig. 5 is a flowchart illustrating a signal synchronization method according to an embodiment of the present invention. As shown in fig. 5, the signal synchronization method includes:
and S20, providing a clock recovery signal, and sampling the digital signal by using the clock recovery signal to obtain a first sampling signal. The first sampling signal may be obtained by the signal sampling module under the action of the clock recovery signal.
And S21, providing a test signal, and synchronizing the first sampling signal with the test signal to obtain a first synchronization signal. The first sampling signal and the internal clock signal may be synchronized in the signal synchronization module, and then the first sampling signal synchronized with the internal clock signal may be synchronized with the test signal to obtain the first synchronization signal.
And S22, detecting the synchronization state of the first synchronization signal and the synchronization test signal. The first synchronization signal may be sampled with an internal clock signal to obtain a second sampled signal. The second sampling signal is synchronized with the synchronization test signal to obtain a second synchronization signal. And sampling the second synchronous signal by using an internal clock signal to obtain a third sampling signal, wherein the third sampling signal is the synchronous test signal. The synchronization state is determined using the second sampling signal and the synchronization test signal.
And S23, outputting a first synchronization signal when the synchronization state is synchronous. The first synchronization signal can be output by using the synchronization signal output module, and the first synchronization signal can be output to a digital-to-analog converter or an FPGA chip in practical application.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (14)
1. A clock signal recovery circuit for use in a digital to analog converter, the clock signal recovery circuit comprising: the latch is used for receiving a digital signal and sampling the digital signal by using a sampling clock signal to obtain a digital signal sample;
the input end of the phase discriminator is in communication connection with the output end of the latch and is used for obtaining a signal containing a phase error according to the phase difference between the digital signal sample and the internal clock signal; the internal clock signal is a clock signal of the digital-to-analog converter;
the input end of the decoder is in communication connection with the output end of the phase discriminator and is used for converting the signal containing the phase error into a control signal;
a phase adjuster having an input communicatively coupled to the output of the decoder and an output communicatively coupled to the input of the latch; the phase adjuster is used for adjusting the phase of the sampling clock signal according to the control signal to obtain the adjusted sampling clock signal; and when the adjusted sampling clock signal is synchronous with the digital signal, obtaining a clock recovery signal.
2. The clock signal recovery circuit of claim 1, wherein the phase detector is further configured to convert the digital signal samples into a binary code, the binary code being configured to characterize phase information of the digital signal samples.
3. The clock signal recovery circuit of claim 2, wherein the control signal is a binary code control signal.
4. The clock signal recovery circuit of any of claims 1 to 3, wherein the clock recovery signal is synchronized with the internal clock signal.
5. A clock signal recovery method applied to the clock signal recovery circuit according to any one of claims 1 to 4, the clock signal recovery method comprising:
acquiring a digital signal, and sampling the digital signal by using a sampling clock signal to obtain a digital signal sample;
obtaining a signal containing a phase error according to a phase difference between the digital signal sample and an internal clock signal; the internal clock signal is a clock signal of the digital-to-analog converter;
converting the signal containing the phase error into a control signal;
adjusting the phase of the sampling clock signal by using the control signal to obtain an adjusted sampling clock signal; and when the adjusted sampling clock signal is synchronous with the digital signal, obtaining a clock recovery signal.
6. The clock signal recovery method of claim 5, wherein said obtaining a signal containing a phase error based on a phase difference between the digital signal samples and an internal clock signal comprises:
converting the digital signal samples into binary codes, the binary codes being used to characterize phase information of the digital signal samples;
the signal containing the phase error is obtained from a phase difference between the binary code and an internal clock signal.
7. An interface circuit, comprising: the device comprises a signal sampling module, a signal synchronization module, a synchronization detection module and a synchronization signal output module;
the signal sampling module comprises a clock recovery circuit, and the clock recovery circuit is used for sampling a digital signal to obtain a first sampling signal; the clock recovery circuit is the clock signal recovery circuit of any one of claims 1 to 4;
the signal synchronization module is in communication connection with the signal sampling module and is used for synchronizing the first sampling signal with a test signal to obtain a first synchronization signal;
the synchronous detection module is in communication connection with the signal synchronization module and is used for detecting the synchronous state of the first synchronous signal and the synchronous test signal;
the synchronous signal output module is respectively in communication connection with the signal synchronous module and the synchronous detection module; and when the synchronous detection module detects that the synchronous detection module is synchronous, the synchronous signal output module outputs the first synchronous signal.
8. The interface circuit of claim 7, wherein the signal sampling module further comprises a first flip-flop communicatively coupled to the clock recovery circuit, the first flip-flop receiving the digital signal and sampling the digital signal with the clock recovery signal to obtain the first sampled signal.
9. The interface circuit of claim 8, wherein the signal synchronization module comprises a signal memory, and a first exclusive-or logic gate communicatively coupled to the signal memory; the input end of the signal memory is in communication connection with the output end of the first trigger;
the signal memory is used for synchronizing the first sampling signal with an internal clock signal;
the first exclusive or logic gate is configured to synchronize the test signal with the first sampling signal synchronized with the internal clock signal to obtain the first synchronization signal.
10. The interface circuit of claim 9, wherein the sync detection module comprises a second flip-flop, a second exclusive-or logic gate, and a third flip-flop; an input of the second flip-flop is communicatively coupled to an output of the first exclusive-or logic gate, and an output of the second flip-flop is communicatively coupled to an input of the second exclusive-or logic gate; the output end of the second exclusive-or logic gate is in communication connection with the input end of the third flip-flop, and the output end of the third flip-flop is in communication connection with the input end of the second exclusive-or logic gate;
the second trigger is used for receiving the first synchronous signal and sampling the first synchronous signal by using the internal clock signal to obtain a second sampling signal;
the second exclusive-or logic gate is used for synchronizing the second sampling signal with a synchronous test signal to obtain a second synchronous signal;
the third flip-flop is configured to receive the second synchronization signal and sample the second synchronization signal by using the internal clock signal to obtain a third sampling signal; the third sampling signal is the synchronous test signal;
when the output of the second exclusive-or logic gate is 0, the second sampling signal and the synchronous test signal are synchronized;
when the output of the second exclusive-or logic gate is 1, the second sampling signal is not synchronized with the synchronous test signal.
11. The interface circuit of claim 10, wherein the synchronization signal output module comprises a selection logic gate communicatively coupled to an output of the second flip-flop;
when the second sampling signal and the synchronous test signal are synchronized, the selection logic gate is set to be 1 so as to output the first synchronous signal;
when the second sampling signal and the synchronous test signal are not synchronized, the selection logic gate is set to be 0, and no first synchronous signal is output.
12. A signal synchronization method applied to the interface circuit according to any one of claims 7 to 11; the signal synchronization method comprises the following steps:
providing a clock recovery signal, and sampling a digital signal by using the clock recovery signal to obtain a first sampling signal;
providing a test signal, and synchronizing the first sampling signal with the test signal to obtain a first synchronization signal;
detecting the synchronization state of the first synchronization signal and the synchronization test signal;
and when the synchronization state is synchronization, outputting the first synchronization signal.
13. The signal synchronization method of claim 12, wherein after obtaining the first sampling signal, providing the test signal, synchronizing the first sampling signal with the test signal, and before obtaining the first synchronization signal, the signal synchronization method further comprises:
synchronizing the first sampling signal with an internal clock signal.
14. The signal synchronization method of claim 12, wherein the detecting the synchronization status of the first synchronization signal and a synchronization test signal comprises:
sampling the first synchronization signal with the internal clock signal to obtain a second sampled signal;
synchronizing the second sampling signal with a synchronous test signal to obtain a second synchronous signal;
sampling the second synchronous signal by using the internal clock signal to obtain a third sampling signal, wherein the third sampling signal is the synchronous test signal;
a synchronization state is determined using the second sampling signal and the synchronization test signal.
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