CN111415992B - Shielding gate MOSFET device and preparation method thereof - Google Patents

Shielding gate MOSFET device and preparation method thereof Download PDF

Info

Publication number
CN111415992B
CN111415992B CN202010310099.0A CN202010310099A CN111415992B CN 111415992 B CN111415992 B CN 111415992B CN 202010310099 A CN202010310099 A CN 202010310099A CN 111415992 B CN111415992 B CN 111415992B
Authority
CN
China
Prior art keywords
type
groove
trench
grooves
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010310099.0A
Other languages
Chinese (zh)
Other versions
CN111415992A (en
Inventor
单建安
梁嘉进
伍震威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anjian Technology Shenzhen Co ltd
Original Assignee
Anjian Technology Shenzhen Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anjian Technology Shenzhen Co ltd filed Critical Anjian Technology Shenzhen Co ltd
Priority to CN202010310099.0A priority Critical patent/CN111415992B/en
Publication of CN111415992A publication Critical patent/CN111415992A/en
Application granted granted Critical
Publication of CN111415992B publication Critical patent/CN111415992B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a shielded gate MOSFET device and a preparation method thereof, relates to a power semiconductor device, and provides the following technical scheme for solving the problems of complicated preparation method and higher cost of the traditional shielded gate groove type field effect transistor device: the epitaxial layer is provided with more than one parallel series of grooves, the series of grooves is composed of a first type of grooves and/or a second type of grooves which are connected with each other, the series of grooves are connected through horizontal grooves with different forms of design, and more than one third type of grooves surrounding the series of grooves are arranged on the periphery of the series of grooves. The invention provides a shielded gate trench field effect transistor device which has a unique structure and a unique manufacturing process flow.

Description

Shielding gate MOSFET device and preparation method thereof
Technical Field
The invention relates to a power semiconductor device, in particular to a structure of a shielded gate trench field effect transistor device and a manufacturing method thereof.
Background
The shielded gate groove type field effect transistor as a novel power device has the characteristics of low on-resistance and high switching speed. The structure of the shielded gate trench field effect transistor is characterized in that a gate electrode and a shielded gate electrode which are mutually isolated are arranged in a trench, wherein the shielded gate electrode is positioned below the gate electrode and needs to be connected to an upper surface metal. As in the solution provided in US7005351, six to eight photolithography steps are required for the whole process flow, usually in the formation of P-body doped regions and N+When the source doping region is used, the photolithography process is performed by using a photolithography mask, which is expensive, and a manufacturing process for reducing the photolithography process is necessary to save the cost.
Disclosure of Invention
In view of the above-mentioned problems of the conventional shielded gate trench fet, there is a need to provide a shielded gate trench fet with a simple process and a low manufacturing cost, and a process flow thereof.
It is an object of the present invention to provide a shielded gate MOSFET device, said MOSFET device comprising:
the lower surface metal at the bottom of the device,
a first conductivity type base layer over the bottom surface metal;
an epitaxial layer of a first conductivity type located over a substrate layer of the first conductivity type;
the epitaxial layer of the first conduction type is provided with more than one series of parallel grooves in the epitaxial layer of the first conduction type, and a doped body region of the second conduction type and a doped source region of the first conduction type which are positioned on the upper surface of the epitaxial layer of the first conduction type;
an oxide dielectric layer located over the series of trenches;
the upper surface metal is positioned above the oxide dielectric layer;
it is characterized in that the preparation method is characterized in that,
the outermost series of trenches is constituted by trenches of a first type;
the other series of grooves positioned in the outermost series of grooves are composed of more than one section of first-type grooves and second-type grooves which are mutually connected, the tail ends of the series of grooves are the first-type grooves, at least one horizontal groove which is the same as the first-type grooves connects the first-type grooves at the tail ends of all the series of grooves, and the second-type grooves in the adjacent series of grooves are arranged in a staggered mode;
more than one third type of grooves surrounding all the series of grooves are arranged at the outermost periphery of all the series of grooves;
the first type of groove is used for forming a conducting area, and a gate electrode and a shielding gate electrode are arranged in the groove;
the second type of groove is used for connecting the shielding gate electrode and the upper surface metal layer, and only the shielding gate electrode is arranged in the groove without the gate electrode;
the third type of groove is used for preventing the periphery of the device from being broken down, only the shielding gate electrode is arranged in the groove without the gate electrode, and the shielding gate electrode in at least one section of the second type of groove and the shielding gate electrode in at least one section of the first type of groove are connected with each other and then are finally connected to the upper surface metal.
Preferably, the shield gate electrode in the second type trench and the third type trench is connected to the top surface metal through a via hole located on the oxide dielectric layer.
Preferably, the shield gate electrode and the gate electrode in the first-type trench are separated by an inter-electrode spacer;
and/or
The shield gate electrode and the gate electrode are isolated from the corresponding trench sidewalls by a trench oxide layer.
Preferably, the inter-electrode isolation layer is made of a semiconductor oxide, a semiconductor nitride and/or an insulating dielectric material.
Preferably, a mask dielectric layer is arranged on the periphery of the third type of groove and is positioned on the upper surface of the semiconductor.
Preferably, the through hole is in a shape with a large width at the top and a small width at the bottom.
Preferably, the third type of groove comprises a vertical section groove and a transverse section groove which are connected.
Preferably, the distance between the vertical section groove of the third type groove and the adjacent series groove in the horizontal direction is equal to the horizontal distance between any two parallel series grooves and equal to the vertical distance between the horizontal section groove of the third type groove and the adjacent horizontal groove.
Preferably, a doped contact region of the second conductivity type is further disposed in the doped body region of the second conductivity type.
Preferably, the third type of trench is wider and deeper than the series of trenches in width and depth.
As one embodiment, more than one fifth trench arranged horizontally is further provided in the epitaxial layer of the first conductivity type, the fifth trench is a first-type trench, and the gate electrode in the fifth trench and the gate electrode in the first-type trench in the same horizontal position in the series of trenches are connected to each other, and the number of the fifth trenches may be one or two or three, and so on.
As an embodiment, the distance between the third type of trenches is equal to the distance between the third type of trench closest to the series of trenches and its adjacent series of trenches.
In one embodiment, the horizontal grooves are fourth grooves connecting the first grooves at the ends of all the series of grooves.
As an embodiment, the horizontal groove is an eighth groove, and the first-type grooves at the tail ends of any two adjacent series of grooves are connected with the eighth groove to form a first inner ring groove;
a first outer ring groove is arranged between every two adjacent first inner ring grooves, the first outer ring groove comprises a series of grooves and a seventh groove which connects the corresponding series of grooves to a transverse section groove of a third type of groove, and the seventh groove is a second type of groove; and the vertical section groove of the peripheral third type groove is adjacent to an inner ring groove.
As one embodiment, the horizontal groove is a ninth groove, the first-type grooves at the ends of two series of grooves which are separated from each other are connected through the ninth groove to form a second inner-ring groove, the two series of grooves are separated from each other through a first-ring groove, and the end of the first-ring groove is the first-type groove;
and a second outer ring groove is arranged between every two adjacent second inner ring grooves, the second outer ring groove comprises a series of grooves and a tenth groove which connects the corresponding series of grooves to the transverse section groove of the third type of groove, and the tenth groove is the second type of groove.
Another object of the present invention is to provide a method for manufacturing a shielded gate MOSFET device, the method comprising the steps of:
the first step is as follows: providing a first conductive type substrate and forming a first conductive type epitaxial layer on the first conductive type substrate;
secondly, forming a series of grooves on the epitaxial layer of the first conduction type;
thirdly, forming a trench oxide layer and a shielding gate electrode in the trench;
fourthly, forming a first dielectric layer on the upper surface of the semiconductor, and then forming a second dielectric layer on the first dielectric layer, wherein the etching rates of materials forming the first dielectric layer and the second dielectric layer are different;
fifthly, forming photoresist on the upper surfaces of the second type groove and the third type groove, and carrying out back etching under the protection of the photoresist to expose the shielding gate electrode in the groove; the boundary of the etched first medium layer is positioned between the second-type groove or the third-type groove and the second-type groove;
and sixthly, etching back the shielding gate electrode and the groove oxide layer, and removing the photoresist.
Seventhly, etching the first dielectric layer to enable the horizontal boundary of the first dielectric layer to shrink inwards; the first dielectric layer which is finally formed after etching and covers the periphery of the third type of groove is a mask dielectric layer;
eighthly, forming an inter-electrode isolation layer on the upper surface of the shielding gate electrode, and forming a gate oxide layer on the side wall of the groove at the upper part;
a ninth step of forming a gate electrode;
tenth step, using the mask dielectric layer as a hard mask to perform ion implantation, wherein the ion implantation at least comprises ion implantation of a second conductive type, and the formation of the doped body region of the second conductive type further comprises ion implantation of a first conductive type to form a type doped source region of the first conductive type;
a tenth step of forming an oxide dielectric layer on the upper surface of the semiconductor, and then forming a through hole on the oxide dielectric layer;
and a twelfth step of forming an upper surface metal on the upper surface of the semiconductor and a lower surface metal under the semiconductor substrate.
Preferably, the materials of the first dielectric layer and the second dielectric layer are oxides, nitrides, polysilicon and/or organic polymers with different components.
Preferably, the material constituting the first dielectric layer is silicon nitride, and the material constituting the second dielectric layer is silicon oxide.
Preferably, the material forming the first dielectric layer is polysilicon, and the material forming the second dielectric layer is silicon oxide.
Preferably, in the sixth step, in order to prevent the horizontal boundary from shrinking inward due to the fact that the first dielectric layer or the second dielectric layer is etched transversely in the etching-back process, before etching-back is performed, a sidewall protection layer is formed in advance on the interface of the horizontal boundary of the second dielectric layer and/or the first dielectric layer, and the sidewall protection layer is removed after etching is completed.
Preferably, an oxidation sacrificial layer is formed in advance before the first dielectric layer is etched, so that the exposed side wall of the trench, the shield gate electrode in the trench and the upper surface of the semiconductor are protected.
Preferably, in the tenth step, after the through hole is etched, one or more steps of ion implantation of the second conductivity type are performed to form a doped contact region of the second conductivity type in the doped body region of the second conductivity type.
As an example, the step of forming the inter-electrode isolation layer and the step of forming the gate oxide layer in the eighth step may be:
firstly, forming a filling oxide covering a groove through chemical vapor deposition, and etching the filling oxide back to enable the upper surface of the filling oxide to be positioned in the groove;
secondly, forming photoresist on the second type of groove and the third type of groove, and etching back the oxide under the protection of the photoresist to form an inter-electrode isolation layer;
and thirdly, forming a gate oxide layer through thermal oxidation or deposition.
As an embodiment, the step of forming the inter-electrode isolation layer and the step of forming the gate oxide layer in the eighth step may further be:
firstly, depositing nitride in a groove and carrying out dry etching on the nitride in the vertical direction to form a nitride protective layer covering the side wall of the groove and a nitride protective layer covering the side walls of a first dielectric layer and a second dielectric layer, and exposing a shield gate electrode in the groove;
secondly, carrying out thermal oxidation to form an inter-electrode isolation layer on the upper surface of the shielding gate electrode;
thirdly, removing the nitride protection layer on the side wall of the groove;
and fourthly, forming a gate oxide layer by thermal oxidation or deposition.
The shielding grid groove type field effect transistor device provided by the invention has a unique structure and a manufacturing process flow. Compared with the traditional structure and process, one to two photoetching steps can be saved, and the manufacturing cost is effectively reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a shielded gate trench fet according to an embodiment of the present invention, and corresponds to a cut line a-a' in fig. 2.
Fig. 2 is a partial top view of a trench structure in one embodiment of a shielded gate trench fet of the present invention.
Fig. 3-6 are partial top views of trench structures in further embodiments of shielded gate trench fets in accordance with the present invention.
Fig. 7-20 are schematic cross-sectional views of the process flow of steps of one embodiment of the shielded gate trench fet of the present invention.
Fig. 21 and 22 are schematic cross-sectional views illustrating another implementation method of the eighth step in an embodiment of the shielded gate trench fet of the present invention.
Fig. 23 and 24 are schematic cross-sectional views illustrating another implementation method of the eighth step in an embodiment of the shielded gate trench fet of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples. It is to be noted that in the following description of the shielded gate trench field effect device and the method of manufacturing the same of the present invention, the semiconductor substrate of the shielded gate trench field effect device is considered to be composed of a silicon (Si) material. However, the substrate may be made of any other material suitable for manufacturing the shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity types of a semiconductor region are divided into P-type (second conductivity type) and N-type (first conductivity type), and a semiconductor region of one P-type conductivity type may be formed by doping an original semiconductor region with one or more impurities, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. An N-type conductive semiconductor regionMay be formed by doping the original semiconductor region with one or more impurities which may be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H)+) And the like. In the following description, the heavily doped P-type conductive semiconductor region is labeled as P+Region, the heavily doped N-type conductive semiconductor region being labeled N+And (4) a zone. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is typically 1 × 10, unless otherwise specified19cm-3To 1X 1021 cm-3In the meantime. It should be understood by those skilled in the art that the P-type (second conductivity type) and the N-type (first conductivity type) can be interchanged according to the present invention.
Fig. 1 and 2 illustrate an embodiment of the present invention. Fig. 1 is a partial cross-sectional view of the embodiment. Fig. 2 is a partial top view of the trench structure of this embodiment. The cut line A-A' in FIG. 2 corresponds to the cross-sectional structure in FIG. 1. Fig. 1 and 2 are described below, respectively:
fig. 1 is a schematic cross-sectional view of one embodiment of a shielded gate trench field effect device of the present invention. Which comprises the following steps:
n on the lower surface metal (220)+A patterned substrate layer (200).
At N+An N-type epitaxial layer (201) over the type substrate layer (200).
In the N-type epitaxial layer (201), there are multiple trenches (250, 251, 252). The depth of the trench is 1-6.5 μm, with the particular depth being related to the breakdown voltage of the device, e.g., about 1-2.8 μm in one device embodiment with a breakdown voltage of about 35V. The trenches may be large-bottom-small in shape with a trench-to-trench spacing of 0.3-3 μm.
The trenches contain mutually isolated gate electrodes (205) and/or shield gate electrodes (203) depending on the role that the trenches (250, 251, 252) play. The gate electrode (205) and the shield gate electrode (203) are typically formed of polysilicon, and may be formed of a metal, a metal-semiconductor compound (e.g., Al, Ti, W, etc.), or a combination thereof.
The shield gate electrode (203) is isolated from the corresponding trench sidewalls by a trench oxide layer (202). In a specific application, the thickness of the trench oxide layer (202) is related to the breakdown voltage of the device, for example, in a device embodiment with a breakdown voltage of about 65V, the thickness of the trench oxide layer (202) is 2000-4000A.
The trenches (250, 251, 252) are divided into a first type trench (250), a second type trench (251) and a third type trench (252), wherein the first type trench (250) is used for forming a conducting region; the second type of groove (251) is used for connecting the shielding grid electrode (203) and the upper surface metal layer (209); the third type of trench (252) is used to guarantee the breakdown voltage at the periphery of the device.
The three types of grooves respectively have the following structural characteristics:
in the first trench type (250), the shield gate electrode (203) is located below the gate electrode (205) and separated from each other by an inter-electrode spacer (204). The inter-electrode isolation layer (204) may be made of a semiconductor oxide, a semiconductor nitride, or other insulating dielectric material, or may be made of a combination of the above materials. In one embodiment, the inter-electrode isolation layer (204) is comprised of an oxide with a thickness of 200-4000A at its thinnest. In the first type of trench (250), the gate electrode (205) is isolated from the corresponding trench sidewall by the gate oxide layer (210). In one embodiment, the gate oxide layer (210) is 150A thick and 1000A thick. In one embodiment, the height of the gate electrode is 0.4-1.1 μm. In a specific embodiment, the distance from the upper surface of the gate electrode to the upper surface of the semiconductor is 0-0.5 μm.
In the second type trench 251 and the third type trench 252, only the shield gate electrode 203 is provided in the trenches without the gate electrode 205, and the upper surface of the shield gate electrode 203 is located at the upper portion of the trenches. In a specific embodiment, the height of the upper surface of the shield gate electrode (203) in the second type of trench (251) and the third type of trench (252) is the same as the height of the upper surface of the gate electrode (205) in the first type of trench (250). In a specific embodiment, the upper surface height is from 0 to 0.4 μm from the upper surface of the semiconductor. In the second type of trench (251) and the third type of trench (252), the shield gate electrode (203) in the trench is connected with the upper surface metal (209) through a through hole (207) on the oxide dielectric layer (206). The top surface metal (209) is typically composed of Al or Al compounds, e.g., Al/Cu, Al/Si/Cu. In one embodiment, the top surface metal is composed of 98% Al and 2% Cu. In addition, in the via hole (207), a diffusion barrier metal may be filled with a composition of a metal such as Ti, W or the like or a metal compound thereof, for example, TiSi, TiN or the like.
At least one shield gate electrode (203) in a section of the second type trench (251) is interconnected with a shield gate electrode (203) in a section of the first type trench (250) and is ultimately connected to the top surface metal (209).
The second type of groove (251) is located between two sections of the first type of groove (250) in the horizontal direction.
The third type of groove (252) is located at the outermost periphery of the multi-section grooves, and the adjacent grooves are the first type of grooves (250).
The periphery of the third type of trench 252 may have a masking dielectric layer 219 overlying the semiconductor top surface. The shield gate electrode (203) and the masking dielectric layer (219) in the third type of trench (252) may be in direct contact with each other or may be separated from each other by an isolation layer (218). The isolation layer (218) is typically an oxide.
In addition, the width and depth of the first type groove (250), the second type groove (251) and the third type groove (252) can be the same or different.
The device structure at least also comprises a P-type doped body region (216) and an N-type doped body region which are positioned between the trenches and on the upper surface of the semiconductor epitaxial layer (201)+And (7) forming a type doping source region (215).
Fig. 2 is a partial top view of the trench structure of the shielded gate trench field effect device of fig. 1.
Wherein, on the semiconductor plane, a plurality of series of parallel grooves (240) are arranged along the vertical direction. Each series of grooves (240) consists of a first type of groove (250) and a second type of groove (251) which are vertically connected with each other, and wherein each of the first type of groove (250) and the second type of groove (251) may have a plurality of sections. Typically, in one series of trenches (240), the total length of the second type of trench (251) portion is less than the total length of the first type of trench (250).
The vertical ends of the series of grooves (240) are of a first type (250) and there is a horizontal fourth groove (253) connecting the ends (ends) of the series of grooves (240) together. The fourth trench (253) is a first-type trench (250).
Of the series of grooves (240), the second-type grooves (251) adjacent to each other on the left and right are vertically offset (offset from each other). Therefore, the second-type groove (251) is in the horizontal direction, and the left and right adjacent grooves are the first-type grooves (250). Furthermore, in the horizontal direction, the outermost peripheral groove of the series of grooves (240) is a whole segment of the first-type groove (250).
In addition, a third type of groove (252) surrounds the inner series of grooves (240) outside the series of grooves (240). The third type of grooves (252) comprise vertical section grooves and horizontal section grooves, the vertical section grooves are parallel to the series of grooves (240), the horizontal section grooves are perpendicular to the series of grooves (240), and the angle formed by the intersection of the vertical section grooves and the horizontal section grooves is equal to ninety degrees, as shown in FIG. 2; the two grooves may be connected by a corner groove, the corner groove is formed by connecting more than one straight groove, namely the corner groove may also be formed by multiple straight grooves, and the obtuse angle between the adjacent straight lines is greater than 90 degrees, when the number of the straight lines is infinite, the corner groove is an arc groove.
In one embodiment, as shown in fig. 2, the distance D1 between the vertical segment of the third kind of groove (252) and the adjacent series of grooves (240) in the horizontal direction is equal to the distance D2 between any two adjacent series of grooves (240) in the horizontal direction, and is equal to the vertical distance H1 between the horizontal segment of the third kind of groove (252) and the fourth groove (253).
In one embodiment, the third type of trench (252) is wider and deeper than the inner series of trenches (240), respectively. In a specific embodiment, the depth of the third type of trench (252) is 2.4 μm and the depth of the series of trenches (240) inside it is 2 μm.
Furthermore, there may be a masking dielectric layer (219) located in the third type of trench (252) and at the periphery of the trench. Wherein the boundary (270) of the masking dielectric layer (219) is located above the third type trench (252).
The trench structure of the shielded gate trench fet described in the present invention is not limited to the trench structure shown in fig. 2. The following description will be made with reference to more embodiments:
fig. 3 is a top view of a portion of a trench structure of an alternate embodiment of the shielded gate trench fet device of fig. 2. Wherein a fifth groove (254) in the horizontal direction having a minimum length is provided in the series of grooves (240) and connects the plurality of series of grooves (240) together. In one embodiment, the fifth trench (254) is a first type trench (250) and connects segments of the first type trench (250) in the series of trenches (240) together. The gate electrodes (205) within the first-type trenches (250) and the fifth trenches (254) are interconnected together, and the shield gate electrodes (203) within the first-type trenches (250) and the fifth trenches (254) are interconnected together. In one embodiment, the width and depth of the fifth trench (254) is the same as the width and depth of the first type of trench (250) in the series of trenches (240).
Fig. 4 is a top view of a portion of a trench structure of an alternate embodiment of the shielded gate trench fet device of fig. 2. Wherein, at the periphery of the third type groove (252) surrounding the series of grooves (240), a sixth groove (255) with at least one section is further arranged, and the sixth groove (255) surrounds the third type groove (252). In one embodiment, the sixth trench (255) and the third type trench (252) have the same width and depth and the same internal structure. In one embodiment, the distance D3 from the sixth trench (255) to the third type of trench (252) is equal to the distance D1 from the third type of trench (252) to the adjacent series of trenches (240).
Figure 5 is a partial top view of a trench structure according to an alternative embodiment of the present invention.
Wherein, on the semiconductor plane, a plurality of series of parallel grooves (240) are arranged along the vertical direction. Each series of grooves (240) is composed of a first type of groove (250) and a second type of groove (251) which are mutually connected in the vertical direction, wherein each of the first type of groove (250) and the second type of groove (251) can have a plurality of sections. Located outside the series of grooves (240), there is a section of a third type of groove (252) surrounding the inner series of grooves (240). The third type of grooves (252) comprise vertical section grooves and transverse section grooves, the vertical section grooves are parallel to the series of grooves (240), and the transverse section grooves are perpendicular to the series of grooves (240).
The series of grooves (240) may be divided into a first inner ring groove (258) and a first outer ring groove (259) according to a vertical direction end-to-end connection method. The first inner ring groove (258) is provided with a first type groove (250) at the end, and the first inner ring groove (258) is composed of two adjacent series grooves (240) and an eighth groove (257) which connects the two adjacent series grooves (240) and is in the horizontal direction. The eighth groove (257) is a first-type groove (250). The first outer ring of grooves (259) is formed by a series of grooves (240) and a seventh groove (256) at the extreme end of the series of grooves (240), the seventh groove (256) connecting the corresponding series of grooves (240) to the transverse segment grooves of the third type of grooves (252), the seventh groove (256) being the second type of groove (251).
The series of grooves (240) are arranged periodically in the horizontal direction in the order of the first inner ring grooves (258) to the first outer ring grooves (259). The outermost periphery in the horizontal direction is a first inner ring groove (258), and the series of grooves (240) in the first inner ring groove (258) adjacent to the third type of grooves (252) is a whole section of the first type of grooves (250).
The vertical distance H2 from the eighth groove 257 to the transverse segment of the third groove 252 is equal to the horizontal distance D2 between any adjacent two series of grooves 240.
Of the series of grooves (240), the second-type grooves (251) adjacent to each other on the left and right are vertically offset. Therefore, the second-type groove (251) is in the horizontal direction, and the left and right adjacent grooves are the first-type grooves (250).
In the groove, the connection formed by the horizontal section and the vertical section may be a right angle or an arc corner.
Figure 6 is a partial top view of a trench structure according to an alternative embodiment of the present invention.
Wherein, on the semiconductor plane, a plurality of series of parallel grooves (240) are arranged along the vertical direction. Each series of grooves (240) consists of a first type of groove (250) and a second type of groove (251) which are vertically interconnected. Wherein, the first type groove (250) and the second type groove (251) can have a plurality of sections. Located outside the series of grooves (240), there is a section of a third type of groove (252) surrounding the inner series of grooves (240). The third type of grooves (252) comprise vertical section grooves and transverse section grooves, the vertical section grooves are parallel to the series of grooves (240), and the transverse section grooves are perpendicular to the series of grooves (240).
The series of grooves (240) can be divided into: a first ring groove (261), a second inner ring groove (262), and a second outer ring groove (263). Wherein the first ring of grooves (261) end with the first type of grooves (250). The second inner ring groove (262) is provided with a first type groove (250) at the end, the second inner ring groove (262) is formed by connecting two series of grooves (240) through a section of ninth groove (260) in the horizontal direction, and the first ring groove (261) is positioned in and surrounded by the second inner ring groove (262). The ninth trench (260) is the first trench (250). The second outer ring grooves (263) are composed of a series of grooves (240) and tenth grooves (264) which are positioned at the extreme ends of the series of grooves (240), the tenth grooves (264) connect the corresponding series of grooves (240) to the transverse section grooves of the third type of grooves (252), every two adjacent second outer ring grooves (263) surround one second inner ring groove (262), namely, a second outer ring groove (263) is arranged between every two adjacent second inner ring grooves (262). The tenth trench (264) is a second type trench (251).
The series of grooves (240) are arranged periodically in the horizontal direction in the order of the second inner ring groove (262) -the second outer ring groove (263). The series of grooves (240) at the outermost periphery in the horizontal direction is a second inner ring groove (262), and the series of grooves (240) adjacent to the third type of grooves (252) in the second inner ring groove (262) is a whole segment of the first type of grooves (250).
The distance H3 from the vertical end of the first ring of grooves (261) to the ninth groove (260) is equal to the vertical distance H4 from the ninth groove (260) to the horizontal section of the third groove (252), and is equal to the horizontal distance D2 between two adjacent series of grooves (240).
Of the series of grooves (240), the second-type grooves (251) adjacent to each other on the left and right are vertically offset. Therefore, the second-type groove (251) is in the horizontal direction, and the left and right adjacent grooves are the first-type grooves (250).
In the groove, the connection formed by the horizontal section and the vertical section may be a right angle or an arc corner.
The above described variations of the embodiments of the trench structure in fig. 2-6 can be combined with each other to achieve further variations of embodiments of the present invention. For example, the upper and lower ends of the trench in the vertical direction use the structure of fig. 5 for the upper end and the structure of fig. 6 for the lower end. The common point of the above-mentioned trench structure embodiments in fig. 2-6 is that the trenches adjacent to the second type trench (251) in the series of trenches (240) in the horizontal direction are the first type trenches (250). The structural feature can achieve the purpose of simplifying the device manufacturing process flow.
The following describes the manufacturing process steps of the above-described shielded gate trench field effect transistor device:
first, providing N+A type substrate (200) and an N type epitaxial layer (201) formed thereon.
Wherein N is+The substrate (200) may be doped with red phosphorus or arsenic to a thickness of between 50-1500 um. In a specific embodiment, N+The substrate is doped with red phosphorus with a doping concentration of 1e20 cm-3To 1e18 cm-3To (c) to (d);
the N-type epitaxial layer may be doped with phosphorus and has a thickness of between 0.5 and 15 μm. The doping concentration of the N-type epitaxial layer may be fixed. In one embodiment, the N-type epitaxial layer is doped with phosphorus at a doping concentration of 5e17 cm-3To 1e16 cm-3And the thickness is between 1 and 5 mu m. The doping concentration of the N-type epitaxial layer may also have different doping concentrations with different depths. In one embodiment, the doping concentration is distributed with a top-to-bottom concentration in the N-type epitaxial layer. Wherein the doping concentration is 5e17 cm at the lightest part-3To 1e16 cm-3Middle, most concentrated at 5e17 cm-3To 1e18 cm-3In the meantime.
In a second step, a series of trenches (250, 251, 252) are formed in the N-type epitaxial layer (201), as shown in fig. 7.
Before the formation of the trench, it may be necessary to form a hard mask (301) on the upper surface of the epitaxial layer in advance by photolithography, and the hard mask (301) may be a semiconductor oxide or nitride, or a combination of the two. In one embodiment, the hard mask (301) is an insulator assembly, which is, from bottom to top: silicon oxide (100-1000A), silicon nitride (1000-3000A), silicon oxide (2000-3000A). In another embodiment, the hard mask (301) is silicon oxide (1500-.
The trench may be formed by dry etching. In one embodiment, the trench may be formed by thermal ion etching. The etched trench may have a shape with a large top and a small bottom. In a specific embodiment, the width of the trench on the semiconductor upper surface is 0.2-0.5um and the depth of the trench is 1-2.8 μm. In another embodiment, the width of the trench on the semiconductor upper surface is 0.5-1.5um and the depth of the trench is 2.5-6 μm.
Third, a trench oxide layer (202) is formed in the trench, and a shield gate electrode (203) is formed in the trench, as shown in fig. 8.
The trench oxide layer 202 is an oxide and may be formed by thermal oxidation or deposition, or a combination thereof. In one embodiment, the trench oxide layer (202) is formed by: the 200-2500A oxide is formed by thermal oxidation, and then the 200-4000A oxide is formed on the oxide formed by thermal oxidation by chemical vapor deposition.
The oxide layer having the same composition may be formed on the upper surface of the semiconductor at the same time as the trench oxide layer is formed. The oxide layer may be completely removed or partially removed.
The shield gate electrode (203) is typically polysilicon and may also be comprised of a metal, a metal-semiconductor compound (e.g., Al, Ti, W, etc.), and combinations thereof. The method of forming the shield gate electrode (203) may be: the shield gate electrode material is first deposited and etched back to the upper portion of the trench. In a specific embodiment, the shield gate electrode is made of polysilicon, wet etching or dry etching is used for back etching, and the distance from the height of the upper surface of the shield gate electrode (203) to the upper surface of the semiconductor epitaxial layer (201) after back etching is 0.1-0.5 μm.
Fourthly, a first dielectric layer (501) is formed on the upper surface of the semiconductor, and a second dielectric layer (502) is formed on the first dielectric layer (501), as shown in fig. 9.
The first dielectric layer (501) and the second dielectric layer (502) are composed of two materials with different etching rates, wherein the materials can be oxide, nitride, polysilicon, organic polymer or the combination of the materials. For example, one possible combination is: the first dielectric layer (501) is silicon nitride, and the second dielectric layer (502) is silicon oxide; another possible combination is: the first dielectric layer (501) is polysilicon and the second dielectric layer (502) is silicon oxide.
The first dielectric layer (501) and the second dielectric layer (502) may be formed by different deposition steps. Wherein the thickness of the first dielectric layer (501) is between 1000A and 8000A. The second dielectric layer (502) has a thickness of between 500A and 5000A.
The shield gate electrode (203) and the first dielectric layer (501) in the trench may be directly connected together or may be separated by an isolation layer (218). The isolation layer (218) may be an oxide and may be formed by thermal oxidation or deposition to a thickness of between 100A-1000A prior to formation of the first dielectric layer (501).
In one embodiment, a 500A thickness oxide is first formed as an isolation layer (218) on the top surface of the shield gate electrode (203) in the trench by thermal oxidation, and 1000-4000A silicon nitride is then formed thereon by chemical vapor deposition as a first dielectric layer (501), and 1000A-3000A silicon oxide is then formed by chemical vapor deposition as a second dielectric layer (502).
Fifthly, forming photoresist (601) on the upper surfaces of the second type of groove (251) and the third type of groove (252), and carrying out back etching under the protection of the photoresist (601) to expose the shielding gate electrode (203) in the groove. As shown in fig. 10.
The etching back comprises multi-step etching, wherein the method for etching the first dielectric layer (501) and the second dielectric layer (502) can be dry etching. And the boundary of the etched first dielectric layer (501) is positioned between the second-type groove (251) or the third-type groove (252) and the second-type groove (250). The boundary is horizontally spaced from the corresponding second-type groove (251) or third-type groove (252) by a distance of between 0.05um and 1 um. In a specific embodiment, the distance is 0.1-0.3 um.
Sixthly, etching back the shielding gate electrode (203) and the trench oxide layer (202), and removing the photoresist. As shown in fig. 11.
The sequence of etching back the shield gate electrode (203) and the trench oxide layer (202) may be: the shield gate electrode is etched back first (203) and then the trench oxide layer is etched back (202). It is also possible to include multiple alternating etchback steps, such as: the shield gate electrode 203 is etched back to one depth first, then the trench oxide 202 is etched back to another depth, and then the shield gate electrode 203 is etched back to yet another depth. The distance from the upper surface of the final shield gate electrode (203) after the back etching to the upper surface of the semiconductor epitaxial layer (201) is 0.4-2.0 μm, and the height of the upper surface of the final trench oxide layer (202) after the back etching may be higher or lower than the height of the upper surface of the shield gate electrode (203), and the distance between the upper surface and the shield gate electrode is +/-0.5 μm.
The trench oxide layer 202 may be etched back by wet etching or dry etching, or a mixture thereof.
If the first dielectric layer 501 or the second dielectric layer 502 comprises an oxide material or the same material as the shield gate electrode 203, the etch back process may laterally etch the second dielectric layer 502 or the first dielectric layer 501 to shrink the horizontal boundary inward. In one embodiment, the first dielectric layer (501) is an oxide and the horizontal boundary shrinks inward by a distance of 0.05-0.2um after the trench oxide layer (202) is etched.
In one embodiment, to prevent the horizontal boundary of the first dielectric layer (501) or the second dielectric layer (502) from shrinking inward, a sidewall protection layer may be formed on the interface of the horizontal boundary of the second dielectric layer (502) and/or the first dielectric layer (501) before performing the corresponding etching back, so as to prevent the occurrence of the lateral etching. The sidewall protection layer may be a nitride. The sidewall protection layer may be removed after the etching is completed.
Seventhly, the first dielectric layer (501) is etched, so that the horizontal boundary of the first dielectric layer (501) shrinks inwards, as shown in fig. 12.
When the first dielectric layer (501) is etched, the etching rate of the second dielectric layer (502) is slower than that of the first dielectric layer (501), and the second dielectric layer (502) plays a role in protecting the upper surface of the first dielectric layer (501) in the etching process. Therefore, the etching of the first dielectric layer (501) occurs only in the horizontal direction, laterally etching from the side surface from the outside to the inside, and shrinking the horizontal boundary inward. Due to the protection of the second dielectric layer (502), the thickness of the first dielectric layer (501) remained after etching is unchanged from that before etching.
As mentioned in fig. 2-6, the trench structure of the present invention is characterized in that the trenches adjacent to the second type trench (251) and the third type trench (252) on the left and right are the first type trenches (250). Therefore, the first dielectric layer (501) above the second type trenches (251) and the third type trenches (252) is etched laterally, and the boundary of the first dielectric layer is shrunk inwards to the positions above the second type trenches (251) and the third type trenches (252). Wherein the first dielectric layer (501) above the second type trenches (251) may remain partially or may be completely etched away, as shown in fig. 12.
A top view of one embodiment of this step is shown in fig. 13, 14. Fig. 13 is a top view of the first dielectric layer (501) before etching, and fig. 14 is a top view of the first dielectric layer (501) after etching.
In fig. 13, the first dielectric layer (501) before etching covers the second-type trenches (251) and the third-type trenches (252), and the horizontal boundaries (801, 802) of the first dielectric layer (501) are at a distance of between 0.05um and 0.4um from the respective second-type trenches (251) and third-type trenches (252).
The first dielectric layer (501) is etched, and the horizontal boundaries (801, 802) of the first dielectric layer shrink in the direction of the second-type trenches (251) and the third-type trenches (252), as shown in fig. 14. The first dielectric layer (501) on the second type of trench (251) is completely removed, and the outermost first dielectric layer (501) has its boundary (803) shrunk above the third type of trench (252).
The method for etching the first dielectric layer (501) may be a wet etch.
In one embodiment, the first dielectric layer (501) is silicon nitride and the second dielectric layer (502) is silicon oxide, and the method for etching the first dielectric layer (501) may be wet etching, which may be performed in a hot phosphoric acid environment.
Before etching the first dielectric layer (501), it is possible to pre-form a protective layer that protects the exposed trench sidewalls and the shield gate electrode (203) within the trench, as well as the semiconductor upper surface. For example, thermal oxidation is performed in advance before etching the first dielectric layer (501), and an oxidation sacrificial layer of 50A-1000A is formed to cover the side wall of the trench and the shield gate electrode (203).
After etching the first dielectric layer (501), the second dielectric layer (502) may be removed or remain.
And finally forming a first dielectric layer (501) which covers the periphery of the third type of groove after etching, namely the mask dielectric layer (219).
In an eighth step, an inter-electrode spacer layer (204) is formed on the upper surface of the shield gate electrode (203), and a gate oxide layer (210) is formed on the upper trench sidewall, as shown in fig. 15.
The inter-electrode spacer layer (204) is typically an oxide and is formed by thermal oxidation, but may also be comprised of a semiconductor oxide, a semiconductor nitride, other insulating dielectric material, or a combination thereof.
The gate oxide layer (210) has a thickness of 150-1000A. The method of forming the gate oxide layer (210) may be thermal oxidation or deposition, or a combination of both. In one embodiment, the method of forming the gate oxide layer (210) is wet thermal oxidation at 900-.
In one embodiment, the inter-electrode isolation layer (204) is an oxide formed simultaneously with the gate oxide layer (210) by thermal oxidation. In the interelectrode isolation layer (204) and the gate oxide layer (210) formed simultaneously, the thickness of the interelectrode isolation layer (204) is thicker than that of the gate oxide layer (210). In one embodiment, the inter-electrode isolation layer (204) has a thickness of 200A-3000A, and the gate oxide layer (210) has a thickness of 150A-1000A.
In the ninth step, a gate electrode (205) is formed as shown in fig. 16.
The gate electrode 205 is typically comprised of polysilicon and may be formed by a process that may include both the deposition of polysilicon and the etching back of polysilicon. In one embodiment, the height of the gate electrode (205) is 0.4-1.1 μm. In one embodiment, the distance from the upper surface of the gate electrode (205) to the upper surface of the semiconductor is 0-0.5 μm.
In the tenth step, ion implantation is performed using the masking dielectric layer (219) as a hard mask, as shown in fig. 16.
The ion implantation comprises at least one step of P-type ion implantation with an implantation energy of 10keV-200keV, and possibly boron as a dopant at a dose of 1e12-5e14 cm-3In the meantime. The P-type ion implantation may be followed by a one-step thermal diffusion process. In one embodiment, the thermal diffusion temperature is 1000 ℃ 1150 ℃ for 10-300 minutes.
In addition, it is also possible to carry out a step N+Type ion implantation with implantation energy of 5keV-100keV, wherein the dopant for ion implantation may be arsenic with dosage of 1e13-5e16 cm-3In the meantime. N is a radical of+The type ion implantation may not require an additional photolithography step, or may require an additional photolithography step to pre-form a patterned photoresist to define N+A region of type ion implantation.
Forming a P-type doped body region (216), N, after the P-type ion implantation+Formation of N after type ion implantation+And (7) forming a type doping source region (215). The depth of the P-type doped body region (216) is 0.2-1.5 μm. N is a radical of+The depth of the type doping source region (215) is 0.05-1.0 mu m.
During the ion implantation, the masking dielectric layer (219) at the periphery of the trenches blocks the ion implantation, so that doped regions (215, 216) are defined within the series of trenches, as shown in fig. 17. Since the masking dielectric layer 219 serves as a self-aligned mask for ion implantation in this step, one to two photolithography steps may be omitted in this step.
The masking dielectric layer 219 may be removed or remain after ion implantation.
In the tenth step, an oxide dielectric layer (206) is formed on the upper surface of the semiconductor, and then a via hole (207) is formed on the oxide dielectric layer.
The oxide dielectric layer (206) is typically comprised of an oxide and has a thickness of 0.3-1.5 μm. In one embodiment, the oxide dielectric layer (206) comprises a layer of undoped silicon oxide with a thickness of 0.05-1.0 μm below and a layer of borophosphosilicate glass with a thickness of 0.1-1.5 μm above. The oxide dielectric layer 206 may be formed by a process including oxide deposition and oxide planarization.
The through hole (207) may have a shape with a large width at the top and a small width at the bottom. Wherein the width of the narrowest part is 0.05-1 μm. A portion of the via 207 is located directly above the trench and extends into either shield gate electrode 203 or gate electrode 205 as shown in fig. 18. A portion of the via 207 is located between the trenches and extends into the semiconductor, contacting the P-doped region 216 and the N + -doped source region 215, as shown in fig. 19.
The method for forming the through hole (207) can be as follows: then, dry etching is performed, and positions of the through holes are defined by the photoresist. During the etching process of the via 207, a step of etching the first dielectric layer 501 may be further included to remove a portion of the first dielectric layer 501 remaining above the second-type trenches 251 or the third-type trenches 252.
After etching the via hole, it is possible to perform one or more steps P+And implanting type ions to form a P + type doped contact region (217) in the P type doped body region (216). P+Before the type ion implantation, a silicon nitride protection layer may be formed on the sidewall of the through hole in advance to reduce the amount of ion implantation in the horizontal direction at the sidewall. The protective layer may be removed after ion implantation.
After the via is formed, it is possible to form a diffusion barrier metal in the via. Among them, the constituent material of the diffusion barrier metal may be a metal such as Ti, W, etc., or a metal compound thereof such as TiSi, TiN, etc.
In the twelfth step, an upper surface metal (209) is formed on the upper surface of the semiconductor and a lower surface metal (220) is formed under the semiconductor substrate (200), as shown in fig. 20.
The semiconductor top surface metal (209) is typically Al or an Al compound, e.g., Al/Cu, Al/Si/Cu, with a thickness of 3-5 μm. The lower surface metal (220) is typically Ag or an Ag compound and has a thickness of 0.1-2 μm.
Before forming the drain metal (220) under the semiconductor substrate (200), the semiconductor substrate (200) may be thinned to a thickness of 30-200 μm.
The manufacturing process flow of the shielded gate trench type field effect transistor disclosed by the invention utilizes the self-aligned mask to limit the range of ion implantation, so that the photoetching steps can be reduced. It should be noted that the process flow of the present invention is not limited to the above-described process steps. For example, in the above eighth step of one embodiment, the method for forming the inter-electrode isolation layer (204) and forming the gate oxide layer (210) may comprise the following steps:
first, a fill oxide (214) is formed by Chemical Vapor Deposition (CVD) to cover the trench, and the fill oxide (214) is etched back to have its upper surface in the trench, as shown in fig. 21. The Chemical Vapor Deposition (CVD) may be high density plasma chemical vapor deposition (HDP CVD). The etch-back may include a Chemical Mechanical Planarization (CMP) process and/or a dry etching process, and the distance from the top surface of the oxide 214 to the top surface of the semiconductor is 0-0.2um after the etch-back.
And secondly, forming a photoresist 1401 on the second-type groove 251 and the third-type groove 252, and etching back the oxide 214 under the protection of the photoresist 1401 to form the inter-electrode isolation layer 204, as shown in fig. 22. The inter-electrode isolation layer (204) has a thickness of 1000A-5000A.
Third, a gate oxide layer (210) is formed by thermal oxidation or deposition.
In another embodiment, the method for forming the inter-electrode isolation layer (204) and the gate oxide layer (210) in the eighth step comprises the following steps:
first, depositing nitride in the trench and performing dry etching on the nitride in the vertical direction to form a nitride protection layer (1501) covering the side walls of the trench and a nitride protection layer (1502) covering the side walls of the first dielectric layer (501) and the second dielectric layer (502) and exposing the shield gate electrode (203) in the trench, as shown in fig. 23.
In the second step, thermal oxidation is performed to form an inter-electrode isolation layer (204) on the upper surface of the shield gate electrode (203), as shown in fig. 24. The inter-electrode spacer (204) may have a shape with a thick middle and thin sides. The interpolar isolation layer (204) has a thinnest point of 500A-4000A. In another embodiment, a thermal oxidation step may be followed by a step of oxide deposition to planarize the top surface of the inter-electrode spacer (204).
Third, the nitride protective layer on the trench sidewalls is removed (1501, 1502).
Fourth, a gate oxide layer (210) is formed by thermal oxidation or deposition.
It will be appreciated by persons skilled in the relevant art that the embodiments of the invention described above are not limiting but exemplary and that the invention may be practiced in a broader range than the embodiments described above.

Claims (24)

1. A shielded gate MOSFET device, said MOSFET device comprising:
the lower surface metal at the bottom of the device,
a first conductivity type base layer over the bottom surface metal;
an epitaxial layer of a first conductivity type located over a substrate layer of the first conductivity type;
the epitaxial layer of the first conduction type is provided with more than one series of parallel grooves in the epitaxial layer of the first conduction type, and a doped body region of the second conduction type and a doped source region of the first conduction type which are positioned on the upper surface of the epitaxial layer of the first conduction type;
an oxide dielectric layer located over the series of trenches;
the upper surface metal is positioned above the oxide dielectric layer;
it is characterized in that the preparation method is characterized in that,
the outermost series of trenches is constituted by trenches of a first type;
the other series of grooves positioned in the outermost series of grooves are composed of more than one section of first-type grooves and second-type grooves which are mutually connected, the tail ends of the series of grooves are the first-type grooves, at least one horizontal groove which is the same as the first-type grooves connects the first-type grooves at the tail ends of all the series of grooves, and the second-type grooves in the adjacent series of grooves are arranged in a staggered mode;
more than one third type of grooves surrounding all the series of grooves are arranged at the outermost periphery of all the series of grooves;
the first type of groove is used for forming a conducting area, and a gate electrode and a shielding gate electrode are arranged in the groove;
the second type of groove is used for connecting the shielding gate electrode and the upper surface metal layer, and only the shielding gate electrode is arranged in the groove without the gate electrode;
the third type of groove is used for preventing the periphery of the device from being broken down, only the shielding gate electrode is arranged in the groove without the gate electrode, and the shielding gate electrode in at least one section of the second type of groove and the shielding gate electrode in at least one section of the first type of groove are connected with each other and then are finally connected to the upper surface metal.
2. The shielded gate MOSFET device of claim 1 wherein the shield gate electrodes in the second-type trenches and the third-type trenches are connected to the top surface metal by vias located in the oxide dielectric layer.
3. The shielded gate MOSFET device of claim 1,
the shield gate electrode and the gate electrode in the first-type trench are separated by an inter-electrode isolation layer;
and/or
The shield gate electrode and the gate electrode are isolated from the corresponding trench sidewalls by a trench oxide layer.
4. The shielded gate MOSFET device of claim 3,
the inter-electrode isolation layer is made of semiconductor oxide, semiconductor nitride and/or insulating medium materials.
5. The shielded gate MOSFET of claim 1 wherein the periphery of said third type of trench is provided with a masking dielectric layer over the top surface of the semiconductor.
6. The shielded gate MOSFET device of claim 2 wherein said via is shaped to have a width that is large at the top and small at the bottom.
7. The shielded gate MOSFET device of claim 1 wherein said third type of trench comprises interconnected vertical segment trenches and lateral segment trenches.
8. The shielded gate MOSFET device of claim 7 wherein the horizontal distance between the third type of trench vertical segment trench and the adjacent series of trenches is equal to the horizontal distance between any two parallel series of trenches and equal to the vertical distance between the third type of trench lateral segment trench and the adjacent horizontal trench.
9. The shielded gate MOSFET device of claim 1 wherein said doped body region of the second conductivity type further has a doped contact region of the second conductivity type disposed therein.
10. The shielded gate MOSFET device of claim 1 wherein said third type of trench is wider and deeper than the series of trenches in width and depth.
11. The shielded gate MOSFET device of any of claims 1-10 wherein said epitaxial layer of the first conductivity type further comprises more than one horizontal fifth trench, said fifth trench being of the first type, and wherein the gate electrode in said fifth trench is interconnected to the gate electrode in the first type of trench of the series of trenches which is at the same horizontal level.
12. The shielded gate MOSFET device of any of claims 1-10 wherein there is a minimum of a sixth trench around the periphery of the third-type trench surrounding the series of trenches, the sixth trench being spaced apart from the third-type trench by a distance D3 equal to the distance D1 from the third-type trench to the adjacent series of trenches.
13. The shielded gate MOSFET device of any of claims 1-10 wherein said horizontal trench is a fourth trench connecting the first-type trenches at the ends of all of the series of trenches.
14. The shielded gate MOSFET device of any one of claims 1-10 wherein said horizontal trench is an eighth trench, and wherein the first-type trenches at the ends of any two adjacent series of trenches are connected by said eighth trench to form a first inner-turn trench;
a first outer ring groove is arranged between every two adjacent first inner ring grooves, the first outer ring groove comprises a series of grooves and a seventh groove which connects the corresponding series of grooves to a transverse section groove of a third type of groove, and the seventh groove is a second type of groove; and the vertical section groove of the peripheral third type groove is adjacent to an inner ring groove.
15. The shielded gate MOSFET device of any of claims 1-10 wherein the horizontal trench is a ninth trench, and wherein a first type of trench at the end of two spaced-apart series of trenches is connected by the ninth trench to form a second inner wrap of trenches, the two series of trenches being spaced-apart by a first wrap of trenches, the first wrap of trenches ending in the first type of trench;
and a second outer ring groove is arranged between every two adjacent second inner ring grooves, the second outer ring groove comprises a series of grooves and a tenth groove which connects the corresponding series of grooves to the transverse section groove of the third type of groove, and the tenth groove is the second type of groove.
16. A method for manufacturing a shielded gate MOSFET device, comprising the steps of:
the first step is as follows: providing a substrate of a first conductive type, and forming an epitaxial layer of the first conductive type on the substrate;
secondly, forming a series of grooves on the epitaxial layer of the first conduction type;
thirdly, forming a trench oxide layer and a shielding gate electrode in the trench;
fourthly, forming a first dielectric layer on the upper surface of the semiconductor, and then forming a second dielectric layer on the first dielectric layer, wherein the etching rates of materials forming the first dielectric layer and the second dielectric layer are different;
fifthly, forming photoresist on the upper surfaces of the second type groove and the third type groove, and carrying out back etching under the protection of the photoresist to expose the shielding gate electrode in the groove; the boundary of the etched first medium layer is positioned between the second-type groove or the third-type groove and the second-type groove;
sixthly, etching back the shielding gate electrode and the trench oxide layer, and removing the photoresist;
seventhly, etching the first dielectric layer to enable the horizontal boundary of the first dielectric layer to shrink inwards; the first dielectric layer which is finally formed after etching and covers the periphery of the third type of groove is a mask dielectric layer;
eighthly, forming an inter-electrode isolation layer on the upper surface of the shielding gate electrode, and forming a gate oxide layer on the side wall of the groove at the upper part;
a ninth step of forming a gate electrode;
tenth step, using the mask dielectric layer as a hard mask to perform ion implantation, wherein the ion implantation at least comprises ion implantation of a second conductive type, and the formation of the doped body region of the second conductive type further comprises the ion implantation of a first conductive type to form a doped source region of the first conductive type;
a tenth step of forming an oxide dielectric layer on the upper surface of the semiconductor, and then forming a through hole on the oxide dielectric layer;
and a twelfth step of forming an upper surface metal on the upper surface of the semiconductor and a lower surface metal under the semiconductor substrate.
17. The method of claim 16, wherein the first dielectric layer and the second dielectric layer are formed from different materials selected from the group consisting of oxides, nitrides, poly-si and organic polymers.
18. The method of claim 16, wherein the first dielectric layer is comprised of silicon nitride and the second dielectric layer is comprised of silicon oxide.
19. The method of claim 16, wherein the first dielectric layer is comprised of polysilicon and the second dielectric layer is comprised of silicon oxide.
20. The method of claim 16, wherein in the sixth step, in order to prevent the horizontal boundary from shrinking inward due to the lateral etching of the first dielectric layer or the second dielectric layer during the etch-back process, a sidewall protection layer is formed in advance on the interface of the horizontal boundary of the second dielectric layer and/or the first dielectric layer before the etch-back process is performed, and the sidewall protection layer is removed after the etch-back process is completed.
21. The method of fabricating the shielded gate MOSFET of claim 16 wherein a sacrificial oxide layer is preformed prior to etching the first dielectric layer to protect exposed trench sidewalls and shield gate electrode within the trench and the semiconductor upper surface.
22. The method of fabricating a shielded gate MOSFET device as claimed in claim 16 wherein in the tenth step, the step of etching the via is followed by one or more steps of ion implantation of the second conductivity type to form the doped contact region of the second conductivity type in the doped body region of the second conductivity type.
23. The method of manufacturing a shielded gate MOSFET of claim 16 wherein the steps of forming the inter-electrode spacer and forming the gate oxide in the eighth step are:
firstly, forming a filling oxide covering a groove through chemical vapor deposition, and etching the filling oxide back to enable the upper surface of the filling oxide to be positioned in the groove;
secondly, forming photoresist on the second type of groove and the third type of groove, and etching back the oxide under the protection of the photoresist to form an inter-electrode isolation layer;
and thirdly, forming a gate oxide layer through thermal oxidation or deposition.
24. The method of manufacturing a shielded gate MOSFET of claim 16 wherein the steps of forming the inter-electrode spacer and forming the gate oxide in the eighth step are:
firstly, depositing nitride in a groove and carrying out dry etching on the nitride in the vertical direction to form a nitride protective layer covering the side wall of the groove and a nitride protective layer covering the side walls of a first dielectric layer and a second dielectric layer, and exposing a shield gate electrode in the groove;
secondly, carrying out thermal oxidation to form an inter-electrode isolation layer on the upper surface of the shielding gate electrode;
thirdly, removing the nitride protection layer on the side wall of the groove;
and fourthly, forming a gate oxide layer by thermal oxidation or deposition.
CN202010310099.0A 2020-04-20 2020-04-20 Shielding gate MOSFET device and preparation method thereof Active CN111415992B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010310099.0A CN111415992B (en) 2020-04-20 2020-04-20 Shielding gate MOSFET device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010310099.0A CN111415992B (en) 2020-04-20 2020-04-20 Shielding gate MOSFET device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111415992A CN111415992A (en) 2020-07-14
CN111415992B true CN111415992B (en) 2021-11-26

Family

ID=71494859

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010310099.0A Active CN111415992B (en) 2020-04-20 2020-04-20 Shielding gate MOSFET device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111415992B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111681963B (en) * 2020-08-11 2020-11-20 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and forming method thereof
CN113745339B (en) * 2021-09-07 2022-08-19 无锡新洁能股份有限公司 High-reliability power semiconductor device and manufacturing method thereof
CN113990755B (en) * 2021-10-25 2023-06-30 安建科技有限公司 Manufacturing method of shielded gate MOSFET device
CN114551589B (en) * 2022-04-26 2022-09-09 安建科技(深圳)有限公司 Power semiconductor device and preparation method thereof
CN115206807A (en) * 2022-09-16 2022-10-18 华羿微电子股份有限公司 Preparation method of medium-voltage shielded gate trench MOSFET device
CN115763543B (en) * 2023-01-09 2023-04-18 无锡先瞳半导体科技有限公司 Composite shielded gate field effect transistor
CN115799324B (en) * 2023-02-09 2023-05-16 无锡先瞳半导体科技有限公司 Segmented shielded gate field effect transistor
CN117727620B (en) * 2024-02-06 2024-04-12 深圳市顾邦半导体科技有限公司 Preparation method of shielded gate power device and shielded gate power device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8187939B2 (en) * 2009-09-23 2012-05-29 Alpha & Omega Semiconductor Incorporated Direct contact in trench with three-mask shield gate process
US7989887B2 (en) * 2009-11-20 2011-08-02 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates as termination
US8779510B2 (en) * 2010-06-01 2014-07-15 Alpha And Omega Semiconductor Incorporated Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
CN107104149B (en) * 2017-05-25 2020-04-07 中山汉臣电子科技有限公司 Power semiconductor device
US10263070B2 (en) * 2017-06-12 2019-04-16 Alpha And Omega Semiconductor (Cayman) Ltd. Method of manufacturing LV/MV super junction trench power MOSFETs
CN108389858A (en) * 2018-02-05 2018-08-10 华润微电子（重庆）有限公司 The shield grid groove MOSFET device and its manufacturing method of integrated ESD protection diodes
CN110034182A (en) * 2019-03-13 2019-07-19 上海华虹宏力半导体制造有限公司 The manufacturing method of trench-gate device with shield grid
CN110838448A (en) * 2019-11-13 2020-02-25 中芯集成电路制造(绍兴)有限公司 Shielded gate trench transistor and method of manufacturing the same
CN110993502A (en) * 2019-12-30 2020-04-10 广州粤芯半导体技术有限公司 Manufacturing method of shielded gate trench power device

Also Published As

Publication number Publication date
CN111415992A (en) 2020-07-14

Similar Documents

Publication Publication Date Title
CN111415992B (en) Shielding gate MOSFET device and preparation method thereof
US9105494B2 (en) Termination trench for power MOSFET applications
US20220085016A1 (en) Method for fabricating semiconductor device
CN111727491A (en) Structure and method for self-aligned trench MOSFET
CN101807574B (en) Groove type power MOS device and manufacturing method thereof
KR20180035410A (en) Semiconductor device and method for fabricating the same
JP4735235B2 (en) Insulated gate semiconductor device and manufacturing method thereof
CN103151382A (en) A method for preparing asymmetric polycrystalline silicon grid electrodes for optimizing terminating design in a groove power mosfet
CN113519054B (en) Method of manufacturing a shielded gate trench MOSFET device
CN112864018A (en) Groove type field effect transistor structure and preparation method thereof
CN111081779A (en) Shielding gate trench type MOSFET and manufacturing method thereof
CN111312824B (en) Groove type power semiconductor device and preparation method thereof
CN202473933U (en) Power metal oxide semiconductor (MOS) device with improved terminal structure
KR20180090928A (en) Power semiconductor device and manufacturing method thereof
CN113990755B (en) Manufacturing method of shielded gate MOSFET device
JP7316746B2 (en) Semiconductor device and method for manufacturing semiconductor device
CN117410347A (en) Super junction power device with low terminal area and preparation method
CN114823343A (en) Shielding gate MOSFET device and manufacturing method thereof
US20220140073A1 (en) Power semiconductor device and manufacturing method thereof
CN113725300B (en) Chip structure of multi-source MOS tube shared grid and manufacturing method thereof
CN205319162U (en) Low pressure MOSFET device with prevent electrostatic protection structure
CN106601811B (en) Trench type power transistor
CN217641348U (en) Shielding gate MOSFET device
CN114512403A (en) Method for manufacturing semiconductor device
CN221150023U (en) Power semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant