CN111413549A - High-reliability pulse width signal detection system, platform and method - Google Patents
High-reliability pulse width signal detection system, platform and method Download PDFInfo
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Abstract
The invention provides a high-reliability pulse width signal detection system, a platform and a method, comprising the following steps: the high-frequency counting and filtering module is used for sampling, counting and filtering by using a high-frequency clock which is millions times of the frequency of the input signal; the triple-modular redundancy latch and judgment module is used for storing the state of the filtered signal, performing combinational logic judgment and outputting the signal; the low-frequency signal sampling module is used for judging the signal state and counting the effective pulse width by using a low-frequency clock which is hundreds times of the input signal frequency; the pulse width counting and judging module is used for judging the effective pulse width value, judging that the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and judging that the input signal is an effective signal if the effective pulse width value is not larger than the preset threshold value; and the pulse width range judging module is used for tracking and counting when the signal is judged to be invalid, judging that the signal is valid and resetting the invalid level counter to count if the continuous count value of the invalid level is in a preset range, and resetting the pulse width counter to count if the signal is judged to be wrong.
Description
Technical Field
The invention relates to a satellite-borne electronic computer and a control technology, in particular to a high-reliability pulse width signal detection system, a platform and a method.
Background
An aircraft in a complex space environment is easy to generate abnormal large-amplitude jitter in a signal transmission process due to electromagnetic interference of the space environment.
In the traditional pulse width detection method, a shift register is mostly adopted to carry out short-time filtering (generally about lus), the jump edge of a collected signal is latched, the logic design is simple, and the reliability is poor. Because the effective width of the pulse width signal is generally ms or hundred ms, the edge of the signal jump may have signal disturbance above us level due to electromagnetic interference, and if the transmission link does not adopt a shielding cable or the grounding is not good, the signal transmission process may also have abnormal large-amplitude jitter, and the jitter may be mistakenly identified by using the traditional detection method. The high-reliability pulse width signal detection method can effectively eliminate the influence of interference signals on actual signals, correctly acquire the signal state, improve the fault-tolerant performance of the satellite-borne hardware platform and ensure the success of satellite tasks.
The invention mainly solves the technical problems that how to effectively eliminate the influence of interference signals on actual signals, avoid data latch errors caused by single event upset and carry out fault tolerance on abnormity in the signal transmission process and normally high or normally low levels when signals are in short circuit or open circuit.
Disclosure of Invention
The invention aims to provide a high-reliability pulse width signal detection system, a high-reliability pulse width signal detection platform and a high-reliability pulse width signal detection method, which are used for solving the problems that signals are mistakenly identified due to jitter when the traditional method is used for detection, and data latch errors can be caused due to a space single event upset effect in a storage process.
To achieve the above object, the present invention provides a highly reliable pulse width signal detection system, comprising:
the high-frequency counting and filtering module is used for sampling, counting and filtering the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
the triple-modular redundancy latch and judgment module is used for storing the state of the filtered signal through a register, and outputting the signal after the combinational logic judgment;
the low-frequency signal sampling module is provided with a pulse width counter and is used for judging the signal state by using a low-frequency clock which is hundreds times of the frequency of the input signal, when the signal is judged to be an effective value, the pulse width counter counts and adds 1, and the effective pulse width of the input signal is obtained through accumulation;
the pulse width counting and judging module is used for judging the effective pulse width value of the input signal, judging the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and otherwise judging the input signal is an effective signal and resetting the pulse width counter to count;
and the pulse width range judging module is provided with an invalid level counter and is used for tracking and counting when the low-frequency signal sampling module judges that the signal is invalid, if the continuous counting value of the invalid level is larger than the first proportional value range of the pulse width of the original input signal and smaller than the second proportional value range of the pulse width of the original input signal, the pulse width range judging module judges that the signal is valid, and the invalid level counter is reset and counted, otherwise, the pulse width counter is judged to be wrong, and the pulse width counter is reset and counted.
Preferably, the filtering width of the high frequency counting filtering module during filtering is set to any value between 1% and 3% of the pulse width of the sampling signal.
Preferably, the triple-modular redundancy latch and judgment module is provided with 3 registers for storing the state of the filtered signal, and performing 3-to-2 combinational logic judgment and outputting.
Preferably, the preset threshold of the pulse width counting and judging module is set to 120% of the input signal.
Preferably, the first ratio range is 80% and the second ratio range is 120%.
Preferably, the high frequency count filter module includes: the logic 1 counter and the logic 0 counter are respectively used for sampling the state of an input signal according to each constant edge of a preset sampling period during sampling counting, if the signal state is logic 1, the logic 1 counter is increased by 1, and if the signal state is logic 0, the logic 0 counter is increased by 1; when the count value of the logic 1 counter and/or the logic 0 counter overflows, the counter is cleared and outputs logic 1 and/or 0.
Preferably, the high-reliability pulse width signal detection system is arranged on the FPGA.
The invention also provides a high-reliability pulse width signal detection platform, which comprises the high-reliability pulse width signal detection system, an interface input circuit and a signal output device, wherein the signal output device is used for simulating the pulse width signal to be monitored and then outputting the pulse width signal to the interface input circuit, and the interface input circuit is used for transmitting an input signal to the high-reliability pulse width signal detection system.
The invention also provides a high-reliability pulse width signal detection method, which is used for the high-reliability pulse width signal detection system to detect the high-reliability pulse width signal and comprises the following steps:
s1: a high-frequency counting and filtering module is adopted to sample, count and filter the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
s2: the state of the filtered signal is stored by a triple-modular redundancy latch and judgment module through a register, and the filtered signal is output after being subjected to combinational logic judgment;
s3: adopting a low-frequency signal sampling module to judge the signal state by using a low-frequency clock which is hundreds times of the frequency of an input signal, counting and adding 1 when the signal is judged to be an effective value, and accumulating to obtain the effective pulse width of the input signal;
s4: judging the effective pulse width value of the input signal by adopting a pulse width counting judgment module, judging that the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and judging that the input signal is an effective signal and resetting the counting if the effective pulse width value is not larger than the preset threshold value;
s5: and tracking and counting when the low-frequency signal sampling module judges that the signal is invalid by adopting a pulse width range judgment module, judging that the signal is valid if the continuous count value of invalid level is larger than the first proportional value range of the pulse width of the original input signal and smaller than the second proportional value range of the pulse width of the original input signal, and resetting the invalid level counter for counting, otherwise, judging that the signal is wrong, and resetting the pulse width counter for counting.
By adopting the high-reliability pulse width signal detection method, the influence of interference signals on actual signals can be effectively eliminated, data latch errors caused by single event upset can be avoided, and the method has good fault-tolerant capability on abnormity in the signal transmission process and normally high or normally low levels when the signals are in short circuit or open circuit, and is an extremely reliable method for detecting the pulse width signals.
The high-reliability pulse width signal detection method can effectively eliminate the influence of interference signals on actual signals, correctly acquire the signal state, improve the fault-tolerant performance of a satellite-borne hardware platform and ensure the success of satellite tasks.
Drawings
FIG. 1 is a schematic diagram of a highly reliable pulse width signal detection system according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a highly reliable pulse width signal detection platform according to a preferred embodiment of the present invention;
fig. 3 is a flow chart of a method for detecting a high-reliability pulse width signal according to a preferred embodiment of the present invention.
Detailed Description
While the embodiments of the present invention will be described and illustrated in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed, but is intended to cover various modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
For the convenience of understanding the embodiments of the present invention, the following description will be further explained by taking specific embodiments as examples with reference to the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.
As shown in fig. 1, the present embodiment provides a highly reliable pulse width signal detection system, which includes:
the high-frequency counting and filtering module 10 is used for sampling, counting and filtering the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
the triple-modular redundancy latch and judgment module 20 is used for storing the state of the filtered signal through a register, performing combinational logic judgment and outputting the signal;
the low-frequency signal sampling module 30 is provided with a pulse width counter, and is used for judging the signal state by using a low-frequency clock which is hundreds times of the frequency of the input signal, and when the signal is judged to be an effective value, the pulse width counter counts and adds 1, and the effective pulse width of the input signal is obtained through accumulation;
the pulse width counting and judging module 40 is used for judging the effective pulse width value of the input signal, judging the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and otherwise judging the input signal is an effective signal and resetting the pulse width counter to count;
the pulse width range determining module 50 is provided with an invalid level counter, and is configured to perform tracking counting when the low-frequency signal sampling module determines that the signal is invalid, and determine that the low-frequency signal sampling module is valid if a continuous count value of the invalid level is larger than a first proportional value range of the pulse width of the original input signal and smaller than a second proportional value range of the pulse width of the original input signal, and clear the invalid level counter for counting, otherwise, determine that the low-frequency signal sampling module is wrong, and clear the pulse width counter for counting.
The high-reliability pulse width signal detection system is arranged on a programmable device (namely, an FPGA-File programmable Gate array). specifically, a high-frequency counting filter module 10, a triple-modular redundancy latch and judgment module 20, a low-frequency signal sampling module 30, a pulse width counting judgment module 40 and a pulse width range judgment module 50 are arranged on the FPGA module to realize the required design.
Further, the filtering width of the high frequency counting filtering module in this embodiment is set to any value between 1% and 3% of the pulse width of the sampling signal, and those skilled in the art can select the filtering width as needed. Wherein, the value range includes 1% and 3%.
And 3 registers are arranged in the triple-modular redundancy latch and judgment module and used for storing the state of the filtered signal, performing 3-to-2 combinational logic judgment and outputting the result. The 3 registers here store the signal values, register0, register1 and register2, respectively, compared two by two, if register0 is register1, the output signal is the value of register 0; register1 ═ register2, the output signal is the value of register 1; the output signal is the value of register0, register0 ═ register 2. This ensures the correctness of signal access.
Preferably, the preset threshold of the pulse width counting and judging module is set to 120% of the input signal. The first range of proportionality values is 80% and the second range of proportionality values is 120%.
In addition, the high frequency count filter module further includes: the logic 1 counter and the logic 0 counter are respectively used for sampling the state of an input signal according to each constant edge of a preset sampling period during sampling counting, if the signal state is logic 1, the logic 1 counter is increased by 1, and if the signal state is logic 0, the logic 0 counter is increased by 1; when the count value of the logic 1 counter and/or the logic 0 counter overflows, the counter is cleared and outputs logic 1 and/or 0.
As shown in fig. 2, the present embodiment further provides a highly reliable pulse width signal detection platform, which includes the above-mentioned highly reliable pulse width signal detection system 1, an interface input circuit 2 and a signal output device 3, wherein the interface input circuit 2 is configured to transmit an input signal to the highly reliable pulse width signal detection system, and the signal output device 3 is configured to simulate a pulse width signal to be monitored and then output the pulse width signal to the interface input circuit 2. The platform can effectively perform high-reliability pulse width signal detection aiming at the faults of single event upset error or electromagnetic interference and the like of the satellite in the orbit stage through the high-reliability pulse width signal detection system 1.
Specifically, when the signal detection platform is built and then detection is carried out, firstly, a pulse width signal, such as a low-level effective square wave CMOS signal with the amplitude of 0-5V and the pulse width of 100ms, is generated through signal output equipment. And then an interface input circuit is utilized, a proper resistor, a proper capacitor and a proper signal isolation integrated circuit are adopted for building, for example, a Rc circuit is built by adopting a 50K ohm resistor and a 340pF capacitor, and a 54 series integrated circuit is adopted for isolating and shaping signals and then inputting the signals to a signal detection module. Finally, a circuit module with an FPGA (namely a high-reliability pulse width signal detection system) is used for signal detection. The platform utilizes the signal output equipment to simulate and output pulse width signals needing to be detected, the detection platform inputs the signals to the signal detection FPGA module through the interface input circuit, and the FPGA programmable characteristic is utilized to realize the functions of the signal detection system and then operate on the FPGA by using a hardware programming language, so that the detection platform is simple and efficient.
The embodiment further provides a high-reliability pulse width signal detection method, which is used for performing high-reliability pulse width signal detection by using the high-reliability pulse width signal detection system, and comprises the following steps:
s1: a high-frequency counting and filtering module is adopted to sample, count and filter the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
s2: the state of the filtered signal is stored by a triple-modular redundancy latch and judgment module through a register, and the filtered signal is output after being subjected to combinational logic judgment;
s3: adopting a low-frequency signal sampling module to judge the signal state by using a low-frequency clock which is hundreds times of the frequency of an input signal, counting and adding 1 when the signal is judged to be an effective value, and accumulating to obtain the effective pulse width of the input signal;
s4: judging the effective pulse width value of the input signal by adopting a pulse width counting judgment module, judging that the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and otherwise, judging that the input signal is an effective signal and resetting the pulse width counter for counting;
s5: and tracking and counting when the low-frequency signal sampling module judges that the signal is invalid by adopting a pulse width range judgment module, judging that the signal is valid if the continuous count value of invalid level is larger than the first proportional value range of the pulse width of the original input signal and smaller than the second proportional value range of the pulse width of the original input signal, and resetting the invalid level counter for counting, otherwise, judging that the signal is wrong, and resetting the pulse width counter for counting.
In step S1, when a high frequency clock with millions times of input signal frequency is used to sample and count signals (for example, when the input signal, i.e., the sampled pulse width signal is 100ms, the counting clock period is 100ns, and logic determination and counting are performed at this period), the signal state is sampled at each clock edge, specifically, two sampling counters of a high frequency counting filter module, i.e., a logic 1 counter and a logic 0 counter are used to sample and count, if 10000 times (i.e., count 10000 × 100ns is 1ms) are high level, the signal is defined as 1, otherwise, 1ms is low level, the signal is defined as 0, when the signal is sampled to be logic 1, the logic 1 counter is increased by 1, otherwise, the count width of the logic 0 counter is increased by 1% of the sampled pulse width signal, for example, when the input signal is 100ms, the maximum value of the counter is 10000.
The triple modular redundancy latch and decision block in step S2 performs a combinational logic decision of 3 to 2 by sampling 3 register latch signals. When at least 2 of the three latch values are judged to be the same, the output is carried out, so that the abnormal rewriting of the data caused by the space single-particle radiation effect and the like in the access process can be effectively avoided.
The low frequency signal sampling module counts by the set pulse width counter in step S3. Specifically, signal state judgment is performed by using a low-frequency clock (if the input pulse width signal is 100ms, the sampling clock is 1ms), which is one hundred times the frequency of the input pulse width signal, and when the signal is judged to be an effective value, the count of the pulse width counter is increased by 1, and thus, the signal is accumulated for effective pulse width judgment.
In step S4, the pulse width counting and determining module reads the pulse width counter value for determination, determines that the signal is erroneous if the counting width is greater than 120% of the signal, determines that the signal is valid if the counting width is not out of the range, and clears the count value to wait for the next signal input. The pulse width counting is judged, and the errors that the signal transmission process is abnormal, and the signal is in short circuit or open circuit, and the signal is judged to be an effective signal by mistake, namely the normal high or low level can be eliminated.
The pulse width range determination module in step S5 reads the pulse width counter value, and if the pulse width counter value is continuously counted to an invalid signal level value, the pulse width range determination needs to be performed, and at this time, if the pulse width count range is greater than 80% of the pulse width of the input signal and less than 120% of the pulse width of the input signal, it is determined that the signal is an valid signal and can be used to perform a corresponding action, and meanwhile, the count value is cleared, and a next signal input is waited. If the judgment range is exceeded, the signal is considered to be wrong. The pulse width range is judged, so that possible large-amplitude jitter interference in signal transmission can be eliminated, the influence of interference signals on actual signals can be eliminated in time, and the fault-tolerant effect is achieved.
Specifically, referring to fig. 3, after the pulse width signal is input, a frequency counting clock is used for periodic filtering. Then, the state latch is carried out on the filtered signal, 3 registers are adopted to store the signal state, and then the combinational logic judgment of 3-to-2 is carried out for output. And returning if no falling edge occurs, and sampling by a period of 1% of the pulse width if the falling edge occurs. If the sampling is carried out to the low level, the sampling count is added with 1, at the moment, if the count is more than 120 percent of the pulse width, the count is cleared, the pulse width is judged not to exceed the range, and the instruction is not executed; and if the high level is continuously sampled, clearing the count and executing the instruction when the count is more than or equal to 80% of the pulse width and less than or equal to 120% of the pulse width, and if the count is not in the range, judging that the pulse width exceeds the range, and executing the instruction. The instructions herein refer to actions required in the information contained in the signal.
Here, when the pulse width signal to be sampled is 100ms in step S1 and the count clock cycle is 100ns, and when the signal taken out from the register is sampled with a clock of 1ms cycle in step S3, if the signal is found to be logic 0 (the signal is active at low level), it is determined that the active signal is started, and the counter starts counting. In this example, if the continuous count value is greater than 120, it is determined that the signal is erroneous, and the behavior required for the signal is not executed. And (3) changing the signal into logic 1 in the sampling, judging whether the count of the logic 1 is more than 3, if so, judging whether the count range is less than 120 and more than 80, if so, judging that the signal is correct, executing the action required by the signal, otherwise, judging that the signal is wrong, and not executing the action required by the signal.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to make modifications or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. A highly reliable pulse width signal detection system, comprising:
the high-frequency counting and filtering module is used for sampling, counting and filtering the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
the triple-modular redundancy latch and judgment module is used for storing the state of the filtered signal through a register, and outputting the signal after the combinational logic judgment;
the low-frequency signal sampling module is provided with a pulse width counter and is used for judging the signal state by using a low-frequency clock which is hundreds times of the frequency of the input signal, when the signal is judged to be an effective value, the pulse width counter counts and adds 1, and the effective pulse width of the input signal is obtained through accumulation;
the pulse width counting and judging module is used for judging the effective pulse width value of the input signal, judging the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and otherwise judging the input signal is an effective signal and resetting the pulse width counter to count;
and the pulse width range judging module is provided with an invalid level counter and is used for tracking and counting when the low-frequency signal sampling module judges that the signal is invalid, if the continuous counting value of the invalid level is larger than the first proportional value range of the pulse width of the original input signal and smaller than the second proportional value range of the pulse width of the original input signal, the pulse width range judging module judges that the signal is valid, and the invalid level counter is reset and counted, otherwise, the pulse width counter is judged to be wrong, and the pulse width counter is reset and counted.
2. The system according to claim 1, wherein the filtering width of the high frequency count filtering module during filtering is set to any value between 1% and 3% of the pulse width of the sampling signal.
3. The system according to claim 1, wherein the triple-modular redundancy latch and judgment module is provided with 3 registers for storing the state of the filtered signal, and performing a combinational logic judgment of 2 out of 3 for outputting.
4. The system according to claim 1, wherein the preset threshold of the pulse width counting and determining module is set to 120% of the input signal.
5. The system according to claim 1, wherein said first proportional range is 80% and said second proportional range is 120%.
6. The highly reliable pulse width signal detection system of claim 1, wherein said high frequency count filter module comprises: the logic 1 counter and the logic 0 counter are respectively used for sampling the state of an input signal according to each constant edge of a preset sampling period during sampling counting, if the signal state is logic 1, the logic 1 counter is increased by 1, and if the signal state is logic 0, the logic 0 counter is increased by 1; when the count value of the logic 1 counter and/or the logic 0 counter overflows, the counter is cleared and outputs logic 1 and/or 0.
7. The system according to claim 1, wherein the system is disposed on an FPGA.
8. A highly reliable pulse width signal detection platform, comprising the highly reliable pulse width signal detection system as claimed in any one of claims 1 to 7, and an interface input circuit and a signal output device, wherein the signal output device is used for simulating a pulse width signal to be monitored and then outputting the pulse width signal to the interface input circuit, and the interface input circuit is used for transmitting an input signal to the highly reliable pulse width signal detection system.
9. A method for detecting a highly reliable pulse width signal by sampling the highly reliable pulse width signal detection system according to any one of claims 1 to 7, comprising the steps of:
s1: a high-frequency counting and filtering module is adopted to sample, count and filter the input signal by a high-frequency clock which is millions times of the frequency of the input signal;
s2: the state of the filtered signal is stored by a triple-modular redundancy latch and judgment module through a register, and the filtered signal is output after being subjected to combinational logic judgment;
s3: adopting a low-frequency signal sampling module to judge the signal state by using a low-frequency clock which is hundreds times of the frequency of an input signal, counting and adding 1 when the signal is judged to be an effective value, and accumulating to obtain the effective pulse width of the input signal;
s4: judging the effective pulse width value of the input signal by adopting a pulse width counting judgment module, judging that the input signal is wrong when the effective pulse width value is larger than a preset threshold value, and judging that the input signal is an effective signal and resetting the counting if the effective pulse width value is not larger than the preset threshold value;
s5: and tracking and counting when the low-frequency signal sampling module judges that the signal is invalid by adopting a pulse width range judgment module, judging that the signal is valid if the continuous count value of invalid level is larger than the first proportional value range of the pulse width of the original input signal and smaller than the second proportional value range of the pulse width of the original input signal, and resetting the invalid level counter for counting, otherwise, judging that the signal is wrong, and resetting the pulse width counter for counting.
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