CN110147140B - Clock signal cross comparison monitoring method and circuit - Google Patents

Clock signal cross comparison monitoring method and circuit Download PDF

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Publication number
CN110147140B
CN110147140B CN201910385029.9A CN201910385029A CN110147140B CN 110147140 B CN110147140 B CN 110147140B CN 201910385029 A CN201910385029 A CN 201910385029A CN 110147140 B CN110147140 B CN 110147140B
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clock
frequency ratio
detection circuit
signal
upper limit
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CN110147140A (en
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段小虎
边庆
王博
程俊强
索晓杰
袁迹
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Xian Aeronautics Computing Technique Research Institute of AVIC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The invention provides a clock signal cross comparison monitoring method and a clock signal cross comparison monitoring circuit. The method comprises the following steps: taking the clock A as a reference clock of a first clock detection circuit; taking the clock B as a measured clock of a first clock detection circuit; detecting a first clock frequency ratio between a clock A and a clock B through a first clock detection circuit, and outputting a first signal group representing that the first clock frequency ratio is not in a preset expected frequency ratio range; when any one of the first signal group is valid, at least one of clocks A and B is confirmed to have a problem. The invention provides a clock signal cross comparison monitoring circuit and a monitoring method thereof. The monitoring circuit can be realized through an FPGA, monitors the frequency ratio of two clock signals and judges whether the frequency ratio exceeds an allowable error range. In a hardware system containing a plurality of clock signals, the invention can be used for monitoring the running state of each clock in real time and reporting clock faults, thereby improving the reliability of the system.

Description

Clock signal cross comparison monitoring method and circuit
Technical Field
The invention belongs to the field of high-reliability computer hardware design, and relates to a clock signal cross comparison monitoring method and a circuit.
Background
In the field of highly reliable computer hardware design, both the detection coverage of faults and the timely discovery of faults are extremely important. There are various technical means for achieving such a goal, for example, the triple modular redundancy design technique can timely find out faults of some functional circuits, the redundancy code error detection and correction technique can timely find out data errors of buses or memories and correct the data errors, the lock step operation technique can timely find out operation faults of processors, and the like.
However, none of these conventional techniques can detect errors in the hardware reference clock signal itself, and stable operation of the reference clock is a precondition for proper operation of these conventional techniques. When the reference clock malfunctions, such as an error becomes large or even stops, the correct operation of the hardware system is likely to be affected, resulting in a change in the predetermined operation time or even a stop of the hardware operation. The fault tolerance technology which is commonly used in the prior art can not monitor the error of the reference clock in time, and can not report the fault to the upper system in time, so that the fault can spread, and the reliability of the whole system is further affected.
Disclosure of Invention
The invention aims to: aiming at the problems that the clock error cannot be timely monitored and the system reliability is affected by the conventional fault-tolerant technology when the hardware reference clock fails and the background technology, the clock signal cross comparison monitoring circuit and the monitoring method thereof are provided. The monitoring circuit can timely monitor the running state of the clock signal and report faults, so that fault spreading can be avoided, and the reliability of a hardware system is further improved.
In a first aspect, a clock signal cross comparison monitoring method is provided, including:
taking the clock A as a reference clock of a first clock detection circuit;
taking the clock B as a measured clock of a first clock detection circuit;
detecting a first clock frequency ratio between a clock A and a clock B through a first clock detection circuit, and outputting a first signal group representing that the first clock frequency ratio is not in a preset expected frequency ratio range;
when any one of the first signal group is valid, at least one of clocks A and B is confirmed to have a problem.
Further, the first signal group includes:
a first upper limit signal representing that the first clock frequency ratio is higher than an upper limit of a preset desired frequency ratio range; a first lower limit signal is characterized in that the first clock frequency ratio is below a preset lower limit of the range of desired frequency ratios.
Further, the method further comprises:
taking the clock A as a measured clock of a second clock detection circuit;
taking the clock B as a reference clock of a second clock detection circuit;
detecting a second clock frequency ratio between the clock A and the clock B through a second clock detection circuit, and outputting a second signal group representing that the second clock frequency ratio is not in a preset expected frequency ratio range;
when the signal of the first signal group is invalid and the second upper limit signal in the second signal group is valid, the clock B is confirmed to be not provided with a signal.
Further, the second signal group includes:
a second upper limit signal representing that the second clock frequency ratio is higher than the upper limit of the preset expected frequency ratio range; a second lower limit signal characterizing that the second clock frequency ratio is below a lower limit of a preset desired frequency ratio range.
Further, before the detecting, by the first clock detecting circuit, the first clock frequency ratio between the clock a and the clock B, the method further includes:
and receiving a reset signal to start the first clock detection circuit for detection.
In a second aspect, a clock signal cross-comparison monitor circuit is provided, comprising: a clock detection circuit;
the reference clock end of the clock detection circuit is connected with the clock A; the clock end to be detected of the clock detection circuit is connected with the clock B; the reset end of the clock detection circuit is connected with a reset signal; the frequency ratio of the detection circuit is higher than the upper limit end, and an upper limit signal representing that the frequency ratio of the clock is higher than the upper limit of a preset expected frequency ratio range is output; the frequency ratio lower limit end of the detection circuit outputs a lower limit signal representing that the clock frequency ratio is lower than the lower limit of a preset expected frequency ratio range.
Further, the clock detection circuit includes: the device comprises a reference counter for counting a reference clock, a measured counter for counting a measured clock, a reference point synchronous circuit and a state machine;
when the reference counter is clear, generating a reference point pulse; the synchronous circuit synchronizes the reference point pulse to obtain a synchronous pulse, and the synchronous pulse triggers the measured counter to clear and start counting; the state machine monitors the count value of the measured counter in real time, and when the final count value before the measured counter is cleared is greater than the preset upper limit, the state machine outputs an upper limit signal representing that the clock frequency ratio is higher than the upper limit of the preset expected frequency ratio range; when the final count value before the measured counter is cleared is smaller than the preset lower limit, the state machine outputs a lower limit signal representing that the clock frequency ratio is lower than the lower limit of the range of the preset expected frequency ratio, and a reset signal is input to the reset end of the reference counter so as to initialize the reference counter.
In a third aspect, a clock signal cross-comparison monitoring circuit is provided, including:
the first clock detection circuit, the second clock detection circuit and the judging circuit;
the reference clock end of the first clock detection circuit is connected with the clock A; the clock end to be detected of the first clock detection circuit is connected with the clock B; the reset end of the first clock detection circuit is connected with a reset signal; the frequency ratio of the first detection circuit is higher than the upper limit end to output a first upper limit signal representing that the frequency ratio of the first clock is higher than the upper limit of a preset expected frequency ratio range; the frequency ratio of the first detection circuit is lower than a first lower limit end, and a first lower limit signal representing that the frequency ratio of the first clock is lower than the lower limit of a preset expected frequency ratio range is output;
the reference clock end of the second clock detection circuit is connected with the clock B; the clock end to be detected of the second clock detection circuit is connected with the clock A; the reset end of the second clock detection circuit is connected with a reset signal; the frequency ratio of the second detection circuit is higher than the upper limit end to output a second upper limit signal representing that the frequency ratio of the second clock is higher than the upper limit of a preset expected frequency ratio range; the frequency ratio of the second detection circuit is lower than a lower limit end to output a second lower limit signal representing that the frequency ratio of the second clock is lower than the lower limit of a preset expected frequency ratio range;
the plurality of input ends of the judging circuit sequentially input a first upper limit signal, a first lower limit signal, a second upper limit signal and a second lower limit signal, and when the judging circuit judges that any signal is valid, at least one clock of the clock A and the clock B is confirmed to have a problem.
Further, when the signal is active high, the discrimination circuit is an or gate; when the signal is active low, the discrimination circuit is an AND gate.
The beneficial effects are that: in a hardware system containing a plurality of clock signals, the invention can be used for monitoring the running state of the clock signals in time and reporting clock faults, thereby avoiding fault propagation and improving the reliability of the system. The invention fills the gap that the clock error can not be monitored in time by the traditional fault-tolerant technology. The invention has the advantage that clock faults can be monitored and reported as long as any clock in the hardware system does not stop running.
Drawings
FIG. 1 is a schematic diagram of a clock detection circuit unit;
FIG. 2 is a schematic diagram of cycle counting of a measured clock according to a reference clock;
FIG. 3 is a state machine diagram of a clock detection circuit unit;
FIG. 4 is a schematic diagram illustrating the operation of the state machine when the ratio of the frequencies of the measured clock to the reference clock is within the tolerance allowable range;
FIG. 5 is a diagram illustrating the operation of the state machine when the ratio of the measured clock to the reference clock is higher than the upper limit allowed by the tolerance;
FIG. 6 is a diagram illustrating the operation of the state machine when the ratio of the measured clock to the reference clock is below the allowable lower limit of the tolerance;
FIG. 7 is a schematic diagram of a clock signal cross-comparison monitor circuit;
fig. 8 is a schematic diagram of a monitor circuit in which three clock signals are compared two by two.
Detailed Description
In a hardware system, there are usually multiple clock signals, and different clock signals may be used to perform state monitoring with each other, and the monitoring circuit may be implemented by using an FPGA. Fig. 1 is a basic clock detection circuit unit. In the clock detection circuit unit, the input signals have "reference clock", "measured clock", and "reset"; the output signal has a clock frequency ratio above an upper limit and a clock frequency ratio below a lower limit; the internal parameters include "reference clock cycle number", "lower limit of measured clock cycle number", and "upper limit of measured clock cycle number". The working principle of the clock detection circuit is as follows: and (3) counting the reference clock, wherein the counting time is a reference clock cycle, counting the cycle number of the measured clock in the time, and if the cycle number of the measured clock exceeds a set error range (the upper limit is an upper limit of the cycle number of the measured clock and the lower limit is a lower limit of the cycle number of the measured clock), considering that the frequency ratio of the reference clock and the measured clock exceeds the tolerance range and clock faults exist. Taking the 50MHz reference clock and the 33MHz measured clock as examples, if the frequency ratio tolerance error range of the system is +/-0.2%, the reference clock cycle number can be set to 30000 (if there is no error, the corresponding measured 33MHz clock cycle number should be 19800, 19800/30000=33/50), the measured clock cycle number lower limit is 19760, and the measured clock cycle number upper limit is 19840.
Fig. 2-6 are schematic diagrams of specific implementations of the clock detection circuit unit. As shown in fig. 2, the reference clock generates a reference point signal every "reference clock cycle number", where the reference point signal is a reference clock domain signal, and after clock domain synchronization processing, the reference point signal in the clock domain to be measured is generated, and the duration between two adjacent reference points is "reference clock cycle number" and is equal to the reference clock cycle number. The measured clock cycles are counted using an internal counter, which is cleared at each reference point, after which each measured clock cycle is self-incremented by 1.
Fig. 3 is a state machine for monitoring clock faults, each time the reference point is reached, the state returns "below the lower limit", after which the state transitions to "within tolerance" after the measured clock count value increases to "the lower limit of the number of measured clock cycles", until the state transitions to "above the upper limit" after the measured clock count value increases to "the upper limit of the number of measured clock cycles". The state of the state machine each time the reference point is reached indicates the current monitored clock condition. When the frequency ratio of the measured clock to the reference clock is within the tolerance allowable range, the working condition of the state machine is shown in fig. 4, and the clock is indicated to be normal; when the frequency ratio of the measured clock to the reference clock is higher than the upper limit allowed by the tolerance, the working condition of the state machine is shown in fig. 5, and clock faults are indicated; when the ratio of the measured clock to the reference clock frequency is below the lower limit allowed by the tolerance, the state machine operates as shown in fig. 6, indicating a clock failure. In addition, if the measured clock count value overflows (exceeds the maximum value that can be represented by the counter) and is not cleared, a clock fault is indicated.
In the clock detection circuit unit, if the reference clock and the measured clock do not stop running, the detection circuit can work normally, so that the clock state is reported. If the reference clock stops running, the measured clock count value will overflow, indicating a clock failure. If the clock to be measured stops running, the counter and the state machine of the clock to be measured are not operated any more, and the clock failure cannot be indicated. Therefore, as shown in fig. 7, two clock detection circuit units are used to constitute one clock cross alignment monitor circuit. The clock A and the clock B are compared in a crossing way, wherein in one clock detection circuit unit, the clock A is used as a reference clock, the clock B is used as a measured clock, and in the other clock detection circuit unit, the clock B is used as a reference clock, and the clock A is used as a measured clock. If any fault signal of the two clock detection circuit units is valid, the fault of the clock A or the clock B is indicated. In the clock cross comparison monitoring circuit, clock faults can be monitored and reported as long as any clock does not stop running.
If more than 2 clock signals exist in the hardware system, the clock signals can be compared pairwise, so that the clock state of the system is comprehensively monitored. For example, fig. 8 is an implementation where three clock signals are fault-monitored with respect to each other.
The working mode of the invention is as follows:
the clock detection circuit unit works as follows:
counting a reference clock, and generating a reference point signal once every other reference clock cycle;
synchronizing a reference point signal of a reference clock domain to a clock domain under measurement;
counting the period of the measured clock, clearing when reaching a reference point each time, and then increasing 1 per period;
if the accumulated measured clock cycle count is smaller than the lower limit of the measured clock cycle count or larger than the upper limit of the measured clock cycle count when the reference point is reached, reporting clock faults;
and if the counted value of the measured clock period overflows, reporting a clock fault.
The clock signal cross comparison monitoring circuit works as follows:
the clock signal cross comparison monitoring circuit comprises a clock detection circuit unit X and a clock detection circuit unit Y;
in the clock detection circuit unit X, a clock A is used as a reference clock, a clock B is used as a measured clock, and the measured clock is monitored and reported to a fault;
in the clock detection circuit unit Y, a clock B is used as a reference clock, a clock A is used as a measured clock, and the measured clock is monitored and reported to a fault;
if any fault signal of the two clock detection circuit units is valid, the fault of the clock A or the clock B is indicated.
The fault tolerance technology commonly used in the prior art can not monitor the error of the hardware reference clock in time, can not report clock faults in time, and is easy to spread faults when the clock is abnormal, thereby affecting the reliability of the system. Aiming at the problem, the invention provides a clock signal cross comparison monitoring circuit and a monitoring method thereof. The monitoring circuit can be realized through an FPGA, monitors the frequency ratio of two clock signals and judges whether the frequency ratio exceeds an allowable error range. In a hardware system containing a plurality of clock signals, the invention can be used for monitoring the running state of each clock in real time and reporting clock faults, thereby improving the reliability of the system.

Claims (7)

1. The clock signal cross comparison monitoring method is characterized by comprising the following steps of:
taking the clock A as a reference clock of a first clock detection circuit;
taking the clock B as a measured clock of a first clock detection circuit;
detecting a first clock frequency ratio between a clock A and a clock B through a first clock detection circuit, and outputting a first signal group representing that the first clock frequency ratio is not in a preset expected frequency ratio range;
when any signal in the first signal group is valid, confirming that at least one clock in the clock A and the clock B has a problem;
taking the clock A as a measured clock of a second clock detection circuit;
taking the clock B as a reference clock of a second clock detection circuit;
detecting a second clock frequency ratio between the clock A and the clock B through a second clock detection circuit, and outputting a second signal group representing that the second clock frequency ratio is not in a preset expected frequency ratio range;
when the signal of the first signal group is invalid and the second upper limit signal in the second signal group is valid, the clock B is confirmed to be not provided with a signal.
2. The method of claim 1, wherein the first signal group comprises:
a first upper limit signal representing that the first clock frequency ratio is higher than an upper limit of a preset desired frequency ratio range; a first lower limit signal is characterized in that the first clock frequency ratio is below a preset lower limit of the range of desired frequency ratios.
3. The method of claim 1, wherein the second signal group comprises:
a second upper limit signal representing that the second clock frequency ratio is higher than the upper limit of the preset expected frequency ratio range; a second lower limit signal characterizing that the second clock frequency ratio is below a lower limit of a preset desired frequency ratio range.
4. A method according to any one of claims 1-3, wherein prior to said detecting, by the first clock detection circuit, a first clock frequency ratio between clock a and clock B, the method further comprises: and receiving a reset signal to start the first clock detection circuit for detection.
5. A clock signal cross-comparison monitoring circuit for implementing the method of any of claims 1-3, the clock signal cross-comparison monitoring circuit comprising: a clock detection circuit;
the reference clock end of the clock detection circuit is connected with the clock A; the clock end to be detected of the clock detection circuit is connected with the clock B; the reset end of the clock detection circuit is connected with a reset signal; the frequency ratio of the detection circuit is higher than the upper limit end, and an upper limit signal representing that the frequency ratio of the clock is higher than the upper limit of a preset expected frequency ratio range is output; the frequency ratio lower limit end of the detection circuit outputs a lower limit signal representing that the clock frequency ratio is lower than the lower limit of a preset expected frequency ratio range.
6. The clock signal crossing comparison monitor circuit of claim 5, wherein the clock detection circuit comprises: the device comprises a reference counter for counting a reference clock, a measured counter for counting a measured clock, a reference point synchronous circuit and a state machine;
when the reference counter is clear, generating a reference point pulse; the synchronous circuit synchronizes the reference point pulse to obtain a synchronous pulse, and the synchronous pulse triggers the measured counter to clear and start counting; the state machine monitors the count value of the measured counter in real time, and when the final count value before the measured counter is cleared is greater than the preset upper limit, the state machine outputs an upper limit signal representing that the clock frequency ratio is higher than the upper limit of the preset expected frequency ratio range; when the final count value before the measured counter is cleared is smaller than the preset lower limit, the state machine outputs a lower limit signal representing that the clock frequency ratio is lower than the lower limit of the range of the preset expected frequency ratio, and a reset signal is input to the reset end of the reference counter so as to initialize the reference counter.
7. A clock signal cross-comparison monitor circuit, comprising:
the first clock detection circuit, the second clock detection circuit and the judging circuit;
the reference clock end of the first clock detection circuit is connected with the clock A; the clock end to be detected of the first clock detection circuit is connected with the clock B; the reset end of the first clock detection circuit is connected with a reset signal; the frequency ratio of the first detection circuit is higher than the upper limit end to output a first upper limit signal representing that the frequency ratio of the first clock is higher than the upper limit of a preset expected frequency ratio range; the frequency ratio of the first detection circuit is lower than a first lower limit end, and a first lower limit signal representing that the frequency ratio of the first clock is lower than the lower limit of a preset expected frequency ratio range is output;
the reference clock end of the second clock detection circuit is connected with the clock B; the clock end to be detected of the second clock detection circuit is connected with the clock A; the reset end of the second clock detection circuit is connected with a reset signal; the frequency ratio of the second detection circuit is higher than the upper limit end to output a second upper limit signal representing that the frequency ratio of the second clock is higher than the upper limit of a preset expected frequency ratio range; the frequency ratio of the second detection circuit is lower than a lower limit end to output a second lower limit signal representing that the frequency ratio of the second clock is lower than the lower limit of a preset expected frequency ratio range;
the plurality of input ends of the judging circuit sequentially input a first upper limit signal, a first lower limit signal, a second upper limit signal and a second lower limit signal, and when the judging circuit judges that any signal is valid, at least one clock of the clock A and the clock B is confirmed to have a problem.
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