CN111403421A - Array substrate, display device and manufacturing method of array substrate - Google Patents
Array substrate, display device and manufacturing method of array substrate Download PDFInfo
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- CN111403421A CN111403421A CN202010207266.9A CN202010207266A CN111403421A CN 111403421 A CN111403421 A CN 111403421A CN 202010207266 A CN202010207266 A CN 202010207266A CN 111403421 A CN111403421 A CN 111403421A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0414—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention provides an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises a substrate, a thin film transistor, a first insulating layer, a touch electrode, a second insulating layer and a pixel electrode which are sequentially arranged; the array substrate further comprises a touch metal pattern, a first via hole and a second via hole, the first via hole penetrates through the first insulating layer, and the second via hole is located in the first via hole; the touch electrode is electrically connected with the touch metal pattern through the first through hole, the thin film transistor comprises a source drain electrode, and the pixel electrode is electrically connected with the source drain electrode through the second through hole. Because the second via hole is positioned in the first via hole, the structure between the second via hole and the first via hole is cancelled, the problem that a film above the part of structure is broken due to stress concentration can be avoided, the probability of poor film tearing is reduced, and the service life of the array substrate is prolonged.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate, a display device and a manufacturing method of the array substrate.
Background
With the continuous improvement of display technology, the demand of people for display devices is also continuously increasing, and among various display technologies, optoelectronic products such as Thin Film Transistor displays, which use a TFT (Thin Film Transistor) as a control element and integrate a large-scale semiconductor integrated circuit and a flat panel light source technology, become a new generation of mainstream display products with the advantages of low power consumption, convenience in carrying, wide application range, high quality, and the like.
Taking L TPS (L w Temperature polysilicon) Display products as an example, the common L TPS Display products at present are TDDI (Touch and Display Driver Integration) products, Touch electrodes of the mainstream TDDI products are in contact with the surface of a Touch metal pattern through via holes to realize electrical connection, and pixel electrodes are electrically connected to source and drain electrodes of a thin film transistor through another via hole.
Disclosure of Invention
The invention provides an array substrate with prolonged service life, a display device and a manufacturing method of the array substrate.
The invention provides an array substrate, which comprises a substrate, a thin film transistor formed on the substrate, a first insulating layer formed on the thin film transistor, a touch electrode formed on the first insulating layer, a second insulating layer formed on the touch electrode and a pixel electrode formed on the second insulating layer, wherein the thin film transistor is arranged on the substrate; the array substrate further comprises a touch metal pattern, a first via hole and a second via hole, the first via hole penetrates through the first insulating layer, and the second via hole is located in the first via hole; the touch electrode is electrically connected with the touch metal pattern through the first through hole, the thin film transistor comprises a source drain electrode, and the pixel electrode is electrically connected with the source drain electrode through the second through hole.
Further, the source and drain electrodes comprise a source electrode and a drain electrode which are arranged along the transverse direction, and the transverse dimension of the first through hole is 11.2 mm-15 mm.
Further, the transverse size of the first via hole is 12 mm-13 mm.
Further, the touch metal pattern comprises an upper surface and a plurality of side surfaces connected with the upper surface, and the touch electrode is electrically contacted with the upper surface and at least one side surface of the touch metal pattern.
Further, the side surface in contact with the touch electrode faces the source-drain electrode.
Furthermore, the source/drain electrode and the touch metal pattern are arranged on the same layer.
Further, the second via hole penetrates through the second insulating layer, and the second insulating layer is partially located in the first via hole.
Further, the touch electrode is multiplexed as a common electrode, and the orthographic projection of the touch electrode on the substrate is at least partially overlapped with the orthographic projection of the pixel electrode on the substrate.
In another aspect, the present invention further provides a display device, which includes the array substrate as described above.
In another aspect, the present invention further provides a method for manufacturing an array substrate, where the method includes: providing a substrate; forming a buffer layer on the substrate; forming a thin film transistor on the buffer layer, wherein the thin film transistor comprises a source drain electrode and a touch metal pattern; forming a first insulating layer on the thin film transistor, the first insulating layer including a first via hole; forming a touch electrode on the first insulating layer, wherein the touch electrode is electrically connected with the touch metal pattern through the first via hole; forming a second insulating layer on the touch electrode, wherein the second insulating layer comprises a second through hole positioned in the first through hole; and forming a pixel electrode on the second insulating layer, wherein the pixel electrode is electrically connected with the source and drain electrodes through the second through hole.
In the invention, the second via hole is positioned in the first via hole, so that the structure between the second via hole and the first via hole is cancelled, the problem that a film above the part of structure is broken due to stress concentration can be avoided, the probability of poor film tearing is reduced, and the service life of the array substrate is prolonged.
Drawings
Fig. 1 is a partial cross-sectional view of an array substrate.
Fig. 2 is a partial cross-sectional view of an array substrate according to an embodiment of the present invention.
Fig. 3 is a schematic view of a structure for forming a buffer layer on a substrate.
Fig. 4 is a schematic view of a structure in which a thin film transistor is formed on a buffer layer.
Fig. 5 is a schematic structural view of a first insulating layer formed over a thin film transistor.
Fig. 6 is a schematic structural diagram of forming a touch electrode on a first insulating layer.
Fig. 7 is a schematic structural diagram of forming a second insulating layer on the touch electrode.
Fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus consistent with certain aspects of the invention, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Referring to fig. 1, in the array substrate, the touch electrode 5A is electrically connected to the touch metal pattern 30A through one via hole, and the pixel electrode 7A is electrically connected to the drain electrode 36A in the source/drain electrode through another via hole, but as the display requirement of the current product is higher and higher, the pixel density is higher and higher, so that the size of each unit of the array substrate is smaller and smaller. Correspondingly, in each unit of the array substrate, the distance between the pixel via hole and the touch metal pattern via hole is smaller and smaller, the transverse size of the structure between the two via holes is smaller, so that the stress borne by the film above the structure is concentrated, the film is easy to break, and the broken film area can accumulate static electricity when the film is torn, so that the liquid crystal deflection is influenced, the tearing is poor, and the service life of the array substrate is influenced.
The invention provides an array substrate, which comprises a substrate, a thin film transistor formed on the substrate, a first insulating layer formed on the thin film transistor, a touch electrode formed on the first insulating layer, a second insulating layer formed on the touch electrode and a pixel electrode formed on the second insulating layer, wherein the thin film transistor is arranged on the substrate; the array substrate further comprises a touch metal pattern, a first via hole and a second via hole, the first via hole penetrates through the first insulating layer, and the second via hole is located in the first via hole; the touch electrode is electrically connected with the touch metal pattern through the first through hole, the thin film transistor comprises a source drain electrode, and the pixel electrode is electrically connected with the source drain electrode through the second through hole. Because the second via hole is positioned in the first via hole, the structure between the second via hole and the first via hole is cancelled, the problem that a film above the part of structure is broken due to stress concentration can be avoided, the probability of poor film tearing is reduced, and the service life of the array substrate is prolonged.
Referring to fig. 2, in this embodiment, the array substrate 100 may be used for a liquid crystal panel, and in other embodiments, the array substrate 100 may also be used for an O L ED panel, the array substrate includes a substrate 1, and a buffer layer 2, a thin film transistor 3, a first insulating layer 4, a touch electrode 5, a second insulating layer 6, and a pixel electrode 7, which are sequentially disposed, the buffer layer 2 is formed on the substrate 1, the thin film transistor 3 is formed on the buffer layer 2, the first insulating layer 4 is formed on the thin film transistor 3, the touch electrode 5 is formed on the first insulating layer 4, the second insulating layer 6 is formed on the touch electrode 5, and the pixel electrode 7 is formed on the second insulating layer 6, where "formed on … …" indicates not only a manufacturing process, but also indicates that the two are disposed in an up-down direction, wherein the two may be disposed adjacently or disposed at intervals, the array substrate 100 may be divided into a plurality of cells, each cell corresponds to a pixel of a liquid crystal panel, and a structure of one cell of the array substrate 100 is shown in fig. 2, and mainly described below.
Referring to fig. 3, the material of the substrate 1 may be selected from glass, plastic, and the like. The buffer layer 2 is formed on the substrate 1, and is used for realizing stress release and dislocation filtering, solving the problem of lattice mismatch between an upper layer and a lower layer, and obtaining perfect crystal quality. The material of the buffer layer 2 may be selected from nitride, oxide, oxynitride, or the like.
Referring to fig. 4, the thin film transistor 3 is formed on the buffer layer 2, and includes an active layer 31, a gate insulating layer 32, a gate 33, an interlayer insulating layer 34, and a source/drain electrode sequentially disposed thereon, where the source/drain electrode includes a source electrode 35 and a drain electrode 36 disposed along a transverse direction X. The active layer 31 is made of low-temperature polysilicon (P-Si), and the source and drain electrodes are in contact with the active layer 31 through via holes penetrating through the gate insulating layer 32 and the interlayer insulating layer 34.
In this embodiment, in order to enable the array substrate 100 to have the functions of the array substrate itself and also have the touch function, the array substrate 100 further includes a touch metal pattern 30, the touch metal pattern 30 and the source/drain electrodes are disposed in the same layer, and the "same layer disposition" may be formed in the same process by using the same material, which is beneficial to simplifying the manufacturing process of the array substrate. It should be noted that the touch metal pattern 30 includes a portion contacting the surface of the touch electrode, and also includes a trace portion disposed in the peripheral area of the array substrate 100, and the trace portion is used for inputting and outputting the touch signal. In other embodiments, the touch metal pattern may be disposed on the same layer as other metal structures or on a single layer.
Referring to fig. 5, the first insulating layer 4 is formed on the thin film transistor 3, and the first insulating layer 4 is partially etched to form a first via hole 41, where the first via hole 41 penetrates through the first insulating layer 4. The first insulating layer 4 is a passivation layer for protecting each film layer covered by the first insulating layer. The material of the first insulating layer 4 is, for example, SiO2 or sion x.
Referring to fig. 6, the touch electrode 5 is formed on the first insulating layer 4, the touch electrode 5 is electrically connected to the touch metal pattern 30 through the first via 41, and the touch metal pattern 30 receives a common end signal through the touch electrode 5 (multiplexed as a common electrode). The touch electrode 5 is made of, for example, a transparent ITO (indium tin oxide) material. The touch metal pattern 30 includes an upper surface 301 (see fig. 5) and a plurality of side surfaces 302 (see fig. 5) connected to the upper surface, and the touch electrode 5 is electrically contacted with the upper surface 301 and at least one side surface 302 of the touch metal pattern 30, so as to increase the contact area between the touch electrode 5 and the touch metal pattern 30, thereby being beneficial to reducing the contact resistance of the two, avoiding the problem of poor touch caused by too large contact resistance, reducing the probability of poor touch, and improving the touch performance.
Of course, if as many sides as possible are to be contacted with the touch electrode 5, the shape of the first via hole 41 is also adapted, which further complicates the manufacturing process of the first insulating layer 4. In this embodiment, in consideration of the requirement of the contact resistance and the complexity of the manufacturing process, the upper surface 301 and one side surface 302 of the touch metal pattern 30 are used for contacting the touch electrode 5, and the side surface 302 contacting the touch electrode 5 faces the source/drain electrode.
Referring to fig. 7, the second insulating layer 6 is formed on the touch electrode 5, and also serves as a passivation layer in this embodiment. The material of the second insulating layer 6 is, for example, SiO2 or sion x.
And partially etching the second insulating layer 6 to form a second via hole 61, wherein the second via hole 61 penetrates through the second insulating layer 6 and is located in the first via hole 41. The second insulating layer 6 is partially located in the first via hole 41, and the second via hole 61 penetrates through the portion of the second insulating layer 6.
Referring to fig. 2, the pixel electrode 7 is formed on the second insulating layer 6, and the pixel electrode 7 is electrically contacted with the drain electrode 36 of the source and drain electrodes through the second via hole 61 to receive a TFT control signal. The touch electrode 5 is reused as a common electrode, and in the present embodiment, the touch electrode 5 is an integral surface electrode and only the area corresponding to the second via hole 61 is opened. The orthographic projection of the touch electrode 5 on the substrate 1 is at least partially overlapped with the orthographic projection of the pixel electrode 7 on the substrate 1, namely, the touch electrode 5 at least partially faces the pixel electrode 7, namely, an electric field can be formed between the touch electrode 5 and the pixel electrode 7, and liquid crystal is deflected under the influence of the electric field to form display.
In this embodiment, in one unit of the array substrate 100, the pixel electrode 7 corresponds to the second via hole 41 and the drain electrode 36 one to one, the touch metal pattern 30 corresponds to the second via hole 61 one to one, and the first via hole 41 corresponds to the second via hole 61 one to one.
Because the second via hole 61 is located in the first via hole 41, the structure between the second via hole 61 and the first via hole 41 is eliminated, the problem that the film above the structure is broken due to stress concentration can be avoided, the probability of poor film tearing is reduced, and the service life of the array substrate is prolonged. On the other hand, the original sizes of the first via holes 41 and the second via holes 61 are kept unchanged, and the thin film between the second via holes 61 and the first via holes 41 is eliminated, so that the first via holes 41 can be arranged more densely, and the pixel electrodes 7 are in one-to-one correspondence with the first openings 41, that is, the number of the pixel electrodes 7 in a unit area is larger, so that the pixel density of the array substrate can be improved, and the display effect is improved.
Of course, the pixel density is not suitable to be too high, because too high pixel density means that the density of the first vias 41 is too high, which may result in a small lateral dimension of the membrane between two adjacent first vias 41, and the membrane between two first vias 41 may also tear due to stress concentration. In the present embodiment, the dimension d of the first via hole 41 in the lateral direction X is 11.2mm to 15mm, so that the strength of the diaphragm between two adjacent first via holes 41 is ensured. The lateral dimension of the first via 41 is comparable to the sum of the lateral dimensions of the two vias shown in fig. 1. Preferably, the dimension d of the first via hole 41 in the transverse direction X is 12mm to 13mm, and at this dimension, a larger pixel density can be obtained, and at the same time, the film between two adjacent first via holes 41 has a sufficiently large transverse dimension to ensure strength, and the film is prevented from cracking due to stress concentration, so that the service life of the array substrate is prolonged.
In another aspect, the present invention further provides a display device, please refer to fig. 8, where the display device is, for example, a liquid crystal panel, and includes the array substrate 100 according to any of the foregoing embodiments, an opposite substrate 300 arranged in a box-to-box with the array substrate, and a liquid crystal 200 located between the array substrate 100 and the opposite substrate 300, where the array substrate 100 and the opposite substrate 300 are used to drive liquid crystal to deflect so as to display different images, and the opposite substrate 300 is internally provided with a Color Filter substrate (CF) including Color resistors of three colors, namely red, green, and blue, and respectively allowing light of corresponding colors to be emitted, so that the liquid crystal panel displays images of different colors.
In other embodiments, the display device may also be an electronic device having a display screen, such as a mobile phone, a tablet computer, a notebook computer, a television, a display, and a monitor. The display device may also comprise other structures, such as processing components, power supply components, etc., which are not described in detail herein.
In addition, the invention also provides a manufacturing method of the array substrate, which is used for manufacturing the array substrate of any one of the above embodiments. Referring to fig. 2 to 7, the manufacturing method includes:
step S1: a substrate 1 is provided.
Step S2: a buffer layer 2 is formed on the substrate 1.
Step S3: forming a thin film transistor 3 on the buffer layer 2, wherein the thin film transistor 3 comprises a source and drain electrode and a touch metal pattern 30, the source and drain electrode comprises a source electrode 35 and a drain electrode 36, and the source electrode 35, the drain electrode 36 and the touch metal pattern 30 are sequentially arranged along a transverse direction X. Since the thin film transistor 3 includes a plurality of layers, step S3 actually includes a plurality of sub-steps, i.e., a sub-step of forming the active layer 31, a sub-step of forming the gate insulating layer 32, a sub-step of forming the gate electrode 33, a sub-step of forming the interlayer insulating layer 34, and a sub-step of forming the source-drain electrode and the touch metal pattern 30.
Step S4: a first insulating layer 4 is formed on the thin film transistor 3, the first insulating layer 4 including a first via hole 41. For example, the first via hole 41 is formed by depositing SiO2 or siox by CVD (Chemical Vapor Deposition), then coating a photoresist, exposing the photoresist using a mask (mask) for forming a first insulating layer, and stripping the remaining photoresist after a developing process and an etching process.
Step S5: a touch electrode 5 is formed on the first insulating layer 4, and the touch electrode 5 is electrically connected to the touch metal pattern 30 through the first via hole 41. For example, an ITO thin film is sputtered on the first insulating layer 4, then a photoresist is coated, the photoresist is exposed using a mask (mask) for fabricating the touch electrode, and the remaining photoresist is stripped after a developing process and an etching process, thereby forming a pattern of the touch electrode.
Step S6: and forming a second insulating layer 6 on the touch electrode 5, wherein the second insulating layer 6 comprises a second via hole 61 positioned in the first via hole 41. Optionally, the second insulating layer 6 is fabricated by a process similar to that of the first insulating layer 4.
Step S7: and forming a pixel electrode 7 on the second insulating layer 6, wherein the pixel electrode 7 is electrically connected with the drain electrode 36 of the source and drain electrode through the second via hole 61. For example, an ITO thin film is sputtered on the second insulating layer 6, then a photoresist is coated, the photoresist is exposed using a mask (mask) for fabricating the pixel electrode, and the remaining photoresist is stripped after a developing process and an etching process, thereby forming a pattern of the pixel electrode.
In the invention, the second via hole is positioned in the first via hole, so that the structure between the second via hole and the first via hole is cancelled, the problem that a film above the part of structure is broken due to stress concentration can be avoided, the probability of poor film tearing is reduced, and the service life of the array substrate is prolonged. In addition, the touch electrode is electrically contacted with the upper surface and at least one side surface of the touch metal pattern, so that the contact area between the touch electrode and the touch metal pattern is increased, the contact resistance between the touch electrode and the touch metal pattern is favorably reduced, the problem of poor touch caused by overlarge contact resistance is avoided, the probability of poor touch is reduced, and the touch performance is improved.
Although the present invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. An array substrate is characterized by comprising a substrate, a thin film transistor formed on the substrate, a first insulating layer formed on the thin film transistor, a touch electrode formed on the first insulating layer, a second insulating layer formed on the touch electrode and a pixel electrode formed on the second insulating layer;
the array substrate further comprises a touch metal pattern, a first via hole and a second via hole, the first via hole penetrates through the first insulating layer, and the second via hole is located in the first via hole;
the touch electrode is electrically connected with the touch metal pattern through the first through hole, the thin film transistor comprises a source drain electrode, and the pixel electrode is electrically connected with the source drain electrode through the second through hole.
2. The array substrate of claim 1, wherein the source and drain electrodes comprise source and drain electrodes arranged in a transverse direction, and the first via hole has a transverse dimension of 11.2mm to 15 mm.
3. The array substrate of claim 2, wherein the first via has a lateral dimension of 12mm to 13 mm.
4. The array substrate of claim 1, wherein the touch metal pattern comprises an upper surface and a plurality of side surfaces connected to the upper surface, and the touch electrode is in electrical contact with the upper surface and at least one side surface of the touch metal pattern.
5. The array substrate of claim 4, wherein a side surface in contact with the touch electrode faces the source and drain electrodes.
6. The array substrate of claim 1, wherein the source drain electrode and the touch metal pattern are disposed on the same layer.
7. The array substrate of claim 6, wherein the second via extends through the second insulating layer, and the second insulating layer is partially within the first via.
8. The array substrate of claim 1, wherein the touch electrodes are multiplexed as a common electrode, and an orthogonal projection of the touch electrodes on the substrate at least partially coincides with an orthogonal projection of the pixel electrodes on the substrate.
9. A display device comprising the array substrate according to any one of claims 1 to 8.
10. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a buffer layer on the substrate;
forming a thin film transistor on the buffer layer, wherein the thin film transistor comprises a source drain electrode and a touch metal pattern;
forming a first insulating layer on the thin film transistor, the first insulating layer including a first via hole;
forming a touch electrode on the first insulating layer, wherein the touch electrode is electrically connected with the touch metal pattern through the first via hole;
forming a second insulating layer on the touch electrode, wherein the second insulating layer comprises a second via hole positioned in the first via hole;
and forming a pixel electrode on the second insulating layer, wherein the pixel electrode is electrically connected with the source and drain electrodes through the second through hole.
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| CN202010207266.9A CN111403421A (en) | 2020-03-23 | 2020-03-23 | Array substrate, display device and manufacturing method of array substrate |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140143046A (en) * | 2013-06-05 | 2014-12-15 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and manufacturing method of the same |
| CN104777692A (en) * | 2015-05-08 | 2015-07-15 | 厦门天马微电子有限公司 | Array substrate and preparation method and touch-control display panel |
| CN105630247A (en) * | 2016-02-02 | 2016-06-01 | 上海天马微电子有限公司 | Array substrate |
-
2020
- 2020-03-23 CN CN202010207266.9A patent/CN111403421A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140143046A (en) * | 2013-06-05 | 2014-12-15 | 엘지디스플레이 주식회사 | Thin film transistor array substrate and manufacturing method of the same |
| CN104777692A (en) * | 2015-05-08 | 2015-07-15 | 厦门天马微电子有限公司 | Array substrate and preparation method and touch-control display panel |
| CN105630247A (en) * | 2016-02-02 | 2016-06-01 | 上海天马微电子有限公司 | Array substrate |
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