CN111385965A

CN111385965A - Printed circuit board

Info

Publication number: CN111385965A
Application number: CN202010310181.3A
Authority: CN
Inventors: 马菲菲; 李敬
Original assignee: Goertek Optical Technology Co Ltd
Current assignee: Goertek Optical Technology Co Ltd
Priority date: 2020-04-17
Filing date: 2020-04-17
Publication date: 2020-07-07
Anticipated expiration: 2040-04-17
Also published as: CN111385965B

Abstract

The invention discloses a printed circuit board, which comprises conducting layers and insulating layers which are arranged in a stacked mode, wherein the insulating layer is arranged between any two adjacent conducting layers, the printed circuit board further comprises a differential line, a positive signal line and a negative signal line of the differential line are respectively and correspondingly arranged in the two conducting layers, a reference layer is arranged between the conducting layer provided with the positive signal line and the conducting layer provided with the negative signal line, and the positive signal line and the negative signal line are commonly referred to the reference layer. In the printed circuit board, the positive signal line and the negative signal line of the differential line have the same reference layer, so that the reference environments of the positive signal line and the negative signal line are consistent, the impedance of the differential line is continuous and consistent in time sequence, the quality of the differential line is improved, the advantages of the differential line can be fully exerted in actual line running, the signal quality of a transmission signal is improved, and the signal integrity of the printed circuit board is improved.

Description

Printed circuit board

Technical Field

The invention relates to the technical field of printed circuit board design, in particular to a printed circuit board.

Background

At present, electronic products are gradually becoming thinner and lighter, the updating speed of the electronic products is increasing, the functional requirements of the electronic products are also becoming richer and richer, and PCBs (Printed Circuit boards) are used as important electronic components of the electronic products, supports of the electronic components and carriers for electrical connection of the electronic components, the requirements on signal integrity and product reliability of the PCBs are also becoming higher and higher, and especially the signal integrity becomes a problem that needs to be concerned in the design of high-speed digital PCBs. The incomplete signals can cause the system to output incorrect data, so that the circuit works abnormally or even does not work completely, the PCB is used as an important electronic component in a product, and the quality of the PCB design is important to the performance of the product. Therefore, when designing a PCB, it is necessary to take the factors of signal integrity into full consideration and take effective control measures.

With the rapid increase in speed requirements in recent years, new bus protocols are continually evolving at higher speeds. Conventional bus protocols have been unable to meet the requirements. The serial bus is preferred by many designers due to better anti-interference performance, fewer signal lines and higher speed, and the serial bus is most in a differential signal mode, and the quality of a differential line plays a crucial role in signal transmission quality, so that when designing a PCB Layout, how to improve the integrity of PCB signals by improving the quality of the differential line becomes an urgent problem to be solved in the current PCB design industry.

Disclosure of Invention

The invention mainly aims to provide a printed circuit board, aiming at solving the technical problem of improving the integrity of PCB signals by improving the quality of differential lines.

In order to achieve the above object, the present invention provides a printed circuit board, which includes conductive layers and insulating layers arranged in a stacked manner, wherein the insulating layer is disposed between any two adjacent conductive layers, the printed circuit board further includes a differential line, a positive signal line and a negative signal line of the differential line are respectively and correspondingly disposed in two of the conductive layers, a reference layer is disposed between the conductive layer provided with the positive signal line and the conductive layer provided with the negative signal line, and the positive signal line and the negative signal line refer to the reference layer together.

Preferably, the conductive layer provided with the positive signal line and the conductive layer provided with the negative signal line are both arranged adjacent to the reference layer, and the positive signal line and the negative signal line are arranged in a right-to-right manner.

Preferably, the thickness of the conductive layer provided with the positive signal line is the same as the thickness of the conductive layer provided with the negative signal line, and the thicknesses of the two insulating layers adjacent to the reference layer are the same.

Preferably, the reference layer is a reference ground layer or a power supply layer.

Preferably, the reference layer is a reference ground line, the reference ground line is arranged over against the positive signal line and the negative signal line, and the width of the reference ground line is greater than the width of the positive signal line and the width of the negative signal line.

Preferably, the width of the positive signal line and the width of the negative signal line are both W, the width of the reference ground line is B, and B is larger than or equal to 2W.

Preferably, first ground wires are arranged on two sides of the positive signal wire, and the first ground wires and the positive signal wire are arranged at intervals and in the same layer; and second ground wires are arranged on two sides of the negative signal wire, and are arranged at intervals and in the same layer with the negative signal wire.

Preferably, the first ground wire is annularly wound outside the positive signal wire; the second ground wire is annularly wound outside the negative signal wire.

Preferably, the first ground wire and the positive signal wire are arranged adjacently, and the width of the first ground wire and the distance between the first ground wire and the positive signal wire are both greater than or equal to the width of the positive signal wire; the second ground wire is arranged adjacent to the negative signal wire, and the width of the second ground wire and the distance between the second ground wire and the negative signal wire are both larger than or equal to the width of the negative signal wire.

Preferably, the length of the positive signal line and the length of the negative signal line coincide.

In the technical scheme of the invention, the printed circuit board arranges the positive signal line of the differential line in one of the conductive layers, arranges the negative signal line in the other conductive layer corresponding to the positive signal line, arranges the reference layer between the conductive layer provided with the positive signal line and the conductive layer provided with the negative signal line, and leads the positive signal line and the negative signal line of the differential line to jointly reference the reference layer, thereby leading the positive signal line and the negative signal line to have the same reference layer, ensuring the consistent reference environment of the positive signal line and the negative signal line, leading the impedance of the differential line to be continuous and consistent in time sequence, improving the quality of the differential line, ensuring that the advantages of the differential line can be fully exerted in actual line running, improving the signal quality of transmission signals, and further improving the signal integrity of the printed circuit board.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a printed circuit board according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a printed circuit board according to another embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a printed circuit board according to another embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a printed circuit board according to yet another embodiment of the present invention;

FIG. 5 is a schematic view of a printed circuit board according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of differential traces of a printed circuit board according to an embodiment of the invention;

FIG. 7 is a structural distribution diagram of a printed circuit board with a six-layer structure according to an embodiment of the present invention;

fig. 8 is a structural distribution diagram of the printed circuit board in an eight-layer stacked structure according to an embodiment of the invention.

The reference numbers illustrate:

reference numerals	Name (R)	Reference numerals	Name (R)
				100	Printed circuit board	113a	Reference formation
10	Conductive layer	113b	Reference ground wire
				11	Differential line	12	First ground wire
111	Positive signal line	13	Second ground wire
				112	Negative signal line	20	Insulating layer
113	Reference layer	30	Via hole

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

The invention provides a printed circuit board.

As shown in fig. 1 to 5, in the present embodiment, the printed circuit board 100 includes conductive layers 10 and insulating layers 20 arranged in a stacked manner, and the insulating layer 20 is disposed between any two adjacent conductive layers 10, and it is understood that the conductive layers 10 and the insulating layers 20 are arranged in a stacked and crossed manner, that is, the insulating layer 20 is disposed between any two adjacent conductive layers 10, and the conductive layer 10 is disposed between any two adjacent insulating layers 20. The printed circuit board 100 of the present embodiment further includes a differential line 11, the positive signal line 111 and the negative signal line 112 of the differential line 11 are respectively and correspondingly disposed in two of the conductive layers 10, a reference layer 113 is disposed between the conductive layer 10 disposed with the positive signal line 111 and the conductive layer 10 disposed with the negative signal line 112, and the reference layer 113 is commonly referred to by the positive signal line 111 and the negative signal line 112.

Specifically, the positive signal line 111 of the differential line 11 is disposed in one of the conductive layers 10, the negative signal line 112 of the differential line 11 is disposed in the other conductive layer 10 corresponding to the positive signal line 111, and the reference layer 113 is disposed between the two conductive layers 10. It should be noted that the cross-section lines in fig. 1 to 5 are only used to distinguish the structure from other non-cross-section line structures. For the sake of convenience of distinction, in the following embodiments, the positive signal line 111, the negative signal line 112, the reference layer 113, the first ground line 12, and the second ground line 13 are represented by hatching.

In designing the printed circuit board 100, the overall structure of the printed circuit board 100 and the thicknesses of the respective conductive layers 10 and the respective insulating layers 20 are determined. As shown in FIGS. 7 and 8, the printed circuit board 100 is designed to have a N-layer laminated structure, which includes, from TOP to bottom, an L1 layer, an L2 layer, an L3 layer, a … LN-2 layer, an LN-1 layer, and an LN layer, wherein N is generally an even number, preferably N is equal to or greater than 6, the L1(TOP) layer and the LN (BOTTOM) layer are surface layers for mounting components, and the other layers except the L1 layer and the LN layer are inner layers. As shown in fig. 7, when the printed circuit board 100 is designed as a six-layer stacked structure, the printed circuit board includes, in order from TOP to BOTTOM, an L1(TOP) layer, an L2(GND) layer, an L3(SIG) layer, an L4(SIG) layer, an L5(POWER) layer, and an L6(BOTTOM) layer. As shown in fig. 8, when the printed circuit board 100 is provided as an eight-layer laminated structure, there are a L1(TOP) layer, a L2(GND) layer, a L3(SIG) layer, a L4(GND) layer, a L5(SIG) layer, a L6(POWER) layer, a L7(GND) layer, and a L8(BOTTOM) layer in this order from TOP to BOTTOM. The thicknesses of the conductive layers 10 and the insulating layers 20 may be set according to actual needs. In selecting layers for the positive signal line 111 and the negative signal line 112 of the differential line 11, it is preferable to dispose the positive signal line 111 and the negative signal line 112 in an inner layer. In the present embodiment, the printed circuit board 100 has an eight-layer structure, and the positive signal line 111 and the negative signal line 112 are preferably disposed in the L3 layer and the L5 layer, respectively.

As shown in fig. 1 and 3, the positive signal line 111 of the differential line 11 is disposed in the L3 layer and the negative signal line 112 is disposed in the L5 layer, or, as shown in fig. 2, the negative signal line 112 of the differential line 11 is disposed in the L3 layer and the positive signal line 111 of the differential line 11 is disposed in the L5 layer. The L4 layer is arranged between the L3 layer and the L5 layer, the reference layer 113 is arranged in the L4 layer, the reference layer 113 is commonly referred to by the positive signal line 111 and the negative signal line 112 of the differential line 11, so that the positive signal line 111 and the negative signal line 112 have the same reference layer 113, the reference environments of the positive signal line 111 and the negative signal line 112 are ensured to be consistent, the impedance of the differential line 11 is enabled to be consistent continuously and timely, the quality of the differential line 11 is improved, the advantage of differential wiring in actual wiring is ensured to be fully played, the signal quality of transmission signals is improved, and the signal integrity of the printed circuit board 100 is improved.

It can be understood that the distribution levels of the positive signal lines 111 and the negative signal lines 112 of the differential lines 11 are not unique and can be adjusted adaptively according to actual needs, in a preferred embodiment, the conductive layer 10 provided with the positive signal lines 111 and the conductive layer 10 provided with the negative signal lines 112 are both disposed adjacent to the reference layer 113, so that the reference layer 113 is adjacent to both the conductive layer 10 where the positive signal lines 111 are located and the conductive layer 10 where the negative signal lines 112 are located, and the positive signal lines 111 and the negative signal lines 112 are disposed opposite to each other, as shown in fig. 1 to 5, the positive signal lines 111 and the negative signal lines 112 are symmetrically disposed above and below the reference layer 113, so as to further improve the consistency of the reference environments of the positive signal lines 111 and the negative signal lines 112, and further improve the signal integrity of the printed circuit board 100.

Further, the thickness of the conductive layer 10 provided with the positive signal line 111 coincides with the thickness of the conductive layer 10 provided with the negative signal line 112, and coincides with the thickness of the two insulating layers 20 adjacent to the reference layer. As shown in fig. 1 to 5, the thickness of the L3 layer is the same as that of the L5 layer, and the thickness of the insulating layer 20 between the L3 layer and the L4 layer is the same as that of the insulating layer 20 between the L4 layer and the L5 layer, so as to effectively improve the consistency of the reference environments of the positive signal line 111 and the negative signal line 112, and further effectively improve the signal integrity of the printed circuit board 100. It is preferable that the thickness of the insulating layer 20 between the L2 layer and the L3 layer is made uniform with the thickness of the insulating layer 20 between the L5 and the L6, and more preferably, the thickness of each insulating layer 20 may be made uniform to provide a more uniform reference environment for the positive signal line 111 and the negative signal line 112.

In an embodiment, as shown in fig. 1, fig. 2, fig. 4, and fig. 5, the reference layer 113 is a reference ground layer 113a, and the reference ground layer 113a is entirely copper-plated, so as to completely isolate the positive signal line 111 and the negative signal line 112 of the differential line 11, prevent signals sent by the positive signal line 111 and the negative signal line 112 from being interfered by an intermediate wiring, and optimize a signal transmission environment of the differential line 11. In another embodiment, the reference layer 113 may also be a power layer, and it is understood that the positive signal line 111 and the negative signal line 112 refer to the same power source of the power layer to ensure consistency of the reference environment.

In yet another embodiment, as shown in fig. 3, the reference layer 113 is a reference ground line 113b, the reference ground line 113b is disposed opposite to the positive signal line 111 and the negative signal line 112, and the width of the reference ground line 113b is greater than the widths of the positive signal line 111 and the negative signal line 112. Specifically, the L4 layer is provided with a reference ground line 113b, the reference ground line 113b is located between the positive signal line 111 and the negative signal line 112 and is directly opposite to the positive signal line 111 and the negative signal line 112, and the width of the reference ground line 113b is greater than the widths of the positive signal line 111 and the negative signal line 112, so as to ensure that the reference environment consistency of the positive signal line 111 and the negative signal line 112 is ensured while the isolation effect is exerted on the positive signal line 111 and the negative signal line 112 of the differential line 11.

Preferably, the width of the positive signal line 111 and the width of the negative signal line 112 are both W, the width of the reference ground line 113B is B, B ≧ 2W, the reference ground line 113B has a sufficient width with respect to the positive signal line 111 and the negative signal line 112 to ensure the stability of the reference ground line 113B in isolation of the positive signal line 111 and the negative signal line 112, and the width of the positive signal line 111 and the width of the negative signal line 112 are the same to improve the impedance continuity and timing consistency of the differential line 11.

In this embodiment, the first ground lines 12 are disposed on two sides of the positive signal line 111, and the first ground lines 12 and the positive signal line 111 are spaced and disposed in the same layer; the second ground lines 13 are disposed on both sides of the negative signal line 112, and the second ground lines 13 are spaced from the negative signal line 112 and disposed in the same layer. As shown in fig. 1 and fig. 3, the positive signal line 111 is located in the L3 layer, the negative signal line 112 is located in the L5 layer, the first ground wire 12 spaced apart from the positive signal line 111 is disposed in the L3 layer, and the second ground wire 13 spaced apart from the negative signal line 112 is disposed in the L5 layer, the first ground wire 12 isolates the positive signal line 111 from other wires disposed in the same layer, and the second ground wire 13 isolates the negative signal line 112 from other wires disposed in the same layer, so that the high-speed signals transmitted by the positive signal line 111 and the negative signal line 112 are not interfered by the other wires on both sides, thereby providing a transmission environment with less interference for the differential line 11, ensuring correct transmission of high-speed signals, improving signal quality of the transmission signals, and further improving signal integrity of the printed circuit board 100.

Specifically, the first ground wire 12 is annularly wound outside the positive signal wire 111; the second ground line 13 is annularly wound outside the negative signal line 112. In a preferred embodiment, the first ground wire 12 is similar to a closed loop structure and surrounds the positive signal wire 111, so as to shield almost all of the periphery of the positive signal wire 111 and provide a transmission environment with less interference for the positive signal wire 111, and the second ground wire 13 is similar to a closed loop structure and surrounds the negative signal wire 112, so as to shield almost all of the periphery of the negative signal wire 112 and provide a transmission environment with less interference for the negative signal wire 112, thereby further improving the signal integrity of the printed circuit board 100.

In this embodiment, the first ground traces 12 are disposed adjacent to the positive signal line 111, and both the width of the first ground traces 12 and the distance between the first ground traces 12 and the positive signal line 111 are greater than or equal to the width of the positive signal line 111; the second ground lines 13 are disposed adjacent to the negative signal lines 112, and the width of the second ground lines 13 and the distance between the second ground lines 13 and the negative signal lines 112 are both greater than or equal to the width of the negative signal lines 112.

Taking the first ground wire 12 as an example, the first ground wire 12 is disposed adjacent to the positive signal wire 111, and there is no other wire between the first ground wire 12 and the positive signal wire 111, so that not only signals of other wires are prevented from interfering with the signal of the positive signal wire 111, but also signals of the positive signal wire 111 are prevented from interfering with signals of other wires, that is, the other wires and the positive signal wire 111 do not interfere with each other, and the transmission environments of the positive signal wire 111 and the other wires are further optimized. The width of the first ground wire 12 is W1, the distance between the first signal wire and the positive signal wire 111 is d, and the width of the positive signal wire 111 is W, wherein W1 is more than or equal to W, and d is more than or equal to W. In the preferred embodiment, d is greater than or equal to W1, which improves the isolation effect on the alignment signal line 111, achieves good isolation effect, and further improves the signal integrity of the printed circuit board 100. The dimensions of the second ground lines 13 and the first ground lines 12, the positions and layout relationships between the second ground lines 13 and the negative signal lines 112 are the same as those between the first ground lines 12 and the positive signal lines 111, and the description thereof is omitted here.

In one embodiment, as shown in fig. 4, the printed circuit board 100 includes two differential lines 11, wherein the positive signal line 111 of one differential line 11 is disposed in the L3 layer, the negative signal line 112 is disposed in the L5 layer, the negative signal line 112 of the other differential line 11 is disposed in the L3 layer, the positive signal line 111 is disposed in the L5 layer, and the two differential lines are spaced side by side. In the case where the space does not allow the first ground lines 12 to be laid on both sides of the positive signal lines 111 and the second ground lines 13 to be laid on both sides of the negative signal lines 112, it is necessary to make the distance between the positive signal lines 111 and the negative signal lines 112 or between the positive signal lines and the negative signal lines 13. As shown in FIG. 4, the distance between the positive signal line 111 and the negative signal line 112 disposed in the same layer is D, preferably, D ≧ 3W.

In this embodiment, the length of the positive signal line 111 is identical to the length of the negative signal line 112. Specifically, as shown in fig. 6, the source end and the terminal end of the differential line 11 are both at the L1 level, and during wiring, the positive signal line 111 of the differential line 11 is switched from the source end node to the L3 level through the via 30 at the left end, and after being arranged at the L3 level in the left-right direction, the positive signal line 111 is switched from the L3 level to the terminal node at the L1 level through the via 30 at the right end; the negative signal line 112 is switched from the source-end node to the L5 layer through the via 30 at the left end, and after being routed in the L5 layer in the left-right direction, the positive signal line 111 is switched from the L5 layer to the terminal node of the L1 layer through the via 30 at the right end. The positive signal line 111 arranged in the L3 layer and the negative signal line 112 arranged in the L5 layer are arranged in an up-down alignment manner, the line length of the positive signal line 111 arranged in the L3 layer is consistent with that of the negative signal line 112 arranged in the L5 layer, in addition, the left end through hole 30 of the positive signal line 111 and the left end through hole 30 of the negative signal line 112 are symmetrically arranged, the right end through hole 30 of the positive signal line 111 and the right end through hole 30 of the negative signal line 112 are symmetrically arranged, and the height difference between the L3 layer and the L5 layer can be basically ignored, so that the total length of the positive signal line 111 and the negative signal line 112 is basically consistent, the consistency of signal timing sequence is ensured, and the advantage of differential signals is better realized.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. The utility model provides a printed circuit board, is including the conducting layer and the insulating layer of range upon range of arrangement, arbitrary adjacent two be provided with between the conducting layer the insulating layer, its characterized in that, printed circuit board still includes the difference line, the positive signal line and the negative signal line of difference line correspond respectively to be set up wherein two in the conducting layer, be provided with the positive signal line the conducting layer with be provided with the negative signal line have the reference layer between the conducting layer, the positive signal line with the negative signal line refers to jointly the reference layer.

2. The printed circuit board of claim 1, wherein the conductive layer provided with the positive signal line and the conductive layer provided with the negative signal line are both disposed adjacent to the reference layer, the positive signal line and the negative signal line being disposed directly opposite.

3. The printed circuit board of claim 2, wherein the thickness of the conductive layer on which the positive signal line is provided is identical to the thickness of the conductive layer on which the negative signal line is provided, and the thickness of two of the insulating layers adjacent to the reference layer is identical.

4. The printed circuit board of claim 1, wherein the reference layer is a reference ground layer or a power layer.

5. The printed circuit board of claim 1, wherein the reference layer is a reference ground line, the reference ground line is disposed opposite to the positive signal line and the negative signal line, and a width of the reference ground line is greater than widths of the positive signal line and the negative signal line.

6. The printed circuit board of claim 5, wherein the width of the positive signal line and the width of the negative signal line are both W, the width of the reference ground line is B, and B ≧ 2W.

7. The printed circuit board according to any one of claims 1 to 6, wherein first ground traces are disposed on both sides of the positive signal line, the first ground traces being spaced apart from the positive signal line and disposed in the same layer; and second ground wires are arranged on two sides of the negative signal wire, and are arranged at intervals and in the same layer with the negative signal wire.

8. The printed circuit board of claim 7, wherein said first ground trace is disposed annularly around said positive signal trace; the second ground wire is annularly wound outside the negative signal wire.

9. The printed circuit board of claim 7, wherein said first ground traces are disposed adjacent to said positive signal lines, and a width of said first ground traces and a distance between said first ground traces and said positive signal lines are both greater than or equal to a width of said positive signal lines; the second ground wire is arranged adjacent to the negative signal wire, and the width of the second ground wire and the distance between the second ground wire and the negative signal wire are both larger than or equal to the width of the negative signal wire.

10. The printed circuit board of any of claims 1-6, wherein the length of the positive signal line and the length of the negative signal line are the same.