CN111384034B - Semiconductor chip, semiconductor wafer and manufacturing method thereof - Google Patents
Semiconductor chip, semiconductor wafer and manufacturing method thereof Download PDFInfo
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- CN111384034B CN111384034B CN201811643537.4A CN201811643537A CN111384034B CN 111384034 B CN111384034 B CN 111384034B CN 201811643537 A CN201811643537 A CN 201811643537A CN 111384034 B CN111384034 B CN 111384034B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 148
- 239000002184 metal Substances 0.000 claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000000463 material Substances 0.000 claims abstract description 57
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- 239000007769 metal material Substances 0.000 claims description 96
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
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- 229910052737 gold Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
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- 239000010937 tungsten Substances 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a semiconductor chip, a semiconductor wafer and a manufacturing method thereof, wherein the semiconductor chip comprises a substrate, the substrate comprises a first side surface and a second side surface which are opposite; a source electrode of the semiconductor chip arranged on the first side surface; the through hole is arranged on the substrate, the arrangement position of the through hole corresponds to the position of the source electrode, and the through hole penetrates from the second side face to the first side face; a seed metal layer formed on the second side and electrically contacted with the source electrode through the through hole; a back metal layer formed based on the seed metal layer, the back metal layer covering a portion of the seed metal layer; and the protective material layer at least covers the edge of the seed metal layer which is not covered by the back metal layer. The protective material layer is wrapped at the edge position of the seed metal layer which is not covered by the back metal layer, so that the seed metal layer is prevented from curling.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor chip, a semiconductor wafer, and a method for manufacturing the semiconductor chip and the semiconductor wafer.
Background
Referring to fig. 1, in a usage environment of a transistor-like semiconductor device generally including a source S, a drain D, a gate G and a substrate B, grounding is often required for the source and the substrate. In some embodiments, to improve the gain of the semiconductor device and reduce the grounding inductance, a through-substrate via is formed in the substrate, and then a metal is filled in the via and contacts the source of the semiconductor device, so as to connect the source and a back metal layer grounded on the back of the substrate, thereby reducing the inductance from the source to the ground. In this manner, a seed metal layer extending through the via hole to electrically contact the source is typically formed on the back surface of the substrate, and then a back metal layer for grounding is formed on the seed metal layer. In the conventional manufacturing method, the problem of edge curl of the seed metal layer may occur, and particularly, when the seed metal layer includes at least two metal material layers and forms an undercut structure (as shown in fig. 2), the problem of edge curl of the seed metal layer is easily generated, thereby affecting the subsequent packaging process of the semiconductor chip.
Disclosure of Invention
In order to overcome at least the above-mentioned deficiencies in the prior art, it is an object of the present application to provide a semiconductor chip comprising:
a substrate comprising opposing first and second sides;
a source electrode of the semiconductor chip arranged on the first side surface;
the through hole is arranged on the substrate, the arrangement position of the through hole corresponds to the position of the source electrode, and the through hole penetrates from the second side surface to the first side surface;
a seed metal layer formed on the basis of the second side surface and electrically contacted with the source electrode through the through hole;
a back metal layer formed based on the seed metal layer, the back metal layer covering a portion of the seed metal layer;
and the protective material layer at least covers the edge of the seed metal layer which is not covered by the back metal layer.
Optionally, the protective material layer covers at least the seed metal layer uncovered by the back metal layer.
Optionally, in the above semiconductor chip, the seed metal layer includes at least two different metal material layers;
the at least two different metal material layers form an undercut structure on the second side surface;
the protective material layer at least covers the edge of the metal material layer which is farthest away from the second side surface in the metal material layer forming the undercut structure.
Optionally, in the semiconductor chip, a portion of the protection material layer is filled in the undercut structure and is in contact with a metal material layer farthest from the second side surface in the metal material layer forming the undercut structure. Optionally, the protective material layer further covers a side surface of the back metal layer, where the side surface is a side surface formed between a surface of the back metal layer close to the seed metal layer and a surface far away from the seed metal layer.
Optionally, the protective material layer further covers a part of the surface of the back metal layer away from the seed metal layer.
Alternatively, in the above semiconductor chip, the protective material layer is formed of a high thermal conductive material.
Optionally, in the semiconductor chip, the substrate includes a substrate layer and a semiconductor epitaxial layer.
Another object of the present application is to provide a semiconductor wafer including a plurality of the semiconductor chips provided in the present application.
Optionally, in the semiconductor wafer, the seed metal layers of different semiconductor chips are spaced from each other by dicing streets.
Another object of the present application is to provide a method for manufacturing a semiconductor wafer, the method comprising:
providing a substrate, wherein the substrate comprises a first side and a second side opposite to the first side;
forming source electrodes of a plurality of semiconductor chips on the first side of the substrate;
manufacturing and forming a plurality of through holes penetrating through the substrate at positions of the substrate corresponding to the source electrodes of the plurality of semiconductor chips respectively;
forming a seed metal layer electrically contacting the source electrode through the via hole based on the second side surface;
forming a back side metal layer covering a portion of the seed metal layer based on the seed metal layer;
etching the seed metal layer to form a scribing channel between two adjacent semiconductor chips;
and forming a protective material layer at least at the edge of the seed metal layer uncovered by the back metal layer.
Optionally, the method further comprises:
forming other portions of the semiconductor chip based on the first side;
and attaching a substrate support sheet to one side of the substrate where the source electrode is manufactured.
Optionally, forming a seed metal layer electrically contacting the source electrode through the via hole based on the second side surface includes:
sequentially forming at least two different metal material layers based on the second side;
wherein the at least two different metal material layers together form the seed metal layer, and the at least two different metal material layers form an undercut structure on the second side; the protective material layer at least covers the edge of the metal material layer which is farthest away from the second side surface in the metal material layer forming the undercut structure.
Optionally, a portion of the protection material layer fills the undercut structure and contacts a metal material layer farthest from the second side surface in the metal material layer forming the undercut structure.
Compared with the prior art, the method has the following beneficial effects:
according to the semiconductor chip, the semiconductor wafer and the manufacturing method thereof, the protective material layer is wrapped and covered at the edge position of the seed metal layer which is not covered by the back metal layer, so that the seed metal layer is prevented from being curled.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic circuit connection diagram of a semiconductor device;
FIG. 2 is a schematic illustration of a prior art seed metal layer curl;
FIG. 3 is a schematic view of a semiconductor wafer according to an embodiment of the present disclosure;
fig. 4-11 are schematic cross-sectional views of semiconductor chips provided in embodiments of the present application;
FIG. 12 is a schematic flow chart illustrating a method for fabricating a semiconductor wafer according to an embodiment of the present disclosure;
fig. 13-21 are schematic views illustrating a manufacturing process of a semiconductor wafer according to an embodiment of the present disclosure.
Icon: 10-a semiconductor chip; 20-scribing lanes; 11-a substrate; 111-a substrate layer; 112-epitaxial layer; 12-a source electrode; 19 a-a gate; 19 b-a drain electrode; 201-a binder; 200-a substrate support sheet; 210-a mask layer; 220-patterning a protective layer; 230-patterning the mask layer; 13-a through hole; 14-a conductive material; 15-seed metal layer; 151-a first metallic material layer; 152-a second metallic material layer; 153-a third metallic material layer; 240-photoresist; 16-back side metal layer; 18-protective material layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is further noted that, unless expressly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 2, the inventors have found that the edge of the seed metal layer of the conventional semiconductor device has a problem of curling and separating from the substrate, which seriously affects the subsequent packaging process of the semiconductor chip.
In view of the above, the present embodiment provides a semiconductor chip, a semiconductor wafer and a method for manufacturing the same to solve the above problems, and the solution provided by the present embodiment is described in detail below. It should be noted that the process of finding the above-mentioned problems and the solution to the above-mentioned problems are all the result of the inventor's creative thinking, and therefore should be regarded as the contribution to the creativity of the present application.
Referring to fig. 3, the semiconductor device provided in this embodiment may be manufactured on the semiconductor wafer shown in fig. 3. A plurality of semiconductor chips 10 can be produced on the basis of a semiconductor wafer, the semiconductor chips 10 being spaced apart from one another by dicing streets 20. A plurality of semiconductor chips 10 are obtained after dicing the semiconductor wafer along the dicing streets 20. In the present embodiment, the semiconductor chip 10 may be a High Electron Mobility Transistor (HEMT) made of a gallium nitride material, or a semiconductor chip made of another material.
Alternatively, in the present embodiment, the plurality of semiconductor chips 10 may be arranged in a matrix on the plane of the semiconductor wafer. One or one segment of scribe lane 20 is provided between any adjacent two semiconductor chips 10. As shown in fig. 3, two adjacent scribe lanes 20 in the same extending direction may be connected to each other, and two adjacent scribe lanes 20 in different extending directions may be disposed to cross each other.
Referring to fig. 4, fig. 4 is a partial cross-sectional view of the semiconductor wafer including a plurality of semiconductor chips 10, which is cut along the direction a-a shown in fig. 3.
The source electrode 12 of the semiconductor chip 10 is provided on one surface (the lower surface shown in fig. 4) of the substrate 11, and in the present embodiment, the surface on which the source electrode 12 of the semiconductor chip 10 is provided is a first side surface of the substrate 11, and the surface (the upper surface shown in fig. 4) of the substrate 11 opposite to the first side surface is a second side surface of the substrate 11.
It should be understood that other parts of the semiconductor chip 10, such as the gate electrode 19a and the drain electrode 19b of the semiconductor chip 10 shown in fig. 5, may be provided on the first side of the substrate 11 in addition to the source electrode 12 of the semiconductor chip 10.
Optionally, in an implementation manner of this embodiment, the substrate 11 may include a substrate layer 111 and a semiconductor epitaxial layer 112, where a layer close to the source 12 of the semiconductor chip 10 is the semiconductor epitaxial layer 112, and a layer far away from the source 12 is the substrate layer 111. The substrate layer 111 may be formed of one of silicon, sapphire, silicon carbide, and gallium arsenide. The semiconductor epitaxial layer 112 may be made of a material such as nitride, for example, formed of one or both of gallium nitride and aluminum gallium nitride.
Optionally, in another embodiment of this embodiment, the substrate 11 may also only include the substrate layer 111.
In this embodiment, the substrate 11 is provided with a through hole 13, the through hole 13 may be disposed at a position corresponding to the source electrode 12, and the through hole 13 may penetrate the substrate 11 from the second side surface to the first side surface. When the base 11 includes the substrate layer 111 and the epitaxial layer 112, the through hole 13 penetrates the substrate layer 111 and the semiconductor epitaxial layer 112. The cross-sectional shape of the through-hole 13 may be any shape such as a circle or an ellipse, and the cross-sectional shape of the through-hole 13 may be any shape such as a trapezoid.
In the present embodiment, a seed metal layer 15 is formed on the second side of the substrate 11, and the seed metal layer 15 covers the second side and is electrically contacted with the source electrode 12 through the via hole 13. The seed metal layers 15 of different semiconductor chips 10 are spaced from each other by dicing streets 20.
A back metal layer 16 is formed on the seed metal layer 15, and the back metal layer 16 covers a part of the seed metal layer 15. A protective material layer 18 covering at least the edge of the seed metal layer 15 not covered by the back metal layer 16 and joined to the second side of the substrate 11, thereby enhancing the stability of the edge of the seed metal layer 15 and preventing the edge of the seed metal layer 15 from curling. Preferably, referring to fig. 6, the protective material layer 18 covers at least the portion of the seed metal layer 15 not covered by the back metal layer 16.
Optionally, referring to fig. 4 again, in an implementation manner of the present embodiment, the seed metal layer 15 extends from the second side surface to electrically contact the source 12 through the via 13.
Further, since the seed metal layer 15 and the back metal layer 16 have different coefficients of expansion and the seed metal layer 15 and the back metal layer 16 have different coefficients of expansion from the substrate 11, in this embodiment, in order to prevent stress caused by the difference in the coefficients of thermal expansion of the different materials from being not relieved, the portions of the seed metal layer 15 and the back metal layer 16 extending into the through-holes 13 are not filled with the through-holes 13, so that a certain space is left in the through-holes 13.
Referring to fig. 7, in another embodiment of the present invention, the via hole 13 is filled with a conductive material 14 electrically contacting the source 12, and the seed metal layer 15 is in contact with the conductive material 14 so as to be electrically connected to the source 12. The conductive material 14 may be, but is not limited to, a metal material such as copper, titanium, nickel, tungsten, platinum, and gold.
Optionally, in this embodiment, the at least two different metal material layers form an undercut (undercut) structure on the second side surface, and in order to prevent the edge of the seed metal layer 15 from curling due to the undercut structure, in this embodiment, the protective material layer 18 covers at least the edge of the metal material layer farthest from the second side surface, among the metal material layers forming the undercut structure.
Taking the example that the seed metal layer 15 includes two metal material layers, referring to fig. 8, the seed metal layer 15 may include a first metal material layer 151 and a second metal material layer 152, the first metal material layer 151 is formed on the basis of the second side surface, and the second metal material layer 152 is formed on the basis of the first metal material layer 151 and is located between the first metal material layer 151 and the back metal layer 16.
Alternatively, the textures of the first metallic material layer 151 and the second metallic material layer 152 may be selected from, but not limited to, different two of titanium, nickel, tungsten, platinum, and gold. The back metal layer 16 may be, but is not limited to, at least one of gold, copper, and gold-tin alloy.
In order to prevent the edge of the second metal material layer 152 from curling due to the undercut structure formed by the second metal material layer 152 and the first metal material layer 151 on the second side, in this embodiment, the protective material layer 18 covers at least a portion of the edge of the second metal material layer 152 and is bonded to the second side of the substrate 11. The protective material layer 18 may also cover at least the portion of the second metal material layer 152 not covered by the back metal layer 16 and be bonded to the second side of the substrate 11.
Further, a portion of the protection material layer 18 may fill the undercut structure and contact the metal material layer farthest from the second side surface in the metal material layer forming the undercut structure. That is, the protective material layer 18 in the structure is in direct contact with at least the second metallic material layer 152, the first metallic material layer 151 and the substrate 11; the thickness of the layer of protective material 18, which is located between the second layer of metallic material 152 and the substrate 11, matches the thickness of the first layer of metallic material 151, which is covered on the second side.
Taking the example that the seed metal layer 15 includes more than two metal material layers, referring to fig. 9, the seed metal layer 15 may include a first metal material layer 151, a second metal material layer 152 and a third metal material layer 153, wherein the first metal material layer 151 is formed based on the second side surface, the second metal material layer 152 is formed based on the first metal material layer 151, and the third metal material layer 153 is formed based on the second metal material layer 152 and is located between the second metal material layer 152 and the back metal layer 16.
Alternatively, the textures of the first, second, and third metallic material layers 151, 152, and 153 may be selected from, but not limited to, different three of titanium, nickel, tungsten, platinum, and gold. The back metal layer 16 may be, but is not limited to, at least one of gold, copper, and gold-tin alloy.
If the third metal material layer 153 only partially covers the second metal material layer 152, and the second metal material layer 152 and the first metal material layer 151 form an undercut structure above the second side, the second metal material layer 152 is the metal material layer farthest from the second side in the metal material layers forming the undercut structure, and in this embodiment, the protection material layer 18 at least covers the edge portion of the second metal material layer 152 and is bonded to the second side of the substrate 11. The protective material layer 18 may further cover at least a portion of the second metal material layer 152 not covered by the third metal material layer 153, and is bonded to the second side of the substrate 11.
Further, a portion of the protection material layer 18 may fill the undercut structure and contact the metal material layer farthest from the second side surface in the metal material layer forming the undercut structure. That is, the protective material layer 18 in the structure is in direct contact with at least the second metallic material layer 152, the first metallic material layer 151 and the substrate 11; the thickness of the layer of protective material 18, which is located between the second layer of metallic material 152 and the substrate 11, matches the thickness of the first layer of metallic material 151, which is covered on the second side.
It should be noted that, in the above example, if an undercut structure is formed between the third metal material layer 153 and the substrate 11, the third metal material layer 153 is a metal material layer forming the most basic second side of the metal material layers forming the undercut structure, and the protective material layer 18 at least covers a portion of the edge of the third metal material layer 153 and is bonded to the second side of the substrate 11.
Alternatively, in the present embodiment, the protective material layer 18 may be made of a metal or non-metal material having high thermal conductivity. In this way, the difference in heating between the seed metal layer 15 covered by the protective material layer 18 and other parts can be reduced.
In this embodiment, the protective material layer 18 may also cover a side surface of the back metal layer 16, where the side surface is a side surface formed between a surface of the back metal layer 16 close to the seed metal layer 15 and a surface far from the seed metal layer 15. For example, the area of the surface of the back metal layer 16 contacting the seed metal layer 15 is larger than the area of the surface of the back metal layer 16 away from the seed metal layer 15, so that the back metal layer 16 forms a slope on the side close to the protective material layer 18. In one embodiment, the protective material layer 18 may also extend from the edge of the seed metal layer 15 to cover the slope formed by the back metal layer 16.
In another embodiment of this embodiment, for example, as shown in fig. 10, a step surface is formed on the side of the back metal layer 16 adjacent to the protective material layer 18. The protective material layer 18 may also extend from the edge of the seed metal layer 15 to cover the step surface formed by the back metal layer 16.
Optionally, referring to fig. 11, in the present embodiment, the protective material layer 18 may also extend to cover the back metal layer 16. For example, in the present embodiment, the protective material layer 18 may also cover a part of the surface of the back metal layer 16 away from the seed metal layer 15.
Referring to fig. 12, the present embodiment further provides a method for manufacturing the semiconductor wafer, and the steps of the method are described in detail below.
Step S110, a substrate 11 is provided, where the substrate 11 includes a first side and a second side opposite to the first side.
Alternatively, in the present embodiment, the semiconductor epitaxial layer 112 may be grown on the substrate layer 111 first. For the entire substrate 11, the side of the semiconductor epitaxial layer 112 facing away from the substrate layer 111 is the first side, and the side of the substrate layer 111 facing away from the semiconductor epitaxial layer 112 is the second side.
In step S120, a plurality of sources 12 of the semiconductor chip 10 are formed on the first side of the substrate 11.
Referring to fig. 13, in the present embodiment, the source electrodes 12 of the plurality of semiconductor chips 10 may be formed on the first side of the substrate 11 by photolithography (photolithography), deposition (deposition), etching (etching), and the like. It should be understood that other portions of the semiconductor chip 10 may be further formed based on the first side after the source 12 is formed.
Alternatively, if the substrate 11 is subjected to subsequent photolithography, etching, metallization, and the like, it is easy to be broken, so in this embodiment, after forming each portion of the semiconductor chip 10, the substrate support sheet 200 may be attached to the side of the substrate 11 where the source 12 is formed.
For example, referring to fig. 14, the semiconductor chip 10 may be attached to the base support sheet 200 by using an adhesive 201 (such as optical adhesive, OCA, OCR, Wax, or the like). The base support sheet 200 may be made of sapphire, glass, silicon carbide, silicon wafer, and the like. Thus, the substrate 11 can be prevented from being broken during the process of thinning. It will be appreciated that in other embodiments, the step of attaching the base support sheet 200 may be omitted, provided that it is ensured that the base 11 does not shatter.
In step S130, a plurality of through holes 13 penetrating through the substrate 11 are provided in the substrate 11 at positions corresponding to the sources 12 of the plurality of semiconductor chips 10, respectively.
Optionally, referring to fig. 15, in step 130, a mask layer 210 may be formed on the second side of the substrate 11. The mask layer 210 may be formed by sputtering, plating, deposition, etc. The mask layer 210 may be formed of one or more of nickel, aluminum, silicon dioxide, and silicon nitride.
Then, a photoresist 240 is formed on the mask layer 210, and the photoresist 240 is subjected to photolithography using a photolithography mask to form the patterned protection layer 220. Wherein.
Next, referring to fig. 16, a portion of the mask layer 210 not covered by the protection layer 220 is removed to form a patterned mask layer 230, exposing a portion of the substrate 11.
Finally, referring to fig. 17, the exposed portion of the substrate 11 is etched to form a plurality of through holes 13 penetrating through the substrate 11, and the patterned mask layer 230 is removed. Specifically, the exposed portion of the substrate 11 may be etched by using an Etching apparatus such as RIE (Reactive Ion Etching), ICP (Inductively Coupled Plasma Etching), IBE (Ion Beam Etching), ERC, or the like.
In step S140, a seed metal layer 15 electrically contacting the source electrode 12 through the via hole 13 is formed on the second side surface.
Referring to fig. 18, in the present embodiment, a seed metal layer 15 covering the second side surface of the substrate 11 and extending from the via hole 13 to the source 12 for electrical contact may be formed on the second side surface by sputtering or deposition. The through hole 13 may be filled with the conductive material 14, and then the seed metal layer 15 electrically contacting the conductive material 14 may be formed as shown in fig. 7.
Alternatively, in the present embodiment, the seed metal layer 15 formed in step S140 may include a first metal material layer 151 and a second metal material layer 152.
In step S140, at least two different metal material layers are sequentially formed based on the second side; at least two different metal material layers jointly form the seed metal layer 15, and at least two different metal material layers form an undercut structure on the second side surface; the protective material layer 18 covers at least the edge of the metal material layer farthest from the second side among the metal material layers forming the undercut structure.
Further, a portion of the protection material layer 18 fills the undercut structure and contacts the metal material layer farthest from the second side among the metal material layers forming the undercut structure.
In step S150, the back metal layer 16 covering a part of the seed metal layer 15 is formed based on the seed metal layer 15.
Referring to fig. 19, in the present embodiment, a photoresist 240 may be formed on the seed metal layer 15, and then a back metal layer 16 may be formed. Referring to fig. 20, after the photoresist 240 is removed, a back metal layer 16 covering a portion of the seed metal layer 15 is formed.
In step S160, scribe lanes 20 are formed between the seed metal layers 15 of different semiconductor chips 10.
Referring to fig. 21, in the present embodiment, the seed metal layers 15 of different semiconductor devices may be separated by photolithography to form scribe lines 20.
Step S170, forming a protective material layer 18 at least on the edge of the seed metal layer 15 not covered by the back metal layer 16, and forming the protective material layer 18 to obtain the structure shown in fig. 4, 5, 6, 7, 8, 9, 10, or 11.
In the present embodiment, after the scribe lane 20 is formed, the edges of the seed metal layer 15 located at both sides of the scribe lane 20 are covered with the protective material layer 18, thereby preventing the curling of the seed metal layer 15.
In summary, the present application provides a semiconductor chip, a semiconductor wafer and a method for manufacturing the same, in which a protective material layer is wrapped at an edge of a seed metal layer not covered by a back metal layer, so as to prevent the seed metal layer from curling.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A semiconductor chip, comprising:
a substrate comprising opposing first and second sides;
a source electrode of the semiconductor chip arranged on the first side surface;
the through hole is arranged on the substrate, the arrangement position of the through hole corresponds to the position of the source electrode, and the through hole penetrates from the second side surface to the first side surface;
a seed metal layer formed on the basis of the second side surface and electrically contacted with the source electrode through the through hole;
a back metal layer formed based on the seed metal layer, the back metal layer covering a portion of the seed metal layer;
a protective material layer at least covering the edge of the seed metal layer not covered by the back metal layer;
wherein the seed metal layer comprises at least two different layers of metal material;
the at least two different metal material layers form an undercut structure on the second side surface;
the protective material layer at least covers the edge of the metal material layer which is farthest away from the second side surface in the metal material layer forming the undercut structure.
2. The semiconductor chip of claim 1, wherein the protective material layer covers at least the seed metal layer uncovered by the back side metal layer.
3. The semiconductor chip of claim 1, wherein a portion of the protective material layer fills the undercut structure and contacts a layer of the metal material layer that is farthest from the second side among the metal material layers forming the undercut structure.
4. The semiconductor chip of claim 2, wherein the protective material layer further covers a side surface of the back metal layer, the side surface being a side surface formed between a surface of the back metal layer close to the seed metal layer and a surface far from the seed metal layer.
5. The semiconductor chip of claim 4, wherein the protective material layer further covers a portion of the surface of the back side metal layer away from the seed metal layer.
6. The semiconductor chip of claim 1, wherein the layer of protective material is formed of a highly thermally conductive material.
7. A semiconductor wafer comprising a plurality of semiconductor chips according to any one of claims 1 to 6.
8. The semiconductor wafer of claim 7, wherein seed metal layers of different semiconductor chips are spaced apart from each other by dicing streets.
9. A method of manufacturing a semiconductor wafer, the method comprising:
providing a substrate, wherein the substrate comprises a first side and a second side opposite to the first side;
forming source electrodes of a plurality of semiconductor chips on the first side of the substrate;
manufacturing and forming a plurality of through holes penetrating through the substrate at positions of the substrate corresponding to the source electrodes of the plurality of semiconductor chips respectively;
forming a seed metal layer electrically contacting the source electrode through the via hole based on the second side surface;
forming a back side metal layer covering a portion of the seed metal layer based on the seed metal layer;
etching the seed metal layer to form a scribing channel between two adjacent semiconductor chips;
forming a protective material layer at least on the edge of the seed metal layer uncovered by the back metal layer;
the forming a seed metal layer through the via in electrical contact with the source based on the second side includes:
sequentially forming at least two different metal material layers based on the second side;
wherein the at least two different metal material layers together form the seed metal layer, and the at least two different metal material layers form an undercut structure on the second side; the protective material layer at least covers the edge of the metal material layer which is farthest away from the second side surface in the metal material layer forming the undercut structure.
10. The method of claim 9, further comprising:
forming other portions of the semiconductor chip based on the first side;
and attaching a substrate support sheet to one side of the substrate where the source electrode is manufactured.
11. The method of claim 9, wherein a portion of the protective material layer fills the undercut structure and contacts a layer of the metal material layer that is farthest from the second side among the metal material layers forming the undercut structure.
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| CN103377914A (en) * | 2012-04-18 | 2013-10-30 | 稳懋半导体股份有限公司 | Improved structure of copper metal on back of semiconductor component and processing method thereof |
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| KR100652443B1 (en) * | 2005-11-17 | 2006-12-01 | 삼성전자주식회사 | Redistribution interconnection structure of wafer level package and the method for manufacturing thereof |
| CN107464777A (en) * | 2016-06-02 | 2017-12-12 | 苏州能讯高能半导体有限公司 | Semiconductor crystal wafer and its manufacture method |
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