CN111383705A - Test circuit and test method of memory - Google Patents
Test circuit and test method of memory Download PDFInfo
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- CN111383705A CN111383705A CN201811648942.5A CN201811648942A CN111383705A CN 111383705 A CN111383705 A CN 111383705A CN 201811648942 A CN201811648942 A CN 201811648942A CN 111383705 A CN111383705 A CN 111383705A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Abstract
The application provides a test circuit and a test method of a memory. The memory includes at least one memory cell, the memory cell including a first terminal and a second terminal, the test circuit including: the current applying unit is electrically connected with the first end and the second end at two ends respectively and used for providing constant current for the storage unit; and two ends of the voltage reading unit are respectively and electrically connected with the first end and the second end, and the voltage reading unit is used for reading the voltage of the storage unit under the constant current. The current applying unit of the test circuit provides constant current for the memory unit to enable the memory unit to work under the constant current, and the voltage reading unit reads the voltage of the memory unit under the constant current, so that the resistance of the memory unit can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the memory unit, and other parasitic resistances in series are not included.
Description
Technical Field
The present disclosure relates to the field of memories, and in particular, to a test circuit and a test method for a memory.
Background
In both conventional MRAM arrays and chip-level embedded MRAM arrays, a read voltage is applied between a Source Line (SL) terminal and a Bit Line (BL) terminal to read a current, and a resistance is calculated from the voltage and the current, as shown in fig. 1. The disadvantage of this method is that the BL end and the SL end are actually connected to the copper wire inside the array through the copper wire, and usually reach the MTJ bit 01 after passing through a plurality of MOS transistors 02 in the decoder/MUX addressing circuit, and the sensing circuit is connected in series with a very large parasitic resistance 03, so that the effective magnetic Tunnel Magnetoresistance (TMR) is greatly reduced especially when the line width is smaller and smaller, and the array density is larger and smaller, and the accuracy of the sense amplifier is deteriorated.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a test circuit and a test method for a memory, so as to solve the problem of low detection accuracy of a resistance of a memory cell of the memory in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a test circuit of a memory, the memory including at least one memory cell, the memory cell including a first terminal and a second terminal, the test circuit including: the two ends of the current applying unit are respectively and electrically connected with the first end and the second end, and the current applying unit is used for providing constant current for the memory unit; and two ends of the voltage reading unit are respectively and electrically connected with the first end and the second end, and the voltage reading unit is used for reading the voltage of the storage unit in constant current.
Further, the current applying unit includes a current source, two ends of the current source are electrically connected with the first end and the second end, respectively, the voltage reading unit includes a voltmeter, and two ends of the voltmeter are electrically connected with the first end and the second end, respectively.
Further, the memory includes a plurality of the memory cells distributed in an array, and the current applying unit further includes: a first selector, including two first output terminals and two first input terminals, the two first output terminals being electrically connected to the first terminal and the second terminal of the predetermined memory cell, respectively, and the two first input terminals being electrically connected to two terminals of the current source, respectively; the voltage reading unit further includes: and the second selector comprises two second output ends and two second input ends, the two second input ends are respectively and electrically connected with the first end and the second end of the preset storage unit, and the two second output ends are respectively and electrically connected with two ends of the voltmeter.
Further, each memory cell comprises a driver and a memory resistor electrically connected with the driver, and the second selector comprises a plurality of switches connected in parallel, wherein the switches are connected in series with the drivers in a one-to-one correspondence.
Further, the current applying unit further includes: a first decoder electrically connected to the first selector, the first decoder being configured to generate and transmit a first selection signal to the first selector, the first selection signal being used to select a predetermined memory cell; the test circuit further includes: the second decoder is electrically connected with the memory and used for generating a second selection signal and transmitting the second selection signal to the memory, and the second selection signal is used for controlling a control end of a row where the preset memory cell is located; the voltage reading unit further includes: and a third decoder electrically connected to the second selector, the third decoder being configured to generate a third selection signal and transmit the third selection signal to the second selector, the third selection signal being used to select the predetermined memory cell, and during reading the resistance of the predetermined memory cell, both the first decoder and the third decoder select the predetermined memory cell.
Further, the third decoder includes a read enable terminal, and an input voltage of the enable terminal controls the second selector to be turned on and off.
Further, the driver is an MOS transistor, the MOS transistor includes a source electrode, a gate electrode, and a drain electrode, the memory further includes a plurality of source lines arranged at intervals, a plurality of word lines arranged at intervals, and a plurality of bit lines arranged at intervals, the source lines are electrically connected to the source electrodes in a one-to-one correspondence, the word lines are electrically connected to the gate electrodes of a row of the MOS transistor, the bit lines are electrically connected to the storage resistors in a one-to-one correspondence, any one end of the source lines is the first end, any one end of the bit lines is the second end, and any one end of the word lines is the control end.
Further, the first selector and/or the second selector is a source line/bit line selector for electrically connecting with the source line and the bit line of a predetermined memory cell.
According to another aspect of the present application, there is provided a test method of a memory including at least one memory cell, the test method including: inputting a constant current to a predetermined memory cell; reading a predetermined voltage across the memory cell; calculating a predetermined resistance of the memory cell based on the constant current and the voltage.
Further, the memory includes a plurality of the memory cells distributed in an array, and before a constant current is input to a predetermined memory cell, the test method further includes: selecting a predetermined storage unit; before reading a predetermined voltage across the memory cell, the test method further comprises: and selecting the preset storage unit.
By applying the technical scheme of the application, in the test circuit, the current applying unit provides constant current for the storage unit, so that the storage unit works under the constant current, the voltage reading unit reads the voltage of the storage unit under the constant current, the resistance of the storage unit can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the storage unit, and other parasitic resistances connected in series are not included, so that the test circuit has a relatively accurate detection result on the resistance of the storage unit.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 illustrates a prior art memory cell and corresponding resistance test circuit;
FIG. 2 illustrates a memory cell and corresponding resistance test circuit provided by an embodiment of the present application;
fig. 3 shows a memory cell and a corresponding resistance test circuit provided in another embodiment of the present application.
Wherein the figures include the following reference numerals:
01. an MTJ bit; 02. an MOS tube; 03. a parasitic resistance;
10. a storage unit; 11. a driver; 12. a storage resistor; 13. a word line; 14. a bit line; 15. a source line; 16. a parasitic resistance; 20. a first selector; 30. a second selector; 40. a first decoder; 50. a second decoder; 60. a third decoder; 70. a current source; 80. a voltmeter; 61. and reading the enabling end.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, the detection accuracy of the resistance of the memory cell of the memory in the prior art is not high, and in order to solve the above problems, the present application proposes a test circuit and a test method for the memory.
In an exemplary embodiment of the present application, a test circuit of a memory is provided, the memory including at least one memory cell, the memory cell including a first terminal and a second terminal, wherein the test circuit includes a current applying unit and a voltage reading unit, two terminals of the current applying unit are electrically connected to the first terminal and the second terminal, respectively, and the current applying unit is configured to provide a constant current to the memory cell; the two ends of the voltage reading unit are respectively and electrically connected with the first end and the second end, and the voltage reading unit is used for reading the voltage of the memory unit under the constant current.
In the test circuit, the current applying unit provides a constant current to the memory cell, so that the memory cell operates under the constant current, and the voltage reading unit reads the voltage of the memory cell under the constant current, so that the resistance of the memory cell can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the memory cell, and the resistance does not include other parasitic resistors 16 connected in series, so that the test circuit has a more accurate detection result on the resistance of the memory cell.
In a specific embodiment of the present application, as shown in fig. 2 and 3, the current applying unit includes a current source 70, two ends of the current source 70 are electrically connected to the first terminal and the second terminal, respectively, and the voltage reading unit includes a voltmeter 80, two ends of the voltmeter 80 are electrically connected to the first terminal and the second terminal, respectively. This allows a more accurate test to be achieved in a simpler manner.
The test circuit of the application can test a simple memory which only comprises one memory cell, can test a memory which comprises a plurality of memory cells, and the corresponding memory can be MRAM, RRAM, PCRAM or FeRAM. One skilled in the art can apply the test circuit of the present application to resistance testing of memory cells of various memories.
When the memory includes a plurality of memory cells 10 distributed in an array, as shown in fig. 3, the current applying unit further includes a first selector 20, the first selector 20 includes two first output terminals and two first input terminals, the two first output terminals are electrically connected to the first terminal and the second terminal of a predetermined memory cell 10, respectively, so that the first selector is electrically connected to the predetermined memory cell, which is the memory cell to be tested, when the memory cell to be tested changes, that is, when other memory cells need to be tested, the first selector is electrically connected to the other memory cells to be tested, and the two first input terminals of the first selector are electrically connected to two terminals of the current source 70, respectively; the voltage reading unit further includes a second selector 30, which includes two second output terminals and two second input terminals, the two second input terminals are electrically connected to the first terminal and the second terminal of the predetermined memory cell 10, the two second input terminals are electrically connected to two terminals of the voltmeter 80, and the first selector 20 and the second column selector are electrically connected to the predetermined memory cell 10 during the process of reading the resistance of the predetermined memory cell 10.
It should be noted that, in the detection process, the first selector and the second selector are electrically connected to the same memory cell, so that it is ensured that the current source and the voltmeter are electrically connected to the same memory cell, and thus the same memory cell can be detected.
Note that the constant current applied during reading is small and does not operate the memory cell.
In one specific embodiment of the present invention, as shown in fig. 3, the first selector 20 is a source line/bit line selector for electrically connecting a source line and a bit line of a corresponding memory cell, and the second selector 30 is a source line/bit line selector for electrically connecting a source line 15 and a bit line 14 of a predetermined memory cell.
In another embodiment of the present application, each of the memory cells 10 includes a driver 11 and a storage resistor 12 electrically connected to the driver 11, and the second selector 30 includes a plurality of switches connected in parallel, and the switches are connected in series with the drivers 11 in a one-to-one correspondence. When the switch electrically connected with a certain driver is closed, the corresponding second selector is electrically connected with the memory cell corresponding to the driver, so that the voltage across the corresponding memory cell can be read.
It should be noted that the driver can be any driver available in the prior art, such as a transistor, a diode, etc., and those skilled in the art can select a suitable driver according to the actual situation. The storage resistance may be any available storage resistance in the prior art, such as MTJ, etc. The switch may be any switch available in the prior art, such as a transistor, a diode, etc., and those skilled in the art can select a suitable switch to be electrically connected to the corresponding driver according to actual situations.
In order to more conveniently and efficiently select a memory cell for testing, in an embodiment of the present application, the current applying unit further includes a first decoder 40, the test circuit further includes a second decoder 50, and the voltage reading unit further includes a third decoder 60.
A first decoder 40 electrically connected to the first selector 20, the first decoder 40 generating a first selection signal for selecting a predetermined memory cell 10 and transmitting the first selection signal to the first selector 20; a second decoder 50 electrically connected to the memory, wherein the second decoder 50 is configured to generate a second selection signal and transmit the second selection signal to the memory, and the second selection signal is used to control a control end of a predetermined row of the memory cells 10 so as to control the transistors of the corresponding memory cells to be turned on; a third decoder 60 is electrically connected to the second selector 30, the third decoder 60 is configured to generate a third selection signal for selecting a predetermined memory cell 10 and transmit the third selection signal to the second selector 30, during reading of the resistance of the predetermined memory cell 10, the first decoder 40 and the third decoder 60 each select the predetermined memory cell 10, the second decoder selects a row in which the predetermined memory cell 10 is located, so that the three decoders function together to place the predetermined memory cell in an operating state, and the first decoder and the third decoder have the same address during the reading operation.
In order to control the state of the second selector more conveniently, in an embodiment of the present application, the third decoder 60 includes a read enable terminal 61, and an input voltage of the read enable terminal 61 controls the second selector 30 to be turned on or off. In the writing operation process, the read enable end is low voltage, the second decoder is closed, all the switches are disconnected, and the second selector is closed. In the reading operation process, the reading enable end is high voltage, the second decoder is opened, all the switches are closed, and the second selector is opened.
In a specific embodiment of the present application, as shown in fig. 3, the driver 11 is a MOS transistor including a source, a gate, and a drain, the memory further includes a plurality of source lines 15 arranged at intervals, a plurality of word lines 13 arranged at intervals, and a plurality of bit lines 14 arranged at intervals, the source lines 15 are electrically connected to the sources in a one-to-one correspondence, the word lines 13 are electrically connected to the gates of a row of the MOS transistors, the bit lines 14 are electrically connected to the memory resistors 12 in a one-to-one correspondence, any one end of the source lines 15 is the first end, any one end of the bit lines 14 is the second end, and any one end of the word lines 13 is the control end. That is, the two first output terminals of the first selector are electrically connected to the source line and the bit line of the predetermined memory cell 10, respectively, and the two second input terminals of the second selector are electrically connected to the source line and the bit line of the predetermined memory cell 10, respectively. The second decoder is electrically connected to the word line.
In another exemplary embodiment of the present application, a method for testing a memory is provided, and the method is implemented by using the test circuit.
In another exemplary embodiment of the present application, a method for testing a memory, the memory including at least one memory cell 10, is provided, the method including: inputting a constant current to a predetermined memory cell 10; reading a predetermined voltage across the memory cell 10; the predetermined resistance of the memory cell 10 is calculated from the constant current and the voltage.
In the test method, the resistance of the memory cell can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the memory cell, and other parasitic resistances connected in series are not included, so that the test circuit has a more accurate detection result on the resistance of the memory cell.
In another embodiment of the present application, the memory includes a plurality of memory cells 10 distributed in an array, and before a constant current is input to a predetermined memory cell 10, the test method further includes: selecting a predetermined storage unit 10; before reading a predetermined voltage across the memory cell 10, the test method further includes: a predetermined memory cell 10 is selected. In this way, a memory cell with a measurement, that is, a predetermined memory cell, can be selected from the plurality of memory cells and then tested.
In order to make the technical solutions and technical effects of the present application more clearly understood by those skilled in the art, the following description will be given with reference to specific embodiments.
Examples
As shown in fig. 3, the test circuit of the memory includes a current applying unit, a voltage reading unit, and a second decoder.
The current applying unit includes a current source 70, a first selector 20, and a first decoder 40; the voltage reading unit includes a voltmeter 80, a second selector 30, and a third decoder 60. The connection relationship of the respective devices is shown in fig. 3 and described above.
The memory comprises a plurality of memory units which are arranged in an array, the memory capacity is 128k, the row address is 10 bits, and the column address is 7 bits. Each of the memory cells 10 includes a driver 11 and a storage resistor 12 electrically connected to the driver 11, the driver 11 is a MOS transistor including a source, a gate and a drain, the storage resistor is an MTJ bit, the memory further includes a plurality of source lines 15 arranged at intervals, a plurality of word lines 13 arranged at intervals, and a plurality of bit lines 14 arranged at intervals, the source lines 15 are electrically connected to the sources in a one-to-one correspondence, the word lines 13 are electrically connected to the gates of a row of the MOS transistors, and the bit lines 14 are electrically connected to the storage resistors 12 in a one-to-one correspondence.
The second selector comprises a plurality of MOS tubes connected in parallel, the drain electrodes of the MOS tubes are electrically connected with the bit lines of the MOS tubes in the storage unit in a one-to-one corresponding mode, the grid electrodes of the MOS tubes are electrically connected with the source lines of the MOS tubes in the storage unit in a one-to-one corresponding mode, and the source electrodes of all the MOS tubes are connected together in parallel and electrically connected with the third decoder.
The testing process of the memory cell comprises the following steps:
and (3) writing: the first decoder sends out a first selection signal and transmits the first selection signal to the first selector, the first selector electrically connects the two first output terminals to the bit line and the source line of the predetermined memory cell 10, respectively, and the second decoder electrically connects the word line of the column in which the predetermined memory cell is located, according to the first selection signal, and the predetermined memory cell operates at a constant current. The read enable terminal of the third decoder is at a low potential.
And (3) reading: the read enable terminal of the third decoder is at a high potential, the second decoder sends out a second selection signal and transmits the second selection signal to the preset memory cell, the second decoder is electrically connected with the word line of the row where the preset memory cell is located, the second selector electrically connects the two second input terminals with the bit line and the source line of the preset memory cell 10 respectively according to the third selection signal, the voltmeter reads out the voltage of the preset memory cell, and the resistance of the preset memory cell is calculated according to the read voltage and the constant current provided by the current source.
In the figure, "VCSL" indicates the power supply voltages of the first decoder and the third decoder, "WLDRV" indicates the word line driving voltage of the third decoder, and "VSUB" indicates the substrate voltage of the MOS transistor.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the test circuit, the current applying unit provides constant current for the storage unit, so that the storage unit works under the constant current, the voltage reading unit reads the voltage of the storage unit under the constant current, the resistance of the storage unit can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the storage unit, and other parasitic resistances connected in series are not included, so that the test circuit has a more accurate detection result on the resistance of the storage unit.
2) In the test method, the resistance of the memory cell can be calculated by using the constant current and the read voltage, the resistance is only the resistance of the memory cell, and other parasitic resistances connected in series are not included, so that the test circuit has a more accurate detection result on the resistance of the memory cell.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A test circuit for a memory, said memory comprising at least one memory cell (10), said memory cell (10) comprising a first terminal and a second terminal, characterized in that said test circuit comprises:
a current applying unit, two ends of which are respectively and electrically connected with the first end and the second end, wherein the current applying unit is used for providing constant current to the memory unit (10);
and two ends of the voltage reading unit are respectively and electrically connected with the first end and the second end, and the voltage reading unit is used for reading the voltage of the storage unit (10) at constant current.
2. The test circuit according to claim 1, wherein the current applying unit comprises a current source (70), both ends of the current source (70) are electrically connected with the first terminal and the second terminal, respectively, and the voltage reading unit comprises a voltmeter (80), both ends of the voltmeter (80) are electrically connected with the first terminal and the second terminal, respectively.
3. Test circuit according to claim 2, characterized in that the memory comprises a plurality of the memory cells (10) distributed in an array,
the current applying unit further includes:
a first selector (20) including two first output terminals electrically connected to the first terminal and the second terminal of the predetermined memory cell (10), respectively, and two first input terminals electrically connected to both terminals of the current source (70), respectively;
the voltage reading unit further includes:
and the second selector (30) comprises two second output ends and two second input ends, the two second input ends are respectively and electrically connected with the first end and the second end of the preset storage unit (10), and the two second output ends are respectively and electrically connected with two ends of the voltmeter (80).
4. The test circuit according to claim 3, wherein each of the memory cells (10) comprises a driver (11) and a storage resistor (12) electrically connected to the driver (11), and wherein the second selector (30) comprises a plurality of switches connected in parallel, the switches being connected in series with the drivers (11) in a one-to-one correspondence.
5. The test circuit of claim 4,
the current applying unit further includes: a first decoder (40) electrically connected to the first selector (20), the first decoder (40) being configured to generate and transmit a first selection signal to the first selector (20), the first selection signal being configured to select a predetermined memory cell (10);
the test circuit further includes: a second decoder (50) electrically connected to the memory, the second decoder (50) being configured to generate and transmit a second selection signal to the memory, the second selection signal being configured to control a control terminal of a row in which a predetermined memory cell (10) is located; the voltage reading unit further includes: a third decoder (60) electrically connected to the second selector (30), wherein the third decoder (60) is configured to generate a third selection signal for selecting a predetermined memory cell (10) and transmit the third selection signal to the second selector (30), and during reading of the resistance of the predetermined memory cell (10), the first decoder (40) and the third decoder (60) both select the predetermined memory cell (10).
6. The test circuit according to claim 5, wherein the third decoder (60) comprises a read enable (61), an input voltage of the read enable (61) controlling the second selector (30) to be turned on and off.
7. The test circuit according to claim 5, wherein the driver (11) is a MOS transistor, the MOS transistor comprises a source, a gate and a drain, the memory further comprises a plurality of spaced apart source lines (15), a plurality of spaced apart word lines (13) and a plurality of spaced apart bit lines (14), the source lines (15) are electrically connected to the source in a one-to-one correspondence, the word lines (13) are electrically connected to the gates of a row of the MOS transistors, the bit lines (14) are electrically connected to the memory resistors (12) in a one-to-one correspondence, any one end of the source lines (15) is the first end, any one end of the bit lines (14) is the second end, and any one end of the word lines (13) is the control end.
8. The test circuit according to claim 7, wherein the first selector (20) and/or the second selector (30) is a source line/bit line selector for electrical connection with the source line (15) and the bit line (14) of a predetermined memory cell.
9. A method for testing a memory, characterized in that the memory comprises at least one memory cell (10), the method comprising:
inputting a constant current to a predetermined memory cell (10);
reading a voltage across a predetermined said memory cell (10);
calculating a predetermined resistance of the memory cell (10) from the constant current and the voltage.
10. The test method according to claim 9, characterized in that the memory comprises a plurality of said memory cells (10) distributed in an array,
before inputting a constant current to a predetermined memory cell (10), the test method further includes: selecting a predetermined storage unit (10);
before reading a predetermined voltage across the memory cell (10), the test method further comprises: selecting a predetermined memory cell (10).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811648942.5A CN111383705A (en) | 2018-12-30 | 2018-12-30 | Test circuit and test method of memory |
| PCT/CN2019/126747 WO2020140765A1 (en) | 2018-12-30 | 2019-12-19 | Testing circuit and testing method for memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811648942.5A CN111383705A (en) | 2018-12-30 | 2018-12-30 | Test circuit and test method of memory |
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| EP0500461A1 (en) * | 1991-02-21 | 1992-08-26 | STMicroelectronics S.A. | Device for the detection of the logical state of a component, whose impedance varies according to it's state |
| CN101562050A (en) * | 2008-01-07 | 2009-10-21 | 旺宏电子股份有限公司 | Phase change memory dynamic resistance test and manufacturing methods |
| CN101872643A (en) * | 2009-04-22 | 2010-10-27 | 索尼公司 | Variable-resistance memory device and method of operating thereof |
| US20100328995A1 (en) * | 2009-06-25 | 2010-12-30 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
| CN104718577A (en) * | 2012-10-15 | 2015-06-17 | 马维尔国际贸易有限公司 | Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers |
| US20140347919A1 (en) * | 2013-05-21 | 2014-11-27 | Fujitsu Limited | Semiconductor storage device |
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