WO2020140765A1

WO2020140765A1 - Testing circuit and testing method for memory

Info

Publication number: WO2020140765A1
Application number: PCT/CN2019/126747
Authority: WO
Inventors: 刘少鹏; 熊宝玉
Original assignee: 浙江驰拓科技有限公司
Priority date: 2018-12-30
Filing date: 2019-12-19
Publication date: 2020-07-09
Also published as: CN111383705A

Abstract

The present disclosure provides a testing circuit and a testing method for a memory. The memory comprises at least one storage unit comprising a first end and a second end. The testing circuit comprises: a current application unit for providing a constant current to the storage unit, two ends of the current application unit being electrically connected to the first end and the second end respectively; and a voltage reading unit for reading a voltage of the storage unit at the constant current, two ends of the voltage reading unit being electrically connected to the first end and the second end respectively. The current application unit of the testing circuit provides a constant current to the storage unit, such that the storage unit operates at the constant current. The voltage reading unit then reads a voltage of the storage unit at the constant current. In this way, the resistance of the storage unit can be calculated simply by means of the constant current and the read voltage, and said resistance is generated by the storage unit alone, excluding other parasitic resistance in a series connection.

Description

Test circuit and test method of memory

This disclosure is based on the patent document filed on December 30, 2018 with the application number 201811648942.5 and titled "Test Circuits and Test Methods for Memory" as the priority document, the entire contents of which are incorporated by reference in this disclosure.

Technical field

The present disclosure relates to the field of memory, and in particular, to a test circuit and test method of a memory.

Background technique

The test circuits of traditional MRAM arrays and chip-level embedded MRAM arrays both apply a reading voltage between the source line (SL) terminal and the bit line (BL) terminal for current reading , And calculate resistance based on voltage and current, see Figure 1 for details. The disadvantage of this method is that the BL and SL terminals are actually connected to the copper wires inside the array through copper wires, and generally reach the MTJ bit 01 after several MOS tubes 02 in the decoder/MUX addressing circuit, and the detection circuit A large parasitic resistance 03 is connected in series, especially when the line width is getting smaller and smaller and the array density is getting larger and larger, the effective magnetic tunnel magnetoresistance (TMR) is greatly reduced, and the accuracy of the sense amplifier is deteriorated.

The above information disclosed in the background section is only used to enhance the understanding of the background technology of the technology described herein. Therefore, the background technology may contain certain information, which is not formed in the country for those skilled in the art. Known prior art.

Summary of the invention

The main purpose of the present disclosure is to provide a test circuit and a test method of a memory to solve the problem of low detection accuracy of the resistance of the memory cell of the memory in the prior art.

In order to achieve the above object, according to an aspect of the present disclosure, a test circuit for a memory is provided, the memory includes at least one storage unit, the storage unit includes a first end and a second end, the test circuit includes: current application Unit, both ends of the current applying unit are electrically connected to the first end and the second end respectively, the current applying unit is used to provide a constant current to the storage unit; a voltage reading unit, the voltage Both ends of the reading unit are electrically connected to the first end and the second end, respectively, and the voltage reading unit is used to read the voltage of the storage unit at the constant current.

Further, the current applying unit includes a current source, and both ends of the current source are electrically connected to the first end and the second end, respectively, and the voltage reading unit includes a voltmeter, and Both ends are electrically connected to the first end and the second end, respectively.

Further, the memory includes a plurality of the storage units distributed in an array, and the current applying unit further includes: a first selector including two first output terminals and two first input terminals, and two The first output terminal is respectively electrically connected to the first terminal and the second terminal of the predetermined storage unit, and the two first input terminals are respectively electrically connected to both ends of the current source; voltage reading The fetching unit further includes: a second selector including two second output terminals and two second input terminals, and the two second input terminals are respectively connected to the predetermined first end and the first end of the storage unit The second terminal is electrically connected, and the two second output terminals are respectively electrically connected to both ends of the voltmeter.

Further, each of the storage units includes a driver and a storage resistor electrically connected to the driver, the second selector includes a plurality of switches connected in parallel, and the switches and the drivers are connected in series in one-to-one correspondence.

Further, the current applying unit further includes: a first decoder electrically connected to the first selector, and the first decoder is used to generate a first selection signal and transmit it to the first selector, The first selection signal is used to select the predetermined storage unit; the test circuit further includes: a second decoder electrically connected to the memory, and the second decoder is used to generate a second selection signal and Transmitted to the memory, the second selection signal is used to control a predetermined control terminal of the row where the storage unit is located; the voltage reading unit further includes: a third decoder, which is electrically connected to the second selector Connected, the third decoder is used to generate a third selection signal and transmitted to the second selector, the third selection signal is used to select the predetermined storage unit, and read the predetermined storage During the resistance of the cell, both the first decoder and the third decoder select the predetermined memory cell.

Further, the third decoder includes a read enable terminal, and the input voltage of the enable terminal controls the opening and closing of the second selector.

Further, the driver is a MOS tube, and the MOS tube includes a source, a gate, and a drain, and the memory further includes a plurality of spaced source lines, a plurality of spaced word lines, and a plurality of spaced settings Bit line, the source line and the source electrode are electrically connected in a one-to-one correspondence, the word line is electrically connected to the gate of a row of the MOS transistors, the bit line and the storage resistor are Electrically connected in a corresponding manner, any end of the source line is the first end, any end of the bit line is the second end, and any end of the word line is the control end.

Further, the first selector is a source line/bit line selector, and the source line/bit line selector is used to electrically connect the source line and the bit line of the predetermined memory cell .

Further, the second selector is a source line/bit line selector, and the source line/bit line selector is used to electrically connect the source line and the bit line of the predetermined memory cell .

Further, both the first selector and the second selector are source line/bit line selectors, and the source line/bit line selector is used to communicate with a predetermined source of the memory cell The line is electrically connected to the bit line.

According to another aspect of the present disclosure, a test method for a memory is provided, the memory includes at least one storage unit, the test method includes: inputting a constant current to a predetermined storage unit; reading two of the predetermined storage unit The voltage of the terminal; calculating a predetermined resistance of the memory cell based on the constant current and the voltage.

Further, the memory includes a plurality of the storage units distributed in an array, and before inputting a constant current to the predetermined storage unit, the test method further includes: selecting the predetermined storage unit; Before taking a predetermined voltage across the storage unit, the test method further includes: selecting the predetermined storage unit.

Applying the technical solution of the present disclosure, in the above test circuit, the current applying unit provides a constant current to the storage unit, so that the storage unit operates at a constant current, and the voltage reading unit reads the voltage of the storage unit at a constant current, so The resistance of the memory cell can be calculated by using the constant current and the voltage obtained by reading. The resistance is only the resistance of the memory cell, excluding other parasitic resistances connected in series, so the test circuit detects the resistance of the memory cell more accurately.

BRIEF DESCRIPTION

The accompanying drawings forming part of the present disclosure are used to provide a further understanding of the present disclosure. The exemplary embodiments and descriptions of the present disclosure are used to explain the present disclosure, and do not constitute an undue limitation on the present disclosure. In the drawings:

FIG. 1 shows a memory cell and a corresponding resistance test circuit in the prior art;

2 shows a memory cell and a corresponding resistance test circuit provided by an embodiment of the present disclosure;

FIG. 3 shows a memory cell and a corresponding resistance test circuit provided by another embodiment of the present disclosure.

Among them, the above drawings include the following reference signs:

01, MTJ bit; 02, MOS tube; 03, parasitic resistance;

10. Memory cell; 11, driver; 12, storage resistance; 13, word line; 14, bit line; 15, source line; 16, parasitic resistance; 20, first selector; 30, second selector; 40 1. The first decoder; 50. The second decoder; 60. The third decoder; 70. The current source; 80. The voltmeter; 61. The read enable terminal.

detailed description

It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanations of the present disclosure. Unless otherwise indicated, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs.

It should be noted that the terminology used herein is for describing specific embodiments only, and is not intended to limit exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and/or "including" are used in this specification, it indicates There are features, steps, operations, devices, components, and/or combinations thereof.

It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element, or intervening elements may also be present. Moreover, in the specification and claims, when an element is described as "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

As introduced in the background art, the detection accuracy of the resistance of the memory cell of the memory in the prior art is not high. In order to solve the above problem, the present disclosure proposes a memory test circuit and method.

In a typical embodiment of the present disclosure, a test circuit for a memory is provided. The memory includes at least one storage unit, and the storage unit includes a first end and a second end, wherein the test circuit includes a current applying unit and A voltage reading unit, both ends of the current applying unit are electrically connected to the first end and the second end respectively; the current applying unit is used to provide a constant current to the storage unit; the two ends of the voltage reading unit are respectively connected to the above The first end is electrically connected to the second end, and the voltage reading unit is used to read the voltage of the storage unit when the constant current is supplied.

In the above test circuit, the current applying unit provides a constant current to the storage unit, so that the storage unit operates at a constant current, and the voltage reading unit reads the voltage of the storage unit at a constant current, which is obtained by using the constant current and reading The resistance of the memory cell can be calculated by the voltage of, the resistance is only the resistance of the memory cell, and does not include other parasitic resistances 16 connected in series, so the test circuit detects the resistance of the memory cell more accurately.

In a specific embodiment of the present disclosure, as shown in FIGS. 2 and 3, the current applying unit includes a current source 70, and both ends of the current source 70 are electrically connected to the first end and the second end, respectively. The voltage reading unit includes a voltmeter 80, and both ends of the voltmeter 80 are electrically connected to the first end and the second end, respectively. In this way, more accurate tests can be achieved in a simpler way.

The test circuit of the present disclosure can test a simple memory including only one memory cell, can test a memory including multiple memory cells, and the corresponding memory can be MRAM, RRAM, PCRAM, or FeRAM. Those skilled in the art can apply the test circuit of the present disclosure to the resistance testing process of the memory cells of various memories.

When the memory includes a plurality of the memory cells 10 distributed in an array, as shown in FIG. 3, the current applying unit further includes a first selector 20. The first selector 20 includes two first output terminals and two An input terminal, the two first output terminals are electrically connected to the first terminal and the second terminal of the predetermined storage unit 10 respectively, so that the first selector is electrically connected to the predetermined storage unit, the predetermined storage unit is to be For the storage unit under test, when the storage unit under test changes, that is, when another storage unit needs to be detected, the first selector is electrically connected to the other storage unit under test, and the two first inputs of the first selector Terminals are electrically connected to the two ends of the current source 70; the voltage reading unit further includes a second selector 30, the second selector includes two second output terminals and two second input terminals, two second input terminals Are electrically connected to the first end and the second end of the predetermined memory cell 10 respectively, the two second input terminals are electrically connected to both ends of the voltmeter 80 respectively, and During the resistance process, both the first selector 20 and the second column selector are electrically connected to the predetermined memory cell 10.

It should be noted that in the detection process, the first selector and the second selector are electrically connected to the same storage unit, which ensures that the current source and the voltmeter are electrically connected to the same storage unit, so that the same One storage unit is tested.

It should be noted that the constant current applied during the reading process is small, and the memory cell will not be operated.

In a specific embodiment of the present disclosure, as shown in FIG. 3, the first selector 20 is a source line/bit line selector for electrically connecting the source line and the bit line of the corresponding memory cell. The second selector 30 is a source line/bit line selector for electrically connecting the source line 15 and the bit line 14 of a predetermined memory cell.

In another embodiment of the present disclosure, each of the storage units 10 includes a driver 11 and a storage resistor 12 electrically connected to the driver 11, the second selector 30 includes a plurality of switches in parallel, and the switch and the driver 11 One corresponds to the series. When the switch electrically connected to a certain drive is closed, the corresponding second selector is electrically connected to the storage unit corresponding to the drive, so that the voltage across the corresponding storage unit can be read.

It should be noted that the above-mentioned driver may be any driver available in the prior art, such as a triode, a diode, etc., and those skilled in the art may select a suitable driver according to actual conditions. The above storage resistor may also be any available storage resistor in the prior art, such as MTJ. The above-mentioned switch can also be any switch available in the prior art, such as a triode, a diode, etc., and a person skilled in the art can select an appropriate switch to be electrically connected to the corresponding driver according to the actual situation.

In order to more conveniently and efficiently select a memory cell for detection, in an embodiment of the present disclosure, the current applying unit further includes a first decoder 40, the test circuit further includes a second decoder 50, and the voltage reading The fetch unit also includes a third decoder 60.

The first decoder 40 is electrically connected to the first selector 20, the first decoder 40 is used to generate a first selection signal and transmitted to the first selector 20, the first selection signal is used to select a predetermined The storage unit 10; the second decoder 50 is electrically connected to the memory, the second decoder 50 is used to generate a second selection signal and transmitted to the memory, the second selection signal is used to control the predetermined storage unit 10 is the control terminal of the row to control the opening of the transistor of the corresponding memory cell; the third decoder 60 is electrically connected to the second selector 30, and the third decoder 60 is used to generate a third selection signal and transmit To the second selector 30, the third selection signal is used to select the predetermined memory cell 10. During the reading of the resistance of the predetermined memory cell 10, the first decoder 40 and the third translator The encoder 60 selects the predetermined storage unit 10 above, and the second decoder selects the predetermined row of the storage unit 10, so that the three decoders work together to make the predetermined storage unit in working state, the first decoding The decoder and the third decoder have the same address during the read operation.

In order to more conveniently control the state of the second selector, in an embodiment of the present disclosure, the third decoder 60 includes a read enable terminal 61, and the input voltage of the read enable terminal 61 controls the second selector 30 on and off. During the write operation, the read enable terminal is at a low voltage, the second decoder is turned off, all switches are turned off, and the second selector is turned off. During the read operation, the read enable terminal is at a high voltage, the second decoder is opened, all switches are closed, and the second selector is opened.

In a specific embodiment of the present disclosure, as shown in FIG. 3, the driver 11 is a MOS tube, the MOS tube includes a source, a gate, and a drain, and the memory further includes a plurality of source lines 15 arranged at intervals A plurality of word lines 13 and a bit line 14 arranged at intervals, the source line 15 is electrically connected to the source in a one-to-one correspondence, and the word line 13 is electrically connected to the gate of a row of the MOS transistors Connected, the bit line 14 is electrically connected to the storage resistor 12 in one-to-one correspondence, any end of the source line 15 is the first end, any end of the bit line 14 is the second end, and the word line 13 Either end is the above control end. That is, the two first output terminals of the first selector are electrically connected to the source line and the bit line of the predetermined memory cell 10 respectively, and the two second input terminals of the second selector are respectively connected to the predetermined memory cell The source line of 10 and the bit line are electrically connected. The second decoder is electrically connected to the word line.

In another embodiment of the present disclosure, the first selector 20 is a source line/bit line selector, and the source line/bit line selector is used to communicate with a predetermined source of the memory cell The line 15 and the bit line 14 are electrically connected.

In still another embodiment of the present disclosure, the second selector 30 is a source line/bit line selector, and the source line/bit line selector is used to communicate with a predetermined source of the memory cell The line 15 and the bit line 14 are electrically connected.

In yet another embodiment of the present disclosure, the first selector 20 and the second selector 30 are both source line/bit line selectors, and the source line/bit line selectors are used to The source line 15 and the bit line 14 of the memory cell are electrically connected.

In another exemplary embodiment of the present disclosure, a test method for a memory is provided, and the test method is implemented using the above test circuit.

In yet another exemplary embodiment of the present disclosure, a test method for a memory is provided. The above-mentioned memory includes at least one storage unit 10. The test method includes: inputting a constant current to a predetermined storage unit 10; reading a predetermined The voltage across the memory cell 10; the predetermined resistance of the memory cell 10 is calculated based on the constant current and the voltage.

In the above test method, the resistance of the memory cell can be calculated by using the constant current and the read voltage. The resistance is only the resistance of the memory cell, excluding other parasitic resistances connected in series, so the resistance of the test circuit to the memory cell Test results are more accurate.

In another embodiment of the present disclosure, the memory includes a plurality of the memory cells 10 distributed in an array. Before inputting a constant current to the predetermined memory cell 10, the test method further includes: selecting a predetermined memory cell Unit 10; before reading the voltage across the predetermined storage unit 10, the test method further includes: selecting the predetermined storage unit 10. In this way, a storage unit with a measurement, that is, a predetermined storage unit, can be selected from a plurality of storage units, and then tested.

In order to enable those skilled in the art to more clearly understand the technical solutions and technical effects of the present disclosure, the following will be described in conjunction with specific embodiments.

Examples

As shown in FIG. 3, the test circuit of the memory includes a current applying unit, a voltage reading unit, and a second decoder.

The current applying unit includes a current source 70, a first selector 20, and a first decoder 40; the voltage reading unit includes a voltmeter 80, a second selector 30, and a third decoder 60. The connection relationship of each device is shown in Figure 3 and the above description.

The memory includes a plurality of storage cells arranged in an array, the storage capacity of the memory is 128k, the row address is 10 bits, and the column address is 7 bits. Each of the memory cells 10 includes a driver 11 and a storage resistor 12 electrically connected to the driver 11, the driver 11 is a MOS tube, the MOS tube includes a source, a gate, and a drain, the storage resistance is an MTJ bit, and the memory Also includes a plurality of spaced source lines 15, a plurality of spaced word lines 13 and a plurality of spaced bit lines 14, the source lines 15 are electrically connected to the sources in one-to-one correspondence, the word lines 13 The gates of the MOS transistors in a row are electrically connected, and the bit lines 14 and the storage resistors 12 are electrically connected in a one-to-one correspondence.

The second selector includes a plurality of MOS tubes connected in parallel, the drain of the MOS tube and the bit line of the MOS tube in the memory cell correspond to each other in electrical connection, the gate of the MOS tube and the source line of the MOS tube in the memory cell One corresponds to the electrical connection. The sources of all MOS tubes are connected in parallel and electrically connected to the third decoder.

The testing process of the storage unit includes:

Writing process: the first decoder sends a first selection signal and transmits it to the first selector, the first selector according to the first selection signal, the two of the first output terminal and the predetermined bit of the storage unit 10 The line and the source line are electrically connected to electrically connect the second decoder to the word line of the column where the predetermined memory cell is located, and the predetermined memory cell operates at a constant current. The read enable terminal of the third decoder is at a low potential.

Reading process: the read enable terminal of the third decoder is at a high potential, the second decoder sends out the second selection signal and transmits it to the predetermined storage unit, the row where the second decoder and the predetermined storage unit are located The word line is electrically connected, and the second selector electrically connects the two second input terminals to the predetermined bit line and source line of the memory cell 10 according to the third selection signal, and the voltmeter reads out the The voltage is calculated based on the read voltage and the constant current provided by the current source to obtain the resistance of the predetermined memory cell.

It should be noted that "VCSL" in the figure represents the power supply voltage of the first decoder and the third decoder, "WLDRV" represents the word line driving voltage of the third decoder, and "VSUB" represents the liner of the MOS tube. Bottom voltage.

From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

1) In the test circuit of the present disclosure, the current applying unit provides a constant current to the storage unit, so that the storage unit operates at a constant current, and the voltage reading unit reads the voltage of the storage unit at a constant current, thus using a constant current The resistance of the memory cell can be calculated based on the read voltage and the resistance is only the resistance of the memory cell, excluding other parasitic resistances connected in series, so the test circuit has a more accurate detection result for the resistance of the memory cell.

2) In the test method of the present disclosure, the resistance of the memory cell can be calculated by using a constant current and the voltage obtained by reading, the resistance is only the resistance of the memory cell, and does not include other parasitic resistances connected in series, so the test circuit is The detection result of the resistance of the memory cell is more accurate.

The above are only preferred embodiments of the present disclosure, and are not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of this disclosure shall be included in the protection scope of this disclosure.

Claims

A test circuit of a memory, the memory includes at least one storage unit (10), the storage unit (10) includes a first end and a second end, characterized in that the test circuit includes:

A current applying unit, both ends of the current applying unit are electrically connected to the first end and the second end respectively, and the current applying unit is used to provide a constant current to the storage unit (10);

A voltage reading unit, two ends of the voltage reading unit are electrically connected to the first end and the second end respectively, and the voltage reading unit is used to read the storage unit (10) in the Voltage at constant current.
The test circuit according to claim 1, wherein the current applying unit includes a current source (70), and both ends of the current source (70) are electrically connected to the first end and the second end, respectively For connection, the voltage reading unit includes a voltmeter (80), and both ends of the voltmeter (80) are electrically connected to the first end and the second end, respectively.
The test circuit according to claim 2, characterized in that the memory includes a plurality of the memory cells (10) distributed in an array,

The current applying unit further includes:

The first selector (20) includes two first output terminals and two first input terminals, and the two first output terminals are respectively connected to the first terminal and all of the predetermined storage unit (10) The second terminal is electrically connected, and the two first input terminals are respectively electrically connected to both ends of the current source (70);

The voltage reading unit further includes:

The second selector (30) includes two second output terminals and two second input terminals, and the two second input terminals are respectively connected to the first terminal and the second terminal of the predetermined storage unit (10) The second terminal is electrically connected, and the two second output terminals are respectively electrically connected to both ends of the voltmeter (80).
The test circuit according to claim 3, wherein each of the memory cells (10) includes a driver (11) and a storage resistor (12) electrically connected to the driver (11), and the second selector (30) includes a plurality of switches connected in parallel, and the switches are connected in series with the driver (11) in a one-to-one correspondence.
The test circuit according to claim 4, wherein:

The current applying unit further includes a first decoder (40) electrically connected to the first selector (20), the first decoder (40) is used to generate a first selection signal and transmit to The first selector (20), the first selection signal is used to select the predetermined storage unit (10);

The test circuit further includes: a second decoder (50) electrically connected to the memory, the second decoder (50) is used to generate a second selection signal and transmit it to the memory, the first Two selection signals are used to control the control terminal of the row where the predetermined storage unit (10) is located;

The voltage reading unit further includes: a third decoder (60) electrically connected to the second selector (30), the third decoder (60) is used to generate and transmit a third selection signal To the second selector (30), the third selection signal is used to select the predetermined storage unit (10), and during the reading of the resistance of the predetermined storage unit (10), all Both the first decoder (40) and the third decoder (60) select the predetermined storage unit (10).
The test circuit according to claim 5, wherein the third decoder (60) includes a read enable terminal (61), and an input voltage of the read enable terminal (61) controls the second The selector (30) turns on and off.
The test circuit according to claim 5, characterized in that the driver (11) is a MOS tube, the MOS tube includes a source, a gate and a drain, and the memory further includes a plurality of spaced sources A line (15), a plurality of spaced word lines (13) and a plurality of spaced bit lines (14), the source line (15) and the source are electrically connected in one-to-one correspondence, the word The line (13) is electrically connected to the gates of a row of the MOS transistors, the bit line (14) and the storage resistor (12) are electrically connected in one-to-one correspondence, and the source line (15) Either end is the first end, any end of the bit line (14) is the second end, and any end of the word line (13) is the control end.
The test circuit according to claim 7, characterized in that the first selector (20) is a source line/bit line selector, and the source line/bit line selector is used for The source line (15) and the bit line (14) of the cell are electrically connected.
The test circuit according to claim 7, characterized in that the second selector (30) is a source line/bit line selector, and the source line/bit line selector is used for The source line (15) and the bit line (14) of the cell are electrically connected.
The test circuit according to claim 7, wherein the first selector (20) and the second selector (30) are both source line/bit line selectors, and the source line/ A bit line selector is used to electrically connect the source line (15) and the bit line (14) of the predetermined memory cell.
A memory testing method, characterized in that the memory includes at least one storage unit (10), and the testing method includes:

Input a constant current into a predetermined storage unit (10);

Reading a predetermined voltage across the storage unit (10);

The predetermined resistance of the memory cell (10) is calculated based on the constant current and the voltage.
The test method according to claim 11, wherein the memory includes a plurality of the storage units (10) distributed in an array,

Before inputting a constant current to the predetermined storage unit (10), the test method further includes: selecting the predetermined storage unit (10);

Before reading the voltage across the predetermined storage unit (10), the test method further includes: selecting the predetermined storage unit (10).