CN111382822B

CN111382822B - Chip

Info

Publication number: CN111382822B
Application number: CN202010332295.8A
Authority: CN
Inventors: 樊再利; 王景山; 杨晓峰
Original assignee: Beijing Huahailong Technology Co ltd
Current assignee: Beijing Huahailong Technology Co ltd
Priority date: 2020-04-24
Filing date: 2020-04-24
Publication date: 2024-08-27
Anticipated expiration: 2040-04-24
Also published as: CN111382822A

Abstract

The invention relates to a chip, comprising a clock generator module, for generating a clock signal; the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or low level, the logic output is in a normal state; after the suspension of the OE signal or the low level is determined, if the working mode of the external clock module is selected, the RSET pin is externally connected with a pull-up resistor to the input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip; the logic generator module is used for outputting fixed time sequence logic according to the working mode of the internal clock module or the working mode of the external clock module; the chip provided by the invention selects the external clock input or the internal clock generation source through the configuration of the external pins, has a simple structure and low power consumption, improves the stability of products and reduces the hardware cost.

Description

Chip

Technical Field

The invention belongs to the technical field of electronics, and particularly relates to a chip.

Background

In the context of integration of industrialization and informatization, with rapid development of electronic information technology and continuous improvement of manufacturing level, radio frequency identification (Radio Frequency Identification, RFID) technology is considered as one of the most promising IT technologies in the 21 st century as a combination of wireless communication and automatic identification technologies, and has been widely used in various fields. The RFID tag reader/writer typically reads information such as an RFID electronic tag ID number in a radio frequency field according to an air interface protocol in the prior art. The passive electronic tag is convenient to install and use because the battery does not need to be replaced, and the application scene is wider than that of the active electronic tag.

In the related art, in a railway car number automatic identification system, along with the development of passive electronic tags, stability and reliability of the tags are increasingly required. At present, the tag is built through various devices, is relatively complex and unstable, and meanwhile, has high power consumption, needs larger starting current and has higher hardware cost.

Disclosure of Invention

In view of the above, the present invention aims to overcome the defects of the prior art, and provide a chip to solve the problems of complex and unstable chip product, high power consumption and high cost in the prior art.

In order to achieve the above purpose, the invention adopts the following technical scheme: a chip, comprising:

a clock generator module for generating a clock signal; the clock generator module comprises an internal clock module and an external clock module;

the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or low level, the logic output is in a normal state; after the OE signal is suspended or low level is determined, if an external clock module working mode is selected, a pull-up resistor is externally connected to an RSET pin to an input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;

and the logic generator module is used for outputting fixed sequential logic according to the working mode of the internal clock module or the working mode of the external clock module.

Further, the method further comprises the following steps:

And the clock switching module is used for switching the internal clock module and the external clock module according to the working mode selected by the enabling and mode selecting module.

Further, the clock generator module includes:

An RC oscillation circuit for setting an oscillation frequency of the clock signal;

The RC oscillation circuit comprises an oscillation current source and a reference resistor, wherein the reference resistor is a pull-down resistor externally connected with an RSET pin and is used for setting clock frequency;

and the clock stabilizing circuit is used for outputting after the clock frequency is stabilized.

Further, the internal clock module working modes include:

the reference module is used for establishing reference current/voltage to drive the clock generator module to work;

and one end of the reference module is connected with the clock generator module, and the other end of the reference module is connected with the enabling and mode selecting module.

Further, the external clock module working modes include:

A CLKIN pin disposed on the chip, the CLKIN pin being a clock input source;

The CLKIN pin inputs a clock signal to the logic generator module.

Further, the method further comprises the following steps:

The trimming module is used for trimming the RC oscillating circuit in real time to output stable clock frequency;

The trimming module is connected with the logic generator.

Further, the method further comprises the following steps:

a plurality of ESD protection modules for preventing the chip from electrostatic breakdown or damage;

the ESD protection module is arranged at a pin inlet and a pin outlet of the chip.

Further, the method further comprises the following steps:

And the power management module is used for providing input voltage for the chip.

Further, the power management module includes: the device comprises a voltage comparison module, a low-dropout voltage stabilizing module and a resetting module;

the voltage comparison module is used for comparing the input voltage with a first preset voltage and a second preset voltage;

The low dropout voltage regulator module is used for increasing the voltage range of the input voltage when the input voltage is larger than a first preset voltage;

The reset module is used for resetting when the input voltage is smaller than a second preset voltage.

Further, the method further comprises the following steps:

The voltage limiting module is used for limiting the voltage output by the power supply management module;

The power supply voltage detection module is used for monitoring the voltage value of the voltage limiting module, and outputting the voltage value when the voltage value output by the voltage limiting module is larger than the set starting voltage;

One end of the power supply voltage detection circuit is connected with the voltage limiting module, and the other end of the power supply voltage detection circuit is connected with the logic generator module.

By adopting the technical scheme, the invention has the following beneficial effects:

The invention provides a chip, which comprises a clock generator module, for generating a clock signal; the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or low level, the logic output is in a normal state; after the suspension of the OE signal or the low level is determined, if the working mode of the external clock module is selected, the RSET pin is externally connected with a pull-up resistor to the input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip; the logic generator module is used for outputting fixed time sequence logic according to the working mode of the internal clock module or the working mode of the external clock module; the chip provided by the invention selects the external clock input or the internal clock generation source through the configuration of the external pins, has a simple structure and low power consumption, improves the stability of products and reduces the hardware cost.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a chip according to the present invention;

Fig. 2 is a schematic workflow diagram of a chip according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, based on the examples herein, which are within the scope of the invention as defined by the claims, will be within the scope of the invention as defined by the claims.

A specific chip provided in the embodiments of the present application is described below with reference to the accompanying drawings.

As shown in fig. 1, the chip provided in the embodiment of the present application includes,

The working principle of the chip is as follows: as shown in fig. 2, an OE pin and a RSET pin are provided on the chip, and the ENABLE and mode selection module ENABLEs, and the ENABLE and mode selection module provides an OE signal through the OE pin, and first the OE signal is used as an input signal, which can control a logic output state: when the OE signal is suspended or at a low level, the logic output is in a normal state, and when the OE signal is at a high level, the logic output is in a high resistance state; after the OE signal is suspended or low level is determined, an internal clock module working mode or an external clock module working mode can be selected through an RSET pin, and if the external clock module working mode is selected, the RSET pin is externally connected with a pull-up resistor to the input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;

The RSET pin, one of which functions as part of the internal clock module, and the other function as the control terminal for clock switching ENABLE, that is, the RSET pin acts as the clock select terminal: when a pull-down resistor externally connected with the RSET is grounded, the pull-down resistor is selected as an internal clock module working mode, and the resistance value of the resistor can determine the frequency generated by the internal clock module; when RSET is pulled high, the working mode of the external clock module is selected, and a clock signal is input through the CLKIN pin and is used as a clock source of the whole chip. After the working mode is selected, the logic generator module is triggered by the external clock module or the internal clock module to generate fixed time sequence output, and the logic generator module can drive SPI slave devices with the same time sequence. In the application, CS is always kept at a low level after being switched from a high level to a low level, and SCK is always present, so that a logic generator module can continuously read.

The chip provided by the application can continuously read the special chip of the EEPROM, supports the standard SPI communication protocol, can realize the selection of an external clock input or an internal high-precision clock generation source through the configuration of an external pin RSET, and has a wide working voltage range of 1.7-5.5V; low power consumption: the external clock is 5uA and 3.3V, and the internal clock is 12uA and 3.3V.

As shown in fig. 1, a pin CS, CLKIN, SCK, SI, GND, OE, REST, VCC is disposed on the chip;

Wherein CS is configured to provide a chip select signal;

CLKIN is used for external clock input and when an internal clock is selected, the chip is pulled down internally;

the SCK is used for providing a clock signal;

SI is used to provide MOSI signals;

GND is chip ground;

OE is chip enable, CS, SCK, SI is high impedance state when OE is high level;

REST is a clock selection end, an external clock source is selected when the external resistor is pulled up, an internal clock is selected when the external resistor is grounded, and the clock frequency is set;

VCC is the chip power supply.

In some embodiments, further comprising:

Preferably, the clock generator module includes:

Specifically, the RC oscillation circuit sets the oscillation frequency of the clock signal and outputs the clock frequency, and the RC oscillation circuit further comprises an external RSET resistor and an internal adjustable capacitor. The reference resistor in the RC oscillation circuit is arranged outside the chip, so that the frequency output precision and stability can be obviously improved, and meanwhile, the clock generator module further comprises a clock stabilizing circuit which is provided for the logic generator module after clock stabilization.

In some embodiments, the internal clock module operating mode includes:

Specifically, the reference module REF is only enabled when the internal clock module is in the operation mode, and its main function is to establish a reference current/voltage and drive the internal clock module OSC to operate; EN is used as an enable switch signal of the reference module, and when en=0, the module does not work; ref_OK provides a reference OK signal for the subsequent circuit; LV is the output voltage of the LDO of the internal low dropout regulator, and provides a stable power supply for other circuits, when VCC is lower than 2.25V (typical value), lv=vcc, and when VCC >2.25V, lv=2.25V.

Preferably, the external clock module working modes include:

A CLKIN pin disposed on the chip, the CLKIN pin being a clock input source;

The CLKIN pin inputs a clock signal to the logic generator module.

When an external clock module is selected, a clock signal is input to the logic generator module through the CLKIN pin.

Preferably, the chip provided by the application further comprises:

The trimming module is used for real-time trimming the RC oscillating circuit to output stable oscillating frequency;

The trimming module is connected with the logic generator.

Specifically, the trimming module can correct the internal capacitance circuit of the chip in real time, so that stable clock frequency output is generated.

Preferably, the method further comprises:

And a plurality of ESD protection modules for preventing the chip from electrostatic breakdown or damage.

In the application, as shown in fig. 1, the chip comprises a plurality of pins, and each pin is provided with an ESD protection module to prevent the chip from being broken down or damaged by static electricity when connected with other electronic devices.

In some embodiments, further comprising:

Preferably, the power management module includes: the device comprises a voltage comparison module, a low-dropout voltage stabilizing module and a resetting module;

The comparator module is used for selecting whether to use an internal low dropout regulator (LDO), the input voltage range is greatly improved due to the increase of the LDO, but the power consumption is increased, the LDO module is not selected when the input voltage is smaller than a first preset voltage of 2.25V, at this time, the input voltage directly provides voltage to each module in the chip, the LDO module is selected when the input voltage is larger than the first preset voltage of 2.25V, and the voltage of each module in the chip is provided by the LDO module;

The reset module is realized according to the input voltage, and when the input voltage is greater than 1.75V, the chip starts to work and outputs a logic time sequence; when the input voltage is smaller than the second preset voltage by 1.45V, the chip is reset, and only when the voltage is larger than 1.75V again, the logic time sequence is output again.

Preferably, the chip further comprises:

In summary, the invention provides a chip, which includes a clock generator module, an enabling and mode selecting module and a logic generator module, and selects an external clock input or an internal clock generating source through external pin configuration, so as to support standard SPI communication, thereby realizing simple structure, low power consumption, improving product stability and reducing hardware cost.

It can be understood that the system embodiments provided above correspond to the method embodiments described above, and the corresponding specific details may be referred to each other, which is not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip, comprising:

the logic generator module is used for outputting fixed time sequence logic according to the working mode of the internal clock module or the working mode of the external clock module;

The clock generator module further includes:

the clock stabilizing circuit is used for outputting after the clock frequency is stabilized;

the internal clock module working mode comprises the following steps:

One end of the reference module is connected with the clock generator module, and the other end of the reference module is connected with the enabling and mode selecting module;

the external clock module working mode comprises the following steps:

A CLKIN pin disposed on the chip, the CLKIN pin being a clock input source;

The CLKIN pin inputs a clock signal to the logic generator module.

2. The chip of claim 1, further comprising:

3. The chip of claim 1, further comprising:

The trimming module is connected with the logic generator.

4. The chip of claim 1, further comprising:

5. The chip of claim 4, further comprising:

6. The chip of claim 5, wherein the power management module comprises: the device comprises a voltage comparison module, a low-dropout voltage stabilizing module and a resetting module;

7. The chip of claim 6, further comprising: