CN111371067A - Load overload step-increasing delay protection circuit - Google Patents
Load overload step-increasing delay protection circuit Download PDFInfo
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- CN111371067A CN111371067A CN202010316995.8A CN202010316995A CN111371067A CN 111371067 A CN111371067 A CN 111371067A CN 202010316995 A CN202010316995 A CN 202010316995A CN 111371067 A CN111371067 A CN 111371067A
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- 238000007493 shaping process Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 71
- 238000010586 diagram Methods 0.000 description 2
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/027—Details with automatic disconnection after a predetermined time
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
- H02H7/1227—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters responsive to abnormalities in the output circuit, e.g. short circuit
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Abstract
The invention relates to a load overload step-increasing delay protection circuit. The load overload step-up delay protection circuit is applied to a UPS system or an inverter system and comprises a shaping circuit, a first comparison circuit, a second comparison circuit, an exclusive-OR gate circuit, a trigger timing circuit, a reset timing circuit and an overload protection circuit, wherein the trigger timing circuit comprises a monostable trigger U1, and the reset timing circuit comprises a D-type trigger U2. Compared with the traditional overload delay protection circuit, the load overload step-up delay protection circuit provided by the application controls the UPS system or the inverter system through the delay circuit, reduces equipment operation faults and simultaneously considers short-time sudden change of the load; and a pure analog device is adopted, so that parameters are convenient to modify, the cost is low, and the universality is high.
Description
Technical Field
The invention relates to the technical field of application of uninterruptible power supplies and inverters, in particular to a load overload step-increasing delay protection circuit.
Background
At present, an overload delay protection circuit adopted by an Uninterruptible Power Supply (UPS)/inverter system generally comprises a processing chip such as a single chip or a DSP and peripheral circuits thereof, and mainly realizes the overload delay protection of the UPS/inverter system through a software program in the processing chip. However, such overload delay protection circuits that rely on software control are costly and have low reliability.
Disclosure of Invention
The invention aims to provide a load overload step-up delay protection circuit with low cost and high reliability.
In order to realize the purpose of the invention, the invention adopts the following technical scheme:
a load overload step-up delay protection circuit is applied to a UPS system or an inverter system and comprises a shaping circuit, a first comparison circuit, a second comparison circuit, an exclusive-OR gate circuit, a trigger timing circuit, a reset timing circuit and an overload protection circuit, wherein the trigger timing circuit comprises a monostable trigger U1, the reset timing circuit comprises a D-type trigger U2, wherein,
the output end of the shaping circuit is respectively connected with the input end of the first comparison circuit and the input end of the second comparison circuit, and the output end of the first comparison circuit is respectively connected with the input end of the XOR gate circuit, the RESET end of the D-type flip-flop U2 and the A0 end of the monostable flip-flop U1; the output end of the second comparison circuit is connected with the SET end of the D-type flip-flop U2;
of said monostable flip-flop U1
The end of the D-type flip-flop U2 is connected with the CLK end of the D-type flip-flop U2, the output end of the XOR gate circuit is connected with the CD end of the monostable flip-flop U1, the Q end of the D-type flip-flop U2 is connected with the input end of the overload protection circuit, and a signal output by the output end of the overload protection circuit is used for controlling the working state of the UPS system/inverter system.
Compared with the traditional overload delay protection circuit, the load overload step-up delay protection circuit provided by the application controls the UPS system or the inverter system through the delay circuit, reduces equipment operation faults and simultaneously considers short-time sudden change of the load; and a pure analog device is adopted, so that parameters are convenient to modify, the cost is low, and the universality is high.
In one embodiment, the shaping circuit comprises a rectifier bridge stack and a voltage dividing circuit, the voltage dividing circuit comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a diode D1, a positive power output end of the rectifier bridge stack is connected with a first end of the resistor R1 and a first end of the resistor R3 respectively, and a negative power output end of the rectifier bridge stack is connected with a second end of the resistor R3 to ground; the second terminal of the resistor R1 is connected to the first terminal of the resistor R2 and the first terminal of the capacitor C1 through the diode D1, and the second terminal of the resistor R2 and the second terminal of the capacitor C1 are grounded.
In one embodiment, the second comparison circuit comprises a resistor R4, a resistor R5, a resistor R6, a capacitor C2 and a comparator U3, wherein a non-inverting input terminal of the comparator U3 is connected with a first terminal of the capacitor C1; the negative phase input end of the comparator U3 is simultaneously connected with the first end of the resistor R4, the first end of the resistor R5 and the first end of the capacitor C2, the second end of the resistor R5 is connected with the positive electrode of a power supply, and the second end of the resistor R4 and the second end of the capacitor C2 are grounded; the output end of the comparator U3 is respectively connected with the first end of the resistor R6 and the SET end of the D-type flip-flop U2, and the second end of the resistor R6 is connected with the positive pole of a power supply.
In one embodiment, the first comparison circuit comprises a resistor R7, a resistor R8, a resistor R9, a resistor R10 and a comparator U4, wherein the negative phase input end of the comparator U4 is connected with the first end of the capacitor C1; a non-inverting input terminal of the comparator U4 is respectively connected to the first terminal of the resistor R7, the first terminal of the resistor R8, and the first terminal of the resistor R9, a second terminal of the resistor R8 is respectively connected to the first terminal of the resistor R10, the output terminal of the comparator U4, and the RESET terminal of the D-type flip-flop U2, a second terminal of the resistor R7 is grounded, and a second terminal of the resistor R9 and the second terminal of the resistor R10 are connected to a positive terminal of a power supply.
In one embodiment, the exclusive-or gate circuit comprises an exclusive-or gate chip U5, a resistor R11, a resistor R12, a diode D2, a capacitor C3 and a capacitor C4, wherein a first input end of the exclusive-or gate chip U5 is connected with a positive electrode of a power supply; a second input end of the exclusive-or gate chip U5 is connected with an output end of the comparator U4; the output end of the exclusive-or gate chip U5 is connected to the first end of the capacitor C3 and the first end of the resistor R12, the second end of the capacitor C3 is connected to the first end of the resistor R11, the anode of the diode D2 and the CD end of the monostable flip-flop U1, the second end of the resistor R11 and the cathode of the diode D2 are connected to the anode of a power supply, and the second end of the resistor R12 is grounded through the capacitor C4.
In one embodiment, the overload protection circuit includes a resistor R13, a resistor R14, a resistor R15, a diode D3, a capacitor C5, a capacitor C6, a zener diode ZD1, and a transistor Q1, a first end of the resistor R13 is connected to the Q terminal of the D-type flip-flop U2, a second end of the resistor R13 is connected to the first end of the capacitor C5 and the cathode of the zener diode ZD1, an anode of the zener diode ZD1 is connected to the first end of the resistor R14 and the base of the transistor Q695 1, a collector of the transistor Q1 is connected to the anode of the diode D2 and the first end of the resistor R15, a cathode of the diode D3 and a second end of the resistor R15 are connected to the positive power supply, a first end of the capacitor C6 is connected to the first end of the resistor R15, and a second end of the capacitor C5 and a second end of the capacitor C8672 are connected to the positive power supply, The emitter of the transistor Q1 and the second terminal of the resistor R14 are both grounded, and the signal output from the first terminal of the resistor R15 is used to control the operation state of the UPS system/inverter system.
In one embodiment, the trigger timing circuit further includes a diode D4, a resistor R16, a resistor R17, and a capacitor C7, a first end of the resistor R16 is connected to the T2 end of the monostable flip-flop U1, a second end of the resistor R16 is connected to the anode of the diode D4, the first end of the resistor R17, and the first end of the capacitor C7, the cathode of the diode D4 and the second end of the resistor R17 are both connected to the anode of the power supply, and the second end of the capacitor C7 is connected to the ground.
In one embodiment, the monostable flip-flop U1 is a monostable flip-flop of type CD4538BN, and the D-type flip-flop U2 is a D-type flip-flop of type CD 4013.
Drawings
Fig. 1 is a schematic structural diagram of a load overload step-up delay protection circuit according to an embodiment;
fig. 2 is a schematic circuit diagram of an embodiment of a load overload step-up delay protection circuit.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Referring to fig. 1 and 2, the present embodiment provides a load overload step-up delay protection circuit applied to a UPS system or an inverter system, including a shaping circuit 100, a first comparison circuit 200, a second comparison circuit 300, an xor gate circuit 400, a trigger timing circuit 500, a reset timing circuit 600, and an overload protection circuit 700, where the trigger timing circuit 500 includes a monostable flip-flop U1, and the reset timing circuit 600 includes a D-type flip-flop U2, where,
the output end of the shaping circuit 100 is respectively connected with the input end of the first comparison circuit 200 and the input end of the second comparison circuit 300, and the output end of the first comparison circuit 200 is respectively connected with the input end of the exclusive-or gate circuit 400, the RESET end of the D-type flip-flop U2 and the A0 end of the monostable flip-flop U1; the output end of the second comparison circuit 300 is connected with the SET end of the D-type flip-flop U2;
of monostable flip-flop U1
The end of the D-type trigger U2 is connected with the CLK end, the output end of the exclusive-OR gate circuit 400 is connected with the CD end of the monostable trigger U1, the Q end of the D-type trigger U2 is connected with the input end of the overload protection circuit 700, and a signal output by the output end of the overload protection circuit 700 is used for controlling the working state of the UPS system/inverter system.
In this embodiment, the shaping circuit 100 may include a rectifier bridge stack (diodes D5-D8) and a voltage divider circuit, where the voltage divider circuit may include a resistor R1, a resistor R2, a resistor R3, a capacitor C1, and a diode D1, a positive output terminal of the rectifier bridge stack is connected to the first terminal of the resistor R1 and the first terminal of the resistor R3, and a negative output terminal of the rectifier bridge stack is grounded to the second terminal of the resistor R3; the second terminal of the resistor R1 is connected to the first terminal of the resistor R2 and the first terminal of the capacitor C1 through the diode D1, and the second terminal of the resistor R2 and the second terminal of the capacitor C1 are grounded.
In this embodiment, the second comparing circuit 300 may include a resistor R4, a resistor R5, a resistor R6, a capacitor C2, and a comparator U3, wherein a non-inverting input terminal of the comparator U3 is connected to a first terminal of the capacitor C1; the negative phase input end of the comparator U3 is simultaneously connected with the first end of the resistor R4, the first end of the resistor R5 and the first end of the capacitor C2, the second end of the resistor R5 is connected with the positive electrode of the 12V power supply, and the second end of the resistor R4 and the second end of the capacitor C2 are grounded; the output end of the comparator U3 is respectively connected with the first end of the resistor R6 and the SET end of the D-type flip-flop U2, and the second end of the resistor R6 is connected with the positive electrode of the 12V power supply.
In this embodiment, the first comparing circuit 100 may include a resistor R7, a resistor R8, a resistor R9, a resistor R10, and a comparator U4, wherein a negative phase input terminal of the comparator U4 is connected to a first terminal of the capacitor C1; the positive phase input end of the comparator U4 is respectively connected with the first end of the resistor R7, the first end of the resistor R8 and the first end of the resistor R9, the second end of the resistor R8 is respectively connected with the first end of the resistor R10, the output end of the comparator U4 and the RESET end of the D-type flip-flop U2, the second end of the resistor R7 is grounded, and the second end of the resistor R9 and the second end of the resistor R10 are connected with the positive pole of a 12V power supply.
In this embodiment, the xor gate circuit 400 may include an xor gate chip U5, a resistor R11, a resistor R12, a diode D2, a capacitor C3, and a capacitor C4, wherein a first input terminal of the xor gate chip U5 is connected to the positive electrode of the 12V power supply; a second input end of the exclusive-or gate chip U5 is connected with an output end of the comparator U4; the output end of the exclusive-or gate chip U5 is respectively connected with the first end of a capacitor C3 and the first end of a resistor R12, the second end of the capacitor C3 is simultaneously connected with the first end of a resistor R11, the anode of a diode D2 and the CD end of a monostable trigger U1, the second end of the resistor R11 and the cathode of the diode D2 are respectively connected with the anode of a 12V power supply, and the second end of the resistor R12 is grounded through the capacitor C4.
In this embodiment, the overload protection circuit may include a resistor R13, a resistor R14, a resistor R15, a diode D3, a capacitor C5, a capacitor C6, a zener diode ZD1, and a transistor Q1, a first end of the resistor R13 is connected to the Q terminal of the D-type flip-flop U2, a second end of the resistor R13 is connected to the first end of the capacitor C5 and the negative electrode of the zener diode ZD1, an anode of the zener diode ZD1 is connected to the first end of the resistor R14 and the base of the transistor Q1, a collector of the transistor Q1 is connected to the anode of the diode D3 and the first end of the resistor R15, a cathode of the diode D3 and a second end of the resistor R15 are connected to the positive power supply, a first end of the capacitor C6 is connected to the first end of the resistor R15, a second end of the capacitor C5, a second end of the capacitor C6, an emitter of the transistor Q1, and a second end of the resistor R14, and the signal output from the first terminal of the resistor R15 is used to control the operation state of the UPS system/inverter system.
In this embodiment, the trigger timing circuit 500 may further include a diode D4, a resistor R16, a resistor R17, and a capacitor C7, wherein a first end of the resistor R16 is connected to the T2 end of the monostable flip-flop U1, a second end of the resistor R16 is connected to an anode of the diode D4, a first end of the resistor R17, and a first end of the capacitor C7, a cathode of the diode D4 and a second end of the resistor R17 are both connected to an anode of the power supply, and a second end of the capacitor C7 is grounded.
Specifically, the monostable flip-flop U1 may be a monostable flip-flop of type CD4538BN, and the D type flip-flop U2 may be a D type flip-flop of type CD 4013.
The working principle of the load overload step-up delay protection circuit provided by the embodiment is as follows:
referring to fig. 2, when the output of the UPS system/inverter system is overloaded, the current signal at the load end is sent to CN1, rectified by the rectifier bridge stack (diodes D5-D8) and then applied to the two ends of the resistor R3 to form a voltage signal V1 in equal proportion to the load current, and the voltage can be changed by changing the size of the resistor R3, which is suitable for the overload modification of UPS systems/inverter systems with different powers. Specifically, the resistor R3 may be a sliding varistor.
The voltage signal V1 obtained by shaping is divided by a resistor R1/a resistor R2/a diode D1 and filtered by a capacitor C1 to generate two paths of signals, one path of the signals is sent to the 8 th pin of a comparator U4, and the other path of the signals is sent to the 11 th pin of a comparator U3, so that two voltage comparators (corresponding to the first stage (105% -150% of overload current value) and the second stage (more than 150% of overload current value)) are respectively formed.
When the UPS system/inverter system is overloaded, namely the load exceeds the current value of 105% overload, the pin 8 voltage of the comparator U3 is higher than the pin 9 voltage, so that the pin 14 outputs low level, and the D-type flip-flop U2 is reset; meanwhile, the low level output from pin 14 is sent to pin 5 (terminal A0) of the monostable flip-flop U1; the 1 st pin of the exclusive-or gate U4 is inconsistent with the 2 nd pin thereof, so that the output of the 3 rd pin thereof becomes high level, the trigger pulse is sent to the 3 rd pin (CD end) of the monostable trigger U1 through the capacitor C3, and the trigger is reset; under the combined action of the 5 th pin (A0 end) of the monostable flip-flop U1, the flip-flop starts to work, the external R/C of the flip-flop is a resistor R17 and a capacitor C7, the capacitor C7 is charged by the resistor R17 at the moment, the charging time is the overload time of the first stage, after the charging is finished, the flip-flop is turned over, the 7 th pin (A0 end) of the flip-flop U1
End) outputs high level, the high level is sent to a pin 3 (CLK end) of a D-type flip-flop U2, a pin 1 (Q end) of the D-type flip-flop U2 outputs high level, and after being filtered by an RC (resistor) consisting of a resistor R13 and a capacitor C5, a voltage stabilizing diode ZD1 is broken down, so that a triode Q1 is conducted, and an INV-OFF signal is pulled to be lowLevel, shut down UPS system/inverter system.
When the load exceeds the current value of 150% overload, the 11 th pin of the comparator U3 is higher than the 10 th pin thereof, so that the 13 th pin thereof outputs high level, the D-type flip-flop U1 is set and overturned, the 1 st pin (Q end) of the D-type flip-flop U2 outputs high level, the INV-OFF signal is pulled to low level, and the UPS system/inverter system immediately enters an automatic shutdown state to prevent the power tube or IGBT from being damaged.
Compared with the traditional overload delay protection circuit, the load overload step-up delay protection circuit provided by the application controls the UPS system or the inverter system through the delay circuit, reduces equipment operation faults and simultaneously considers short-time sudden change of the load; and a pure analog device is adopted, so that parameters are convenient to modify, the cost is low, and the universality is high.
It should be noted that the load overload step-up delay protection circuit provided in this embodiment can operate according to this logic regardless of whether the UPS system/inverter system is directly overloaded by more than 150% of overloaded current value or is increased from 120% of overloaded current value to more than 150% of overloaded current value.
If the UPS system/inverter system is overloaded in the first stage (in the range of 105% -150%) only for a short time, after the monostable trigger U1 starts to work in a timing mode, the overload is cancelled, the 14 th pin output of the comparator U4 becomes high level, the monostable trigger U1 is reset, and the normal work of the UPS system/inverter system is not influenced.
If a stage of overload setting is needed to be added, a circuit can be added in the same way, and the circuits do not influence each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A load overload step-up delay protection circuit is applied to a UPS system or an inverter system and is characterized by comprising a shaping circuit, a first comparison circuit, a second comparison circuit, an exclusive-OR gate circuit, a trigger timing circuit, a reset timing circuit and an overload protection circuit, wherein the trigger timing circuit comprises a monostable trigger U1, the reset timing circuit comprises a D-type trigger U2,
the output end of the shaping circuit is respectively connected with the input end of the first comparison circuit and the input end of the second comparison circuit, and the output end of the first comparison circuit is respectively connected with the input end of the XOR gate circuit, the RESET end of the D-type flip-flop U2 and the A0 end of the monostable flip-flop U1; the output end of the second comparison circuit is connected with the SET end of the D-type flip-flop U2;
of said monostable flip-flop U1
The end of the D-type flip-flop U2 is connected with the CLK end of the D-type flip-flop U2, the output end of the XOR gate circuit is connected with the CD end of the monostable flip-flop U1, the Q end of the D-type flip-flop U2 is connected with the input end of the overload protection circuit, and a signal output by the output end of the overload protection circuit is used for controlling the working state of the UPS system/inverter system.
2. The load overload step-up delay protection circuit according to claim 1, wherein the shaping circuit comprises a rectifier bridge stack and a voltage divider circuit, the voltage divider circuit comprises a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a diode D1, a positive electrical output terminal of the rectifier bridge stack is connected to a first terminal of the resistor R1 and a first terminal of the resistor R3, respectively, and a negative electrical output terminal of the rectifier bridge stack is connected to a second terminal of the resistor R3; the second terminal of the resistor R1 is connected to the first terminal of the resistor R2 and the first terminal of the capacitor C1 through the diode D1, and the second terminal of the resistor R2 and the second terminal of the capacitor C1 are grounded.
3. The load overload step-up delay protection circuit of claim 2, wherein the second comparison circuit comprises a resistor R4, a resistor R5, a resistor R6, a capacitor C2 and a comparator U3, and a non-inverting input terminal of the comparator U3 is connected to a first terminal of the capacitor C1; the negative phase input end of the comparator U3 is simultaneously connected with the first end of the resistor R4, the first end of the resistor R5 and the first end of the capacitor C2, the second end of the resistor R5 is connected with the positive electrode of a power supply, and the second end of the resistor R4 and the second end of the capacitor C2 are grounded; the output end of the comparator U3 is respectively connected with the first end of the resistor R6 and the SET end of the D-type flip-flop U2, and the second end of the resistor R6 is connected with the positive pole of a power supply.
4. The load overload step-up delay protection circuit of claim 3, wherein the first comparison circuit comprises a resistor R7, a resistor R8, a resistor R9, a resistor R10 and a comparator U4, and a negative phase input end of the comparator U4 is connected with a first end of the capacitor C1; a non-inverting input terminal of the comparator U4 is respectively connected to the first terminal of the resistor R7, the first terminal of the resistor R8, and the first terminal of the resistor R9, a second terminal of the resistor R8 is respectively connected to the first terminal of the resistor R10, the output terminal of the comparator U4, and the RESET terminal of the D-type flip-flop U2, a second terminal of the resistor R7 is grounded, and a second terminal of the resistor R9 and the second terminal of the resistor R10 are connected to a positive terminal of a power supply.
5. The load overload step-up delay protection circuit according to claim 4, wherein the XOR gate circuit comprises an XOR gate chip U5, a resistor R11, a resistor R12, a diode D2, a capacitor C3 and a capacitor C4, and a first input end of the XOR gate chip U5 is connected with a positive electrode of a power supply; a second input end of the exclusive-or gate chip U5 is connected with an output end of the comparator U4; the output end of the exclusive-or gate chip U5 is connected to the first end of the capacitor C3 and the first end of the resistor R12, the second end of the capacitor C3 is connected to the first end of the resistor R11, the anode of the diode D2 and the CD end of the monostable flip-flop U1, the second end of the resistor R11 and the cathode of the diode D2 are connected to the anode of a power supply, and the second end of the resistor R12 is grounded through the capacitor C4.
6. The overload step-up delay protection circuit according to claim 5, wherein the overload protection circuit comprises a resistor R13, a resistor R14, a resistor R15, a diode D3, a capacitor C5, a capacitor C6, a Zener diode ZD1 and a transistor Q1, a first end of the resistor R13 is connected to the Q terminal of the D-type flip-flop U2, a second end of the resistor R13 is connected to a first end of the capacitor C5 and the cathode of the Zener diode ZD1, an anode of the Zener diode ZD1 is connected to a first end of the resistor R14 and the base of the transistor Q1, a collector of the transistor Q1 is connected to the anode of the diode D3 and the first end of the resistor R15, a cathode of the diode D3 and a second end of the resistor R15 are connected to the anode of the power supply, a first end of the capacitor C6 is connected to the first end of the resistor R15, the second terminal of the capacitor C5, the second terminal of the capacitor C6, the emitter of the transistor Q1, and the second terminal of the resistor R14 are all grounded, and a signal output from the first terminal of the resistor R15 is used to control the operating state of the UPS system/inverter system.
7. The load overload step-up delay protection circuit of claim 6, wherein the trigger timing circuit further comprises a diode D4, a resistor R16, a resistor R17 and a capacitor C7, a first end of the resistor R16 is connected to the T2 end of the monostable flip-flop U1, a second end of the resistor R16 is connected to the anode of the diode D4, the first end of the resistor R17 and the first end of the capacitor C7, the cathode of the diode D4 and the second end of the resistor R17 are both connected to the anode of the power supply, and the second end of the capacitor C7 is connected to ground.
8. The load overload step-up delay protection circuit according to claim 7, wherein the one-shot U1 is a CD4538BN type one-shot, and the D-shot U2 is a CD4013 type D-shot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010316995.8A CN111371067B (en) | 2020-04-21 | Load overload step-by-step delay protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010316995.8A CN111371067B (en) | 2020-04-21 | Load overload step-by-step delay protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111371067A true CN111371067A (en) | 2020-07-03 |
| CN111371067B CN111371067B (en) | 2024-07-02 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN211530722U (en) * | 2020-04-21 | 2020-09-18 | 东莞市台诺电子有限公司 | Load overload step-increasing delay protection circuit |
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| US20020074974A1 (en) * | 2000-12-14 | 2002-06-20 | Kaoru Shinba | Method and apparatus for overload-controlling inverter power generation apparatus |
| US20060176634A1 (en) * | 2005-02-04 | 2006-08-10 | Topower Computer Industrial Co., Ltd. | Current-limiting protection circuit for a power supply |
| WO2008119293A1 (en) * | 2007-03-30 | 2008-10-09 | Haoyi Lu | Circuit protection and control system, and protection and control method applying the system |
| CN103441467A (en) * | 2013-05-22 | 2013-12-11 | 佛山市宝星科技发展有限公司 | Load nonlinear progressively-increasing delay protection circuit |
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| CN104955225A (en) * | 2014-11-27 | 2015-09-30 | 成都雷克尔科技有限公司 | Combined protective logic amplification type blue light LED lamp protection system |
| CN205489443U (en) * | 2015-12-31 | 2016-08-17 | 深圳市汇川技术股份有限公司 | Power overcurrent protection circuit |
| CN211530722U (en) * | 2020-04-21 | 2020-09-18 | 东莞市台诺电子有限公司 | Load overload step-increasing delay protection circuit |
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