CN111370427A - Array substrate - Google Patents
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- CN111370427A CN111370427A CN202010191364.8A CN202010191364A CN111370427A CN 111370427 A CN111370427 A CN 111370427A CN 202010191364 A CN202010191364 A CN 202010191364A CN 111370427 A CN111370427 A CN 111370427A
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 239000013078 crystal Substances 0.000 claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 abstract description 22
- 230000008025 crystallization Effects 0.000 abstract description 22
- 238000005224 laser annealing Methods 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides an array substrate which comprises a substrate, a buffer layer, a dielectric layer, a planarization layer, a first electrode and a pixel limiting layer. The a-Si (amorphous silicon) is arranged in the buffer layer corresponding to the channel of the active layer and serves as a crystal nucleus of a subsequent active layer during ELA (excimer laser annealing) crystallization, the a-Si is required to be located under the channel of the active layer, the width and the length of the a-Si are equal to those of the channel of the active layer, and the a-Si under the channel of the active layer serves as the crystal nucleus during crystallization of the channel of the active layer, so that the channel of the active layer can realize fixed-point crystallization of the ELA, crystal grains are increased, crystal boundaries are reduced, the uniformity of the ELA crystallization is greatly improved, the electrical uniformity of the switching TFT and the driving TFT is improved, and the yield of LTPS is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate of low-temperature polycrystalline silicon.
Background
In the conventional process of manufacturing LTPS-TFT (low temperature polysilicon thin film transistor), amorphous silicon (a-Si) is deposited on a substrate, and then Excimer Laser Annealing (ELA) is used to anneal and crystallize the a-Si to form polysilicon, but the crystallization in this method is a whole-surface crystallization, has no fixed direction, and the obtained crystal grains have poor uniformity, smaller crystal grains and more grain boundaries, which may affect the mobility of carriers and the leakage current of TFT devices, resulting in poor electrical uniformity of switching TFTs and driving TFTs, thereby directly affecting the light Emitting characteristics of organic light-Emitting Diode (OLED) devices and seriously affecting the yield of low temperature polysilicon technology (LTPS) preparation.
Therefore, the invention provides an array substrate, which is used for enabling the crystalline grains of an active layer to have better uniformity and improving the electrical uniformity of a switch TFT and a driving TFT.
Disclosure of Invention
The invention aims to solve the technical problem of providing an array substrate.A-Si (amorphous silicon) is arranged in a buffer layer corresponding to a channel of an active layer and is used as a crystal nucleus of a subsequent active layer during ELA (excimer laser annealing) crystallization, so that the channel of the active layer can realize the fixed-point crystallization of the ELA, crystal grains are enlarged, crystal boundaries are reduced, the uniformity of the ELA crystallization is greatly improved, and meanwhile, the electrical uniformity of a switching TFT and a driving TFT is improved, thereby improving the yield of LTPS.
In order to solve the above problems, the present invention provides an array substrate, including a substrate; the buffer layer is arranged on one side of the substrate; the dielectric layer is arranged on one side of the buffer layer, which is far away from the substrate, and a switch thin film transistor and a driving thin film transistor which are transversely arranged are arranged in the dielectric layer; the planarization layer is arranged on one side of the dielectric layer, which is far away from the buffer layer; and crystal nuclei are arranged on one side of the buffer layer close to the dielectric layer and correspond to channels of the active layers of the switch thin film transistor and the driving thin film transistor.
Further, the dielectric layer includes: the first insulating layer is arranged on one side, far away from the substrate, of the buffer layer; the second insulating layer is arranged on one side, far away from the buffer layer, of the first insulating layer; the third insulating layer is arranged on one side, far away from the first insulating layer, of the second insulating layer; and the passivation layer is arranged on one side of the second insulating layer far away from the first insulating layer.
Further, the structures of the switching thin film transistor and the driving thin film transistor both include: the active layer is arranged on the buffer layer and is coated by the first insulating layer; the grid electrode is arranged on the first insulating layer and is coated by the second insulating layer, and the grid electrode corresponds to the active layer; and the source and drain electrode layer is arranged on the second insulating layer and is coated by the passivation layer, the source and drain electrode layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected with the active layer.
Furthermore, the active layer of the driving thin film transistor further comprises an extension part which is arranged between the switch thin film transistor and the driving thin film transistor.
Further, the material of the crystal nucleus is amorphous silicon; and/or the material of the active layer is polysilicon.
Further, the width of the channel is equal to the width of the crystal nucleus.
Furthermore, the second insulating layer is provided with a first through hole, and the first through hole penetrates through the first insulating layer and part of the second insulating layer to reach the surface of the active layer; the source drain electrode layer is connected with the active layer through the first through hole.
Further, the material of the grid electrode comprises metal molybdenum.
Further, still include: the first electrode is arranged on one side, far away from the dielectric layer, of the planarization layer and is connected with the driving thin film transistor; the pixel limiting layer is arranged on the planarization layer and the first electrode and is provided with a groove which is sunken downwards to the surface of the first electrode.
Furthermore, the planarization layer is provided with a second through hole, the second through hole penetrates through the planarization layer and part of the passivation layer to reach the surface of the source/drain electrode layer, and the first electrode is connected with the source electrode of the source/drain electrode layer through the second through hole.
The invention has the beneficial effects that: the invention provides an array substrate, which is characterized in that a-Si (amorphous silicon) is arranged in a buffer layer corresponding to an active layer channel and is used as a crystal nucleus of a subsequent active layer during ELA (excimer laser annealing) crystallization, the a-Si is required to be positioned right below the active layer channel, the width and the length of the a-Si are equal to those of the active layer channel, and the a-Si right below the active layer channel is used as the crystal nucleus during the crystallization of the active layer channel, so that the active layer channel can realize the fixed-point crystallization of the ELA, crystal grains are increased, crystal boundaries are reduced, the uniformity of the ELA crystallization is greatly improved, the electrical uniformity of a switching TFT and a driving TFT is improved, and the yield of LTPS is improved.
Drawings
The invention is further described below with reference to the figures and examples.
Fig. 1 is a schematic structural diagram of an array substrate provided in the present invention.
An array substrate 100;
a substrate 101; a buffer layer 102; a dielectric layer 103;
a planarization layer 104; a first electrode 107; a pixel defining layer 106;
a first insulating layer 1031; a second insulating layer 1032; a third insulating layer 1033;
a passivation layer 1034; an active layer 1101; a gate 1102;
a source-drain electrode layer 1103; a channel 1105; a first via 1104;
a second through hole 1041; a slot 1061; an extension 1106;
a crystal nucleus 105.
Detailed Description
In order that the present invention may be better understood, the following examples are included to further illustrate the invention, but not to limit its scope.
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
As shown in fig. 1, an array substrate 100 of the present invention includes a substrate 101, a buffer layer 102, a dielectric layer 103, a planarization layer 104, a first electrode 107, and a pixel defining layer 106.
The buffer layer 102 is arranged on one side of the substrate 101; the buffer layer 102 is formed by a lamination of at least two layers, and the material of each lamination comprises silicon nitride or silicon oxide.
The dielectric layer 103 is disposed on a side of the buffer layer 102 away from the substrate 101, and a switching thin film transistor and a driving thin film transistor disposed in a transverse direction are disposed in the dielectric layer 103. The material of the dielectric layer 103 includes silicon nitride or silicon oxide.
The dielectric layer 103 includes: a first insulating layer 1031, a second insulating layer 1032, a third insulating layer 1033, and a passivation layer 1034.
The first insulating layer 1031 is disposed on a side of the buffer layer 102 away from the substrate 101; the second insulating layer 1032 is disposed on a side of the first insulating layer 1031 away from the buffer layer 102; the third insulating layer 1033 is disposed on a side of the second insulating layer 1032 remote from the first insulating layer 1031.
The passivation layer 1034 is disposed on a side of the second insulating layer 1032 far from the first insulating layer 1031, and is made of silicon nitride.
The second insulating layer 1032 has a first via 1104, and the first via 1104 penetrates through the first insulating layer 1031 and a portion of the second insulating layer 1032 to the surface of the active layer 1101.
The planarization layer 104 is disposed on a side of the dielectric layer 103 away from the buffer layer.
A crystal nucleus 105 is disposed on one side of the buffer layer close to the dielectric layer 103, and the crystal nucleus 105 corresponds to the channels 1105 of the active layers 1101 of the switching thin film transistor and the driving thin film transistor.
The material of the crystal nucleus 105 is amorphous silicon. The specific preparation method comprises the steps that buffer layers are sequentially manufactured on a substrate 101, patterned a-Si (amorphous silicon) is required to have a special shape, namely the width and the length of the a-Si are equal to those of an active layer channel; then a layer of integral a-Si is deposited. ELA crystallization is utilized, and at the moment, the ELA crystallization takes patterned a-Si as a crystal nucleus to realize fixed-point crystallization and greatly improve the size and uniformity of crystals at a channel;
the structures of the switch thin film transistor and the driving thin film transistor comprise: the active layer 1101, the gate 1102 and the source drain electrode layer 1103.
The active layer 1101 is disposed on the buffer layer and is covered by the first insulating layer 1031; the material of the active layer 1101 is polysilicon. The width of the channel 1105 is equal to the width of the crystal nucleus 105.
When the active layer channel 1105 is crystallized, the a-Si right below the channel 1105 is used as the crystal nucleus 105, so that the channel 1105 of the active layer 1101 can realize fixed point crystallization, the crystal grains are enlarged, the crystal boundary is reduced, the uniformity of crystallization is greatly improved, and the electrical uniformity of the switch TFT and the drive TFT is improved, thereby improving the yield of LTPS.
The gate 1102 is disposed on the first insulating layer 1031 and covered by the second insulating layer 1032, the gate 1102 corresponds to the active layer 1101, that is, the gate 1102 is disposed right above the active layer 1101. The material of the gate 1102 includes molybdenum metal.
The source and drain electrode layer 1103 is disposed on the second insulating layer 1032 and is covered by the passivation layer 1034, the source and drain electrode layer 1103 includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer. The source/drain electrode layer 1103 is connected to the active layer 1101 through the first via 1104.
The active layer 1101 of the driving thin film transistor further includes an extension portion 1106, and the extension portion 1106 is disposed between the switching thin film transistor and the driving thin film transistor.
The first electrode 107 is disposed on a side of the planarization layer 104 away from the dielectric layer 103, and is connected to the driving thin film transistor.
The pixel defining layer 106 is disposed on the planarization layer 104 and the first electrode 107, and the pixel defining layer 106 has a slot 1061, and the slot 1061 is recessed downward to the surface of the first electrode 107.
The planarization layer 104 has a second through hole 1041, the second through hole 1041 penetrates through the planarization layer 104 and a portion of the passivation layer 1034 to the surface of the source/drain electrode layer 1103, and the first electrode 107 is connected to the source of the source/drain electrode layer 1103 through the second through hole 1041.
The invention provides an array substrate 100, which is characterized in that a-Si (amorphous silicon) is arranged in a buffer layer corresponding to a channel 1105 of an active layer 1101 and is used as a crystal nucleus 105 of the subsequent active layer 1101 in ELA (excimer laser annealing) crystallization, the a-Si is required to be positioned right below the channel 1105 of the active layer 1101, the width and the length are equal to those of the channel 1105 of the active layer 1101, and the a-Si right below the channel 1105 of the active layer 1101 is used as the crystal nucleus 105 in the crystallization of the channel 1105 of the active layer 1101, so that the channel 1105 of the active layer 1101 can realize the fixed-point crystallization of ELA, the crystal grains are enlarged, the grain boundary is reduced, the uniformity of the ELA crystallization is greatly improved, the electrical uniformity of a switching TFT and a driving TFT is improved, and the yield of LTPS is.
It should be noted that many variations and modifications of the embodiments of the present invention fully described are possible and are not to be considered as limited to the specific examples of the above embodiments. The above examples are given by way of illustration of the invention and are not intended to limit the invention. In conclusion, the scope of the present invention should include those changes or substitutions and modifications which are obvious to those of ordinary skill in the art.
Claims (10)
1. An array substrate, comprising:
a substrate;
the buffer layer is arranged on one side of the substrate;
the dielectric layer is arranged on one side of the buffer layer, which is far away from the substrate, and a switch thin film transistor and a driving thin film transistor which are transversely arranged are arranged in the dielectric layer;
the planarization layer is arranged on one side of the dielectric layer, which is far away from the buffer layer;
and crystal nuclei are arranged on one side of the buffer layer close to the dielectric layer and correspond to channels of the active layers of the switch thin film transistor and the driving thin film transistor.
2. The array substrate of claim 1,
the dielectric layer includes:
the first insulating layer is arranged on one side, far away from the substrate, of the buffer layer;
the second insulating layer is arranged on one side, far away from the buffer layer, of the first insulating layer;
the third insulating layer is arranged on one side, far away from the first insulating layer, of the second insulating layer;
and the passivation layer is arranged on one side of the second insulating layer far away from the first insulating layer.
3. The array substrate of claim 2,
the structures of the switch thin film transistor and the driving thin film transistor comprise:
the active layer is arranged on the buffer layer and is coated by the first insulating layer;
the grid electrode is arranged on the first insulating layer and is coated by the second insulating layer, and the grid electrode corresponds to the active layer;
and the source and drain electrode layer is arranged on the second insulating layer and is coated by the passivation layer, the source and drain electrode layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected with the active layer.
4. The array substrate of claim 3,
the active layer of the driving thin film transistor further comprises an extension part which is arranged between the switch thin film transistor and the driving thin film transistor.
5. The array substrate of claim 1,
the material of the crystal nucleus is amorphous silicon; and/or the presence of a gas in the gas,
the active layer is made of polysilicon.
6. The array substrate of claim 1,
the width of the channel is equal to the width of the crystal nucleus.
7. The array substrate of claim 3,
the second insulating layer is provided with a first through hole, and the first through hole penetrates through the first insulating layer and part of the second insulating layer to reach the surface of the active layer;
the source drain electrode layer is connected with the active layer through the first through hole.
8. The array substrate of claim 3,
the material of the grid electrode comprises metal molybdenum.
9. The array substrate of claim 3, further comprising:
the first electrode is arranged on one side, far away from the dielectric layer, of the planarization layer and is connected with the driving thin film transistor;
the pixel limiting layer is arranged on the planarization layer and the first electrode and is provided with a groove which is sunken downwards to the surface of the first electrode.
10. The array substrate of claim 9,
the planarization layer is provided with a second through hole, the second through hole penetrates through the planarization layer and part of the passivation layer to the surface of the source drain electrode layer, and the first electrode is connected with the source electrode of the source drain electrode layer through the second through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191364.8A CN111370427A (en) | 2020-03-18 | 2020-03-18 | Array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010191364.8A CN111370427A (en) | 2020-03-18 | 2020-03-18 | Array substrate |
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| CN111370427A true CN111370427A (en) | 2020-07-03 |
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| CN202010191364.8A Pending CN111370427A (en) | 2020-03-18 | 2020-03-18 | Array substrate |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501449A (en) * | 2002-11-12 | 2004-06-02 | 友达光电股份有限公司 | Method for making polysilicon layer |
| US20150155390A1 (en) * | 2013-03-11 | 2015-06-04 | Ordos Yuansheng Optoelectronics Co., Ltd. | Manufacturing method of polysilicon layer, and polysilicon thin film transistor and manufacturing method thereof |
| CN105097667A (en) * | 2015-06-24 | 2015-11-25 | 深圳市华星光电技术有限公司 | Fabrication method of low-temperature polycrystalline silicon thin-film transistor (TFT) substrate structure and low-temperature polycrystalline silicon TFT substrate structure |
| CN105938800A (en) * | 2016-07-01 | 2016-09-14 | 深圳市华星光电技术有限公司 | Thin film transistor manufacture method and array substrate manufacture method |
| CN108288621A (en) * | 2018-03-09 | 2018-07-17 | 京东方科技集团股份有限公司 | Manufacturing method, array substrate and the display panel of array substrate |
| CN109817644A (en) * | 2019-01-30 | 2019-05-28 | 武汉华星光电半导体显示技术有限公司 | A kind of tft array substrate and preparation method thereof |
| CN109860109A (en) * | 2019-02-28 | 2019-06-07 | 武汉华星光电半导体显示技术有限公司 | A kind of thin film transistor and its manufacturing method, display panel |
-
2020
- 2020-03-18 CN CN202010191364.8A patent/CN111370427A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501449A (en) * | 2002-11-12 | 2004-06-02 | 友达光电股份有限公司 | Method for making polysilicon layer |
| US20150155390A1 (en) * | 2013-03-11 | 2015-06-04 | Ordos Yuansheng Optoelectronics Co., Ltd. | Manufacturing method of polysilicon layer, and polysilicon thin film transistor and manufacturing method thereof |
| CN105097667A (en) * | 2015-06-24 | 2015-11-25 | 深圳市华星光电技术有限公司 | Fabrication method of low-temperature polycrystalline silicon thin-film transistor (TFT) substrate structure and low-temperature polycrystalline silicon TFT substrate structure |
| US20170162610A1 (en) * | 2015-06-24 | 2017-06-08 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Method for manufacturing ltps tft substrate structure and structure of ltps tft substrate |
| CN105938800A (en) * | 2016-07-01 | 2016-09-14 | 深圳市华星光电技术有限公司 | Thin film transistor manufacture method and array substrate manufacture method |
| CN108288621A (en) * | 2018-03-09 | 2018-07-17 | 京东方科技集团股份有限公司 | Manufacturing method, array substrate and the display panel of array substrate |
| CN109817644A (en) * | 2019-01-30 | 2019-05-28 | 武汉华星光电半导体显示技术有限公司 | A kind of tft array substrate and preparation method thereof |
| CN109860109A (en) * | 2019-02-28 | 2019-06-07 | 武汉华星光电半导体显示技术有限公司 | A kind of thin film transistor and its manufacturing method, display panel |
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