CN111367352B - Circuit for determining source-drain saturation voltage of MOS (Metal oxide semiconductor) tube and operation method thereof - Google Patents

Circuit for determining source-drain saturation voltage of MOS (Metal oxide semiconductor) tube and operation method thereof Download PDF

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CN111367352B
CN111367352B CN202010340052.9A CN202010340052A CN111367352B CN 111367352 B CN111367352 B CN 111367352B CN 202010340052 A CN202010340052 A CN 202010340052A CN 111367352 B CN111367352 B CN 111367352B
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nmos tube
voltage
drain
current
source
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CN111367352A (en
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张俊安
李彦
刘钦晓
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Chongqing University of Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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    • G05F3/262—Current mirrors using field-effect transistors only

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Abstract

The invention discloses a circuit for determining source-drain saturation voltage of an MOS (metal oxide semiconductor) tube and an operation method thereof, wherein the circuit comprises 4 NMOS tubes, 2 operational amplifiers, 2 current mirrors, 1 current subtraction operation unit, 1 voltage subtraction operation unit, 1 current-voltage division operation unit, 1 transconductance-voltage conversion unit, 1 alternative switch, 1 voltage retainer, 1 comparator and 1 successive approximation unit; the 4 NMOS tubes comprise a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, the 2 operational amplifiers comprise a first operational amplifier and a second operational amplifier, and the 2 current mirrors comprise a first current mirror and a second current mirror. The invention also discloses an operation method for determining the source-drain saturation voltage of the MOS tube. The technical scheme of the invention not only ensures that the MOS tube is in a saturated state, but also does not waste the power supply voltage margin.

Description

Circuit for determining source-drain saturation voltage of MOS (Metal oxide semiconductor) tube and operation method thereof
Technical Field
The invention belongs to the technical field of electricity, relates to a circuit for determining source-drain saturation voltage of an MOS (metal oxide semiconductor) tube and an operation method thereof, and particularly relates to a circuit for determining source-drain saturation voltage of an MOS tube based on a successive approximation mode and an operation method thereof.
Background
The source-drain saturation voltage VDSAT of the MOS transistor is a very important parameter characterizing the operating state of the MOS transistor, specifically, the gate-source voltage VGS of the MOS transistor is subtracted by the threshold voltage VTH of the MOS transistor, that is, VDSAT is VGS-VTH. When the drain-source voltage VDS of the MOS tube is more than or equal to the source-drain saturation voltage, the MOS tube works in a saturation region, namely the MOS tube is in the saturation region when the VDS is more than or equal to VDSAT; conversely, the MOS transistor is in the linear region when VDS < VDSAT. The output impedance ro of the MOS tube in the saturation region is larger, and the transconductance gm is larger. In an analog CMOS integrated circuit, when an MOS tube realizes an amplification function or an active load function, the MOS tube is required to be in a saturation region, and if the MOS tube falls into a linear region, transconductance and output impedance of the MOS tube are reduced, so that performance parameters of the whole circuit are influenced.
The current method is more common to obtain the variation range (not the precise value) of the source-drain saturation voltage VDSAT by performing combined simulation of various temperature and process deviations on the MOS transistor. Then the drain-source voltage VDS of the MOS tube is set to be slightly larger than the upper limit value of the variation range of the VDSAT, so that the MOS tube is in a saturation region.
The prior art has the following disadvantages: if the MOS transistor model is inaccurate and the simulation condition is insufficient, the variation range of the obtained source-drain saturation voltage VDSAT is inaccurate, and if the source-drain voltage VDS is set based on the variation range, the MOS transistor may fall into a linear region under certain conditions, so that the circuit performance is influenced. Since the drain-source voltage VDS is set to be slightly larger than the upper limit of the variation range of VDSAT, but VDS does not need to be set to be as large as the upper limit in most cases, the power supply voltage margin is wasted, and the dynamic range of the signal is reduced.
Two difficulties exist in accurately determining the source-drain saturation voltage VDSAT of the MOS transistor on a chip. Firstly, the source, gate and drain voltages of the MOS transistor are the voltages actually applied to each end of the MOS transistor, so the values of VDS and VGS can be directly obtained. However, the threshold voltage VTH of the MOS transistor is a process parameter, which needs to be measured by a special semiconductor parameter tester and cannot be directly obtained. Therefore, it is difficult to directly determine the value of the MOS transistor source-drain saturation voltage VDSAT on the chip. Secondly, even if the threshold voltage VTH is measured by a semiconductor parameter tester in advance, when the environmental temperature and the power supply voltage of the whole chip are changed, the value of the threshold voltage VTH of the MOS transistor is also changed, so that the value of the source-drain saturation voltage VDSAT of the MOS transistor is also changed. Therefore, how to accurately determine the source-drain saturation voltage VDSAT of the MOS transistor on the chip, and further adjust the drain-source voltage VDS of the MOS transistor, so that the MOS transistor is always in a saturation region, which is a difficult technical problem for circuit designers.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a circuit for determining the source-drain saturation voltage of an MOS (metal oxide semiconductor) tube.
The technical scheme is as follows:
a circuit for determining source-drain saturation voltage of an MOS (metal oxide semiconductor) tube comprises 4 NMOS (N-channel metal oxide semiconductor) tubes, 2 operational amplifiers, 2 current mirrors, 1 current subtraction operation unit, 1 voltage subtraction operation unit, 1 current-voltage division operation unit, 1 transconductance-voltage conversion unit, 1 two-way switch, 1 voltage retainer, 1 comparator and 1 successive approximation unit; the 4 NMOS transistors comprise a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, the 2 operational amplifiers comprise a first operational amplifier and a second operational amplifier, and the 2 current mirrors comprise a first current mirror and a second current mirror;
wherein:
the source electrode of the first NMOS tube is connected with the VSS end, the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the negative input end of the first operational amplifier.
The source electrode of the second NMOS tube is connected with the VSS end, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube and the negative input end of the second operational amplifier.
The source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube and the negative input end of the first operational amplifier, the grid electrode of the third NMOS tube is connected with the output end of the first operational amplifier, and the drain electrode of the third NMOS tube is connected with the input end of the first current mirror.
The source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube and the negative input end of the second operational amplifier, the grid electrode of the fourth NMOS tube is connected with the output end of the second operational amplifier, and the drain electrode of the fourth NMOS tube is connected with the input end of the second current mirror.
The positive input end of the first operational amplifier is connected with the a end of the voltage subtraction operation unit and the vc1 end of the successive approximation unit, the negative input end is connected with the drain electrode of the first NMOS tube and the source electrode of the third NMOS tube, and the output end is connected with the grid electrode of the third NMOS tube. The first operational amplifier, the third NMOS tube and the first NMOS tube form a feedback structure.
The positive input end of the second operational amplifier is connected with the b end of the voltage subtraction operation unit and the vc2 end of the successive approximation unit, the negative input end is connected with the drain electrode of the second NMOS tube and the source electrode of the fourth NMOS tube, and the output end is connected with the grid electrode of the fourth NMOS tube. The second operational amplifier, the fourth NMOS tube and the second NMOS tube form a feedback structure.
The current input end of the first current mirror is connected with the drain electrode of the third NMOS tube, the image output end of the first current mirror is connected with the a end of the current subtraction operation unit, and the power supply end of the first current mirror is connected with the power supply VDD.
The current input end of the second current mirror is connected with the drain electrode of the fourth NMOS tube, the mirror image output end is connected with the end b of the current subtraction operation unit, and the power supply end is connected with a power supply VDD.
And the output end of the current subtraction operation unit is connected with the end a of the current-voltage division operation unit. The current subtraction operation unit realizes the function of y-a-b.
The a end of the voltage subtraction operation unit is connected with the positive input end of the first operational amplifier and the vc1 end of the successive approximation unit, the b end is connected with the positive input end of the second operational amplifier and the vc2 end of the successive approximation unit, and the output end is connected with the b end of the current-voltage division operation unit. The voltage subtraction operation unit realizes the function of y-a-b.
The output end of the transconductance-voltage conversion unit is connected with the input end of the current-voltage division operation unit. The current-voltage division operation unit realizes the function of y being a/b.
The input end of the transconductance-voltage conversion unit is connected with the output end of the current-voltage division operation unit, and the output end of the transconductance-voltage conversion unit is connected with the in end of the alternative switch. The transconductance-voltage conversion unit realizes the conversion function of transconductance and voltage, because the subsequent comparator and the voltage keeper can only process voltage signals.
The in end of the alternative switch is connected with the out end of the transconductance-voltage conversion unit, the o1 end is connected with the positive input end of the comparator and the input end of the voltage retainer, the o2 end is connected with the negative input end of the comparator, and the c end is connected with the vctl end of the successive approximation unit. The alternative switch is used for selecting in and o1 or in and o2 to be communicated based on the input voltage signal at the c terminal.
The input end of the voltage keeper is connected with the o1 end of the one-out switch and the positive input end of the comparator. The voltage keeper realizes that the voltage of the input end is always kept.
The positive input end of the comparator is connected with the o1 end of the one-out switch and the input end of the voltage keeper, the negative input end of the comparator is connected with the o2 end of the one-out switch, and the output end of the comparator is connected with the cmp end of the successive approximation unit. The comparator compares the voltages of the positive input end and the negative input end, and the output end outputs a comparison result.
The vc1 of the successive approximation unit is connected with the positive input end of the first operational amplifier and the a end of the voltage subtraction unit, the vc2 is connected with the positive input end of the second operational amplifier and the b end of the voltage subtraction unit, the vctl is connected with the c end of the alternative switch, the cmp is connected with the output end of the comparator, and the vout end outputs the final value of the source-drain saturation voltage VDSAT. The successive approximation unit realizes the function of determining the source-drain saturation voltage of the MOS tube by using a successive approximation method.
Furthermore, the sizes of the first NMOS tube and the second NMOS tube are identical, and the sizes of the third NMOS tube and the fourth NMOS tube are identical.
An operation method for determining source-drain saturation voltage of a MOS transistor comprises the following steps:
step 1, under the condition that the gate-source voltages of the first NMOS tube and the second NMOS tube are the same, the successive approximation unit sets the drain-source voltage of the second NMOS tube to a lower voltage value (to ensure that the drain-source voltage is lower than the source-drain saturation voltage in any case) through a feedback loop formed by the second operational amplifier and the fourth NMOS tube, and sets the drain-source voltage of the first NMOS tube to a higher voltage value (to ensure that the drain-source voltage is higher than the source-drain saturation voltage in any case) through a feedback loop formed by the first operational amplifier and the third NMOS tube. And then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit. The difference value of the drain-source voltages of the first NMOS tube and the second NMOS tube is obtained through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction operation unit. And then obtaining a quotient value of the difference value of the drain current and the difference value of the drain-source voltage through a current-voltage division operation unit (the quotient value is a transconductance in a dimension). And then the transconductance is converted into voltage through a transconductance voltage conversion unit. The one-out switch o1 is then connected in to save the voltage value to the voltage keeper.
Step 2, connecting an alternative switch o2 to in; the successive approximation unit increases the drain-source voltage of the second NMOS tube by a change step value through a feedback loop formed by the second operational amplifier and the fourth NMOS tube; then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit; obtaining a difference value of drain-source voltages of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction unit; then, a quotient value of the difference value of the drain current and the difference value of the drain-source voltage is obtained through a current-voltage division operation unit; then, the transconductance is converted into voltage through a transconductance voltage conversion unit, and the voltage is in direct proportion to the slope of an ID-VDS curve, namely the transconductance; the voltage value is smaller than the voltage value in the voltage retainer, the voltage is in direct proportion to the initial slope of the ID-VDS curve, namely the initial transconductance, and the comparator is turned over;
step 3, the successive approximation unit gradually reduces the drain-source voltage of the first NMOS tube through a feedback loop formed by the first operational amplifier and the third NMOS tube; then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit; obtaining a difference value of drain-source voltages of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction unit; then, a quotient value of the difference value of the drain current and the difference value of the drain-source voltage is obtained through a current-voltage division operation unit; then the transconductance is converted into voltage through a transconductance voltage conversion unit; the voltage value is also gradually increased until the voltage value exceeds the voltage value in the voltage retainer, and the comparator is turned over again;
and N, continuously and repeatedly executing the step 2 and the step 3 until the source-drain voltage of the first NMOS tube and the source-drain voltage of the second NMOS tube are close enough (the difference value between the source-drain voltage of the first NMOS tube and the source-drain voltage of the second NMOS tube is smaller than a certain preset value) when the third step of operation is executed, stopping the approximation operation, and enabling the successive approximation unit to output the arithmetic mean value of the source-drain voltage of the first NMOS tube and the source-drain voltage of the second NMOS tube, wherein the obtained arithmetic mean voltage value is the saturation voltage of the first NMOS tube and the second NMOS tube.
The invention has the beneficial effects that:
the method determines the source-drain saturation voltage VDSAT of the MOS tube in a successive approximation mode by utilizing the characteristic of the V-I output curve of the MOS tube without acquiring the value of the threshold voltage VTH in advance. The invention directly utilizes the characteristics of the V-I output curve of the MOS tube, does not require that the V-I characteristic strictly meets the Subtincg equation, and is also suitable for the short-channel MOS tube. When the environmental temperature and the power supply voltage of the whole chip change, the source-drain saturation voltage VDSAT of the MOS tube in a new state can be determined again only by running the successive approximation process again. Because the source-drain saturation voltage VDSAT of the MOS tube is accurately obtained, the source-drain saturation voltage VDSA can be set to be slightly higher than the source-drain saturation voltage VDSAT, so that the MOS tube is ensured to be in a saturation state and the power supply voltage margin is not wasted.
Drawings
FIG. 1 is a general functional block diagram of a circuit for determining source-drain saturation voltage of a MOS transistor according to the present invention;
fig. 2 is a schematic flow chart of the operating method for determining the source-drain saturation voltage of the MOS transistor according to the present invention.
Detailed Description
The technical solutions of the present invention will be described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, a circuit for determining a source-drain saturation voltage of an MOS transistor includes 4 NMOS transistors, 2 operational amplifiers (operational amplifiers for short), 2 current mirrors, 1 current subtraction operation unit, 1 voltage subtraction operation unit, 1 current-voltage division operation unit, 1 transconductance-voltage conversion unit, 1 alternative switch, 1 voltage keeper, 1 comparator, and 1 successive approximation unit.
Wherein:
the source electrode of the first NMOS tube (NM1) is connected with the VSS end, the grid electrode of the first NMOS tube (NM1) is connected with the grid electrode of the second NMOS tube (NM2), and the drain electrode of the first NMOS tube (NM3) is connected with the source electrode of the third NMOS tube and the negative input end of the first operational amplifier (operational amplifier 1). The drain voltage of NM1 is labeled VDS 1' in fig. 1, and the gate voltage of NM1 is labeled VGS in fig. 1. NM1 and NM2 are the same size.
The source of NM2 is connected to VSS, the gate is connected to the gate of NM1, and the drain is connected to the source of the fourth NMOS transistor (NM4) and the negative input terminal of the second operational amplifier (operational amplifier 2). The drain voltage of NM2 is labeled VDS 2' in fig. 1, and the gate voltage of NM2 is labeled VGS in fig. 1.
The source of NM3 is connected to the drain of NM1 and the negative input terminal of operational amplifier 1, the gate is connected to the output terminal of operational amplifier 1, and the drain is connected to the input terminal (in terminal) of the first current mirror (current mirror 1). The drain currents of NM1 and NM3 are labeled ID 1' in fig. 1. NM3 and NM4 are the same size.
The source of NM4 is connected to the drain of NM2 and the negative input terminal of op-amp 2, the gate is connected to the output terminal of op-amp 2, and the drain is connected to the input terminal (in terminal) of the second current mirror (current mirror 2). The drain currents of NM2 and NM4 are labeled ID 2' in fig. 1.
The positive input end of the operational amplifier 1 is connected with the a end of the voltage subtraction operation unit and the vc1 end of the successive approximation unit, the negative input end is connected with the drain of the NM1 and the source of the NM3, and the output end is connected with the gate of the NM 3. The positive input voltage of the operational amplifier 1 is labeled VDS1 in fig. 1. The negative input voltage of the op-amp 1 is labeled VDS 1' in fig. 1. The operational amplifier 1 and NM3, NM1 form a feedback structure, so that VDS1 ≈ VDS 1'. The operational amplifier 1 is implemented using a conventional CMOS circuit.
The operational amplifier 2 has a positive input connected to the b terminal of the voltage subtraction unit and the vc2 terminal of the successive approximation unit, a negative input connected to the drain of the NM2 and the source of the NM4, and an output connected to the gate of the NM 4. The positive input voltage of the operational amplifier 2 is labeled VDS2 in fig. 1. The negative input voltage of the op-amp 2 is labeled VDS 2' in fig. 1. The operational amplifier 2 and NM4, NM2 form a feedback structure, so that VDS2 ≈ VDS 2'. The operational amplifier 2 is implemented using conventional CMOS circuitry.
The current input end (in end) of the current mirror 1 is connected with the drain electrode of the NM3, the mirror output end (mir end) is connected with the a end of the current subtraction operation unit, and the power supply end is connected with the power supply VDD. The mirror output current of the current mirror 1 is labeled ID1 in fig. 1. The current mirror 1 completes mirroring the input current such that ID1 ≈ ID 1'. The current mirror 1 is implemented using conventional CMOS circuitry.
The current input end (in end) of the current mirror 2 is connected with the drain electrode of the NM4, the mirror output end (mir end) is connected with the b end of the current subtraction arithmetic unit, and the power supply end is connected with the power supply VDD. The mirror output current of the current mirror 2 is labeled ID2 in fig. 1. The current mirror 2 completes mirroring the input current such that ID2 ≈ ID 2'. The current mirror 2 is implemented using conventional CMOS circuitry.
The a end of the current subtraction operation unit is connected with the mirror image output end (mir end) of the current mirror 1, the b end of the current subtraction operation unit is connected with the mirror image output end (mir end) of the current mirror 2, and the output end (y end) of the current subtraction operation unit is connected with the a end of the current-voltage division operation unit. The current subtraction unit realizes the function of y being a-b, namely, the output end (y end) outputs the difference current of the a end and the b end: Δ ID is ID1-ID 2. The current subtraction operation unit is realized by a conventional CMOS circuit.
The a end of the voltage subtraction operation unit is connected with the positive input end of the operational amplifier 1 and the vc1 end of the successive approximation unit, the b end is connected with the positive input end of the operational amplifier 2 and the vc2 end of the successive approximation unit, and the output end (y end) is connected with the b end of the current-voltage division operation unit. The voltage subtraction operation unit realizes the function that y is a-b, namely, the output end (y end) outputs the difference voltage of the a end and the b end: Δ VDS1-VDS 2. The voltage subtraction operation unit is realized by a conventional CMOS circuit.
The output end (y end) is connected with the input end (in end) of the transconductance-voltage conversion unit. The current-voltage division operation unit realizes the function of y ═ a/b, that is, the output end (y end) outputs the value of the division between the a end and the b end (the dimension is transconductance): g is delta ID/delta VDS. The current-voltage division operation unit is realized by a conventional CMOS circuit.
The input end (in end) of the transconductance-voltage conversion unit is connected with the output end (y end) of the current-voltage division operation unit, and the output end (out end) is connected with the in end of the alternative switch. The transconductance-voltage conversion unit realizes the conversion function of transconductance and voltage, because the subsequent comparator and the voltage keeper can only process voltage signals. That is, the in-end transconductance of the output end (y-end) is converted into a voltage value (dimension is voltage): k (Δ ID/Δ VDS). The current-voltage division operation unit is realized by a conventional CMOS circuit.
The in end of the alternative switch is connected with the out end of the transconductance-voltage conversion unit, the o1 end is connected with the positive input end of the comparator and the input end of the voltage retainer, the o2 end is connected with the negative input end of the comparator, and the c end is connected with the vctl end of the successive approximation unit. The function of the alternative switch is to select in and o1 or in and o2 to be connected based on the input voltage signal at the c terminal. The alternative switch is implemented using conventional CMOS circuitry.
The input end of the voltage keeper is connected with the o1 end of the one-out switch and the positive input end of the comparator. The voltage keeper keeps the voltage of the input end all the time (even if the input signal is disconnected, the original value is still kept). The voltage keeper is implemented using conventional CMOS circuitry.
The positive input end of the comparator is connected with the o1 end of the one-out switch and the input end of the voltage keeper, the negative input end of the comparator is connected with the o2 end of the one-out switch, and the output end of the comparator is connected with the cmp end of the successive approximation unit. The comparator compares the voltages of the positive input end and the negative input end, and the output end outputs a comparison result. The comparator is implemented using conventional CMOS circuitry.
The vc1 end of the successive approximation unit is connected with the positive input end of the operational amplifier 1 and the a end of the voltage subtraction operation unit, the vc2 end of the operational amplifier 2 and the b end of the voltage subtraction operation unit, the vctl end is connected with the c end of the alternative switch, the cmp end is connected with the output end of the comparator, and the vout end outputs the final value of the source-drain saturation voltage VDSAT. The successive approximation unit realizes the function of determining the source-drain saturation voltage of the MOS tube by using a successive approximation method. The successive approximation unit is implemented using conventional CMOS circuitry.
Operation flow of successive approximation
The size of NM1 and NM2 are identical, so the I-V output curves of the two NMOS transistors should be identical. Also, the gate-source voltages of NM1 and NM2 are equal (both equal to VGS in fig. 1), so the drain voltages VDS1 '(≈ VDS1), VDS 2' (≈ VDS2), and ID1 '(≈ ID1), ID 2' (≈ ID2) determine the positions of NM1 and NM2 on the I-V output curve (as shown in fig. 2). In fig. 1, a signal path composed of the current mirror 1, the current mirror 2, the current subtraction unit, the voltage subtraction unit, and the current-voltage division unit can complete the operation of G ═ Δ ID/Δ VDS ═ ID1-ID2)/(VDS1-VDS2), that is, the operation of the slope (dimension is transconductance) between two points on the I-V output curve of the NMOS transistor. The transconductance-voltage conversion unit realizes the conversion function of transconductance and voltage, because the subsequent comparator and the voltage keeper can only process voltage signals. The voltage keeper realizes that the voltage of the input end is always kept (even if the input signal is disconnected, the current value is still)
As shown in fig. 2, the first step operation (initial operation):
the successive approximation unit brings the initial value of the output voltage VDS1 at the terminal vc1 to a value (e.g., VDD/2) much higher than the VDSAT range, and brings the initial value of the output voltage VDS2 at the terminal vc2 to a value (e.g., 30mV) much lower than the VDSAT range. Due to the feedback effect of the operational amplifiers 1 and 2, the drain-source voltages VDS1 '≈ VDS1 and VDS 2' ≈ VDS2 of NM1 and NM2, and thus the state of NM1 is at the position of the circle at the upper right corner in the first step I-V curve of fig. 2, the abscissa of the point is equal to VDS1 '(≈ VDS1), and the ordinate is equal to ID 1' (≈ ID 1); also the state of NM2 is in the lower left-hand circle position in the first step I-V curve of FIG. 2, with the abscissa equal to VDS2 '(≈ VDS2) and the ordinate equal to ID 2' (≈ ID 2). Therefore, the slope between two points in the initial state can be obtained by a circuit formed by the current mirror 1, the current mirror 2, the current subtraction unit, the voltage subtraction unit and the current-voltage division unit in fig. 1, and the initial slope is converted into a voltage signal by the transconductance-voltage conversion unit. The successive approximation unit enables the in end of the alternative switch and the o1 end to be communicated through a control signal output by the vctl end, and enables the voltage value converted by the slope to be kept on the voltage keeper.
And a second step of operation:
the successive approximation unit enables the in terminal of the alternative switch to be communicated with the o2 terminal through the control signal output by the vctl terminal, and then enables the output voltage VDS2 of the vc2 terminal to be increased by a preset micro-step (such as 10mV), so that the VDS1 keeps the current value unchanged. As shown in the second step of fig. 2, the state of NM2 becomes the position of the circle at the lower left corner of the figure, and the position of NM1 does not change, so the slope becomes small, and the comparator outputs state 0.
The third step of operation:
the successive approximation unit first determines whether VDS1 and VDS2 are close enough (i.e. whether the difference between the two is smaller than a certain preset value, such as 10mV), if not (indicating that VDS1 and VDS2 are not close to VDSAT), the successive approximation unit control voltage VDS1 decreases by a certain preset step size (such as 10mV), the decrease of VDS1 will cause the slope between the two points in the third step of fig. 2 to increase, then the successive approximation unit monitors whether the comparator output is turned to 1, and if not, the third step is repeatedly executed. Gradually reducing VDS1 until the slope between the two points in the third step of fig. 2 is just greater than the initial slope, the comparator output state is inverted to 1, and the first approximation operation is completed. And then turns to perform the second step operation.
Operation in the Nth step:
as shown in the nth step in fig. 2, the second and third steps are repeatedly performed several times until VDS1 and VDS2 are found to be close enough (the difference between the two is already smaller than a certain preset value) when the third step is performed, the approximation operation is stopped, and the successive approximation unit outputs VDSAT ═ VDS1+ VDS 2)/2. The resulting VDSAT is the source-drain saturation voltage value of NM1 and NM 2.
The invention can be manufactured by adopting a CMOS process and a BiCMOS process.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and any simple modifications or equivalent substitutions of the technical solutions that can be obviously obtained by those skilled in the art within the technical scope of the present invention are within the scope of the present invention.

Claims (3)

1. A circuit for determining source-drain saturation voltage of a MOS transistor is characterized in that: the device comprises 4 NMOS tubes, 2 operational amplifiers, 2 current mirrors, 1 current subtraction operation unit, 1 voltage subtraction operation unit, 1 current-voltage division operation unit, 1 transconductance-voltage conversion unit, 1 two-way switch, 1 voltage retainer, 1 comparator and 1 successive approximation unit; the 4 NMOS transistors comprise a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, the 2 operational amplifiers comprise a first operational amplifier and a second operational amplifier, and the 2 current mirrors comprise a first current mirror and a second current mirror;
wherein:
the source electrode of the first NMOS tube is connected with the VSS end, the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the negative input end of the first operational amplifier;
the source electrode of the second NMOS tube is connected with the VSS end, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube and the negative input end of the second operational amplifier;
the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube and the negative input end of the first operational amplifier, the grid electrode of the third NMOS tube is connected with the output end of the first operational amplifier, and the drain electrode of the third NMOS tube is connected with the input end of the first current mirror;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube and the negative input end of the second operational amplifier, the grid electrode of the fourth NMOS tube is connected with the output end of the second operational amplifier, and the drain electrode of the fourth NMOS tube is connected with the input end of the second current mirror;
the positive input end of the first operational amplifier is connected with the a end of the voltage subtraction operation unit and the vc1 end of the successive approximation unit, the negative input end of the first operational amplifier is connected with the drain electrode of the first NMOS tube and the source electrode of the third NMOS tube, and the output end of the first operational amplifier is connected with the grid electrode of the third NMOS tube; the first operational amplifier, the third NMOS tube and the first NMOS tube form a feedback structure;
the positive input end of the second operational amplifier is connected with the b end of the voltage subtraction operation unit and the vc2 end of the successive approximation unit, the negative input end of the second operational amplifier is connected with the drain electrode of the second NMOS tube and the source electrode of the fourth NMOS tube, and the output end of the second operational amplifier is connected with the grid electrode of the fourth NMOS tube; the second operational amplifier, the fourth NMOS tube and the second NMOS tube form a feedback structure;
the current input end of the first current mirror is connected with the drain electrode of the third NMOS tube, the image output end is connected with the a end of the current subtraction operation unit, and the power supply end is connected with a power supply VDD;
the current input end of the second current mirror is connected with the drain electrode of the fourth NMOS tube, the mirror image output end is connected with the end b of the current subtraction operation unit, and the power supply end is connected with a power supply VDD;
the a end of the current subtraction operation unit is connected with the mirror image output end of the first current mirror, the b end of the current subtraction operation unit is connected with the mirror image output end of the second current mirror, and the output end of the current subtraction operation unit is connected with the a end of the current-voltage division operation unit; the current subtraction operation unit realizes the function of y-a-b;
the a end of the voltage subtraction operation unit is connected with the positive input end of the first operational amplifier and the vc1 end of the successive approximation unit, the b end of the voltage subtraction operation unit is connected with the positive input end of the second operational amplifier and the vc2 end of the successive approximation unit, and the output end of the voltage subtraction operation unit is connected with the b end of the current-voltage division operation unit; the voltage subtraction operation unit realizes the function of y-a-b;
the output end of the transconductance-voltage conversion unit is connected with the input end of the current-voltage division operation unit; the current-voltage division operation unit realizes the function of y being a/b;
the input end of the transconductance-voltage conversion unit is connected with the output end of the current-voltage division operation unit, and the output end of the transconductance-voltage conversion unit is connected with the in end of the alternative switch; the transconductance-voltage conversion unit realizes the conversion function of transconductance and voltage, and the subsequent comparator and the voltage keeper can only process voltage signals;
the in end of the alternative switch is connected with the out end of the transconductance-voltage conversion unit, the o1 end is connected with the positive input end of the comparator and the input end of the voltage retainer, the o2 end is connected with the negative input end of the comparator, and the c end is connected with the vctl end of the successive approximation unit; the alternative switch is used for selecting in and o1 or in and o2 to be communicated based on the input voltage signal at the c terminal;
the input end of the voltage keeper is connected with the o1 end of the one-of-two switch and the positive input end of the comparator; the voltage keeper realizes that the voltage of the input end is always kept;
the positive input end of the comparator is connected with the o1 end of the one-out-of-two switch and the input end of the voltage keeper, the negative input end of the comparator is connected with the o2 end of the one-out-of-two switch, and the output end of the comparator is connected with the cmp end of the successive approximation unit; the comparator compares the voltages of the positive input end and the negative input end, and the output end outputs a comparison result;
the vc1 end of the successive approximation unit is connected with the positive input end of the first operational amplifier and the a end of the voltage subtraction operation unit, the vc2 end is connected with the positive input end of the second operational amplifier and the b end of the voltage subtraction operation unit, the vctl end is connected with the c end of the alternative switch, the cmp end is connected with the output end of the comparator, and the vout end outputs the final value of the source-drain saturation voltage VDSAT; the successive approximation unit realizes the function of determining the source-drain saturation voltage of the MOS tube by using a successive approximation method.
2. The circuit for determining the source-drain saturation voltage of a MOS transistor according to claim 1, wherein: the sizes of the first NMOS tube and the second NMOS tube are the same, and the sizes of the third NMOS tube and the fourth NMOS tube are the same.
3. An operation method for determining source-drain saturation voltage of a MOS transistor is characterized in that: the method comprises the following steps:
step 1, under the condition that the grid-source voltages of a first NMOS tube and a second NMOS tube are the same, a successive approximation unit sets the drain-source voltage of the second NMOS tube to a lower voltage value through a feedback loop formed by a second operational amplifier and a fourth NMOS tube, and the successive approximation unit sets the drain-source voltage of the first NMOS tube to a higher voltage value through the feedback loop formed by the first operational amplifier and a third NMOS tube; then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit; obtaining a difference value of drain-source voltages of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction unit; then, a quotient value of the difference value of the drain current and the difference value of the drain-source voltage is obtained through a current-voltage division operation unit; then the transconductance is converted into voltage through a transconductance voltage conversion unit; then the alternative switch o1 is connected in to store the voltage value in the voltage keeper;
step 2, connecting an alternative switch o2 to in; the successive approximation unit increases the drain-source voltage of the second NMOS tube by a change step value through a feedback loop formed by the second operational amplifier and the fourth NMOS tube; then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit; obtaining a difference value of drain-source voltages of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction unit; then, a quotient value of the difference value of the drain current and the difference value of the drain-source voltage is obtained through a current-voltage division operation unit; then, the transconductance is converted into voltage through a transconductance voltage conversion unit, and the voltage is in direct proportion to the slope of an ID-VDS curve, namely the transconductance; the voltage value is smaller than the voltage value in the voltage retainer, the voltage is in direct proportion to the initial slope of the ID-VDS curve, namely the initial transconductance, and the comparator is turned over;
step 3, the successive approximation unit gradually reduces the drain-source voltage of the first NMOS tube through a feedback loop formed by the first operational amplifier and the third NMOS tube; then obtaining the difference value of the drain currents of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the current subtraction unit; obtaining a difference value of drain-source voltages of the first NMOS tube and the second NMOS tube through a circuit formed by the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first current mirror, the second current mirror and the voltage subtraction unit; then, a quotient value of the difference value of the drain current and the difference value of the drain-source voltage is obtained through a current-voltage division operation unit; then the transconductance is converted into voltage through a transconductance voltage conversion unit; the voltage value is also gradually increased until the voltage value exceeds the voltage value in the voltage retainer, and the comparator is turned over again;
and continuously repeating the step 2 and the step 3 until the source-drain voltage of the first NMOS tube and the source-drain voltage of the second NMOS tube are close enough when the third step is executed, stopping the approximation operation, and enabling the successive approximation unit to output the arithmetic mean value of the source-drain voltage of the first NMOS tube and the source-drain voltage of the second NMOS tube, wherein the obtained arithmetic mean voltage value is the saturation voltage of the first NMOS tube and the second NMOS tube.
CN202010340052.9A 2020-04-26 2020-04-26 Circuit for determining source-drain saturation voltage of MOS (Metal oxide semiconductor) tube and operation method thereof Expired - Fee Related CN111367352B (en)

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CN103094144B (en) * 2011-10-31 2015-11-25 无锡华润上华科技有限公司 A kind of method of the threshold voltage for estimating metal-oxide-semiconductor
TWI425236B (en) * 2012-05-11 2014-02-01 Univ Nat Chiao Tung Threshold voltage measurement device
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