CN111354681A - Transistor structure and forming method thereof - Google Patents

Transistor structure and forming method thereof Download PDF

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Publication number
CN111354681A
CN111354681A CN201811587509.5A CN201811587509A CN111354681A CN 111354681 A CN111354681 A CN 111354681A CN 201811587509 A CN201811587509 A CN 201811587509A CN 111354681 A CN111354681 A CN 111354681A
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groove
layer
substrate
forming
transistor
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CN111354681B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a transistor structure and a forming method thereof, wherein the forming method of the transistor structure comprises the following steps: providing a substrate comprising a first region and a second region; etching the base of the first region to form a first substrate and a plurality of first fin parts which are separated from the first substrate, wherein a first groove is formed between every two adjacent first fin parts; etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove; doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor; and after ions are doped, forming an isolation layer in the first groove and the second groove. Ions are doped on the bottom surface of the second groove, so that the threshold voltage of the parasitic device is improved, and the parasitic device is not easy to open when the device works.

Description

Transistor structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a transistor structure and a forming method thereof.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to reduce the impact of short channel effects, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a transistor structure and a method for forming the same to optimize electrical properties of the transistor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a transistor structure, including: providing a substrate comprising a first region and a second region; etching the base of the first region to form a first substrate and a plurality of first fin parts which are separated from the first substrate, wherein a first groove is formed between every two adjacent first fin parts; etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove; doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor; and after ions are doped, forming an isolation layer in the first groove and the second groove.
Optionally, the step of doping ions on the bottom surface of the second groove includes: and doping ions on the bottom surface of the second groove by adopting an ion implantation mode.
Optionally, the transistor is a PMOS transistor, and the doped ions include phosphorus, arsenic, or antimony; or, the transistor is an NMOS transistor, and the doped ions include boron, gallium, or indium.
Optionally, the process parameters of the doped ions include: the implantation dose is 1.0E13 atoms per square centimeter to 2.0E14 atoms per square centimeter, the implantation energy is 15KeV to 60KeV, and the angle between the ion implantation direction and the normal is 0 degree to 15 degrees.
Optionally, the step of forming the isolation layer in the first groove and the second groove includes: forming a first isolation layer in the first groove; and forming a second isolating layer in the second groove, wherein the density of the second isolating layer is higher than that of the first isolating layer.
Optionally, the first isolation layer is made of silicon oxide, and the second isolation layer is made of silicon nitride.
Optionally, the second groove is formed first, and then the first groove is formed; or, the first groove is formed first, and then the second groove is formed.
Optionally, the step of forming the second groove includes: forming a masking material layer overlying the substrate, forming a plurality of discrete core layers on the masking material layer; forming a mask side wall covering the side wall of the core layer; forming a mask protective layer on the exposed mask material layer of the core layer and the exposed mask side wall; forming a shielding layer exposing the second region on the mask side wall; etching the substrate by taking the shielding layer as a mask to form a second groove; after the second groove is formed, removing the shielding layer, the core layer and the mask protective layer;
the step of forming the first groove includes: forming a groove protection layer in the second groove; etching the substrate of the first region by taking the mask side wall as a mask to form the first groove; the forming method of the transistor structure comprises the following steps: and removing the groove protection layer after the first groove is formed.
Optionally, the groove protection layer is made of a bottom anti-reflection coating, silicon oxide, silicon nitride, or silicon oxynitride.
Optionally, the depth of the second groove is 600 to 900 angstroms.
Optionally, the depth of the first groove is 1000 to 1500 angstroms.
Optionally, a gate structure is formed to cross the first fin portion and the second fin portion, and the gate structure includes a work function layer.
Correspondingly, an embodiment of the present invention further provides a transistor structure, including: a substrate comprising a second region and a first region; the first region comprises a first substrate and a plurality of first fin parts separated from the first substrate, and a first groove is formed between every two adjacent first fin parts; the second region comprises a second substrate and a plurality of second fin parts separated from the second substrate, a second groove is formed between every two adjacent second fin parts, and the depth of the second groove is smaller than that of the first groove; the doped ions are positioned on the bottom surface of the second groove, and the type of the doped ions is opposite to that of the transistor; and the isolation layer is positioned in the second groove and the first groove.
Optionally, the depth of the second groove is 600 to 900 angstroms.
Optionally, the depth of the first groove is 1000 to 1500 angstroms.
Optionally, the transistor is a PMOS transistor, and the ions doped on the bottom surface of the second groove include phosphorus, arsenic, or antimony.
Optionally, the transistor is an NMOS transistor, and the ions doped on the bottom surface of the second groove include boron, gallium, or indium.
Optionally, the thickness of the isolation layer in the second groove is 25 nm to 50 nm.
Optionally, the isolation layer in the first groove is a first isolation layer, the isolation layer in the second groove is a second isolation layer, and the density of the second isolation layer is higher than that of the first isolation layer.
Optionally, the first isolation layer is made of silicon oxide, and the second isolation layer is made of silicon nitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the base of the first area is etched to form a first substrate and a plurality of first grooves which are separated from the first substrate; etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove; doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor; and after ions are doped, forming an isolation layer in the first groove and the second groove. The transistor structure also typically includes a gate structure formed in the first recess and the second recess, the gate structure including a work function layer. The material of the first substrate and the second substrate is usually a semiconductor, the material of the isolation layer is usually a dielectric material, the material of the work function layer is usually a metal material, so the first substrate, the isolation layer and the work function layer constitute a parasitic device, but the parasitic device constituted by the first substrate, the isolation layer and the work function layer is difficult to turn on because the isolation layer on the first substrate is thick, the second substrate, the isolation layer and the work function layer constitute a parasitic device, because the isolation layer on the second substrate is thin, so the parasitic device constituted by the second substrate, the isolation layer and the work function layer is easy to turn on, and the doped ions are doped on the bottom surface of the second groove, namely in the second substrate, so that the fermi level of the parasitic device tends to change towards the top of the valence band or tends to change towards the conduction band bottom, the Fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is improved, the parasitic device at the bottom of the second groove is not easy to turn on, and the electrical performance of the transistor is optimized.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a transistor structure;
fig. 4 to fig. 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a transistor structure according to the embodiment of the invention.
Detailed Description
The reason why the electrical performance of the transistor is to be improved is analyzed in conjunction with a method for forming a transistor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a transistor structure are shown.
As shown in fig. 1, a substrate 1 is provided, the substrate 1 comprising a first region I and a second region II, a first recess 6 being formed in the first region I; forming fin parts 4 and second grooves 7 located between adjacent fin parts 4 in the second region II; the depth of the second groove 7 is smaller than the depth of the first groove 6.
As shown in fig. 2, a dummy gate structure 8 is formed to cross the fin 4, and the dummy gate structure 8 covers a part of the top surface and a part of the sidewall of the fin 4. The pseudo gate structure 8 comprises a pseudo gate oxide layer 3 which conformally covers the fin portion 4 and a pseudo gate layer 5 which is positioned on the pseudo gate oxide layer 3. An isolation layer 2 is formed in the first groove 6 (shown in fig. 1) and the second groove 7 (shown in fig. 1), and the isolation layer 2 is made of silicon oxide.
As shown in fig. 3, the dummy gate structure 8 (shown in fig. 2) is removed. Get rid of pseudo-gate oxide 3 (as shown in fig. 2) in-process, isolation layer 2 in second recess 7 is easily by mistake sculpture, follow-up fin portion 4 and fin portion 4 exposes conformal cover work function layer (not shown in the figure) on isolation layer 2, the work function layer is metal material, and the material of substrate 1 is semiconductor material, and isolation layer 2's material is silicon oxide, and work function layer, substrate 1 and isolation layer 2 constitute parasitic device, works as isolation layer 2 in second recess 7 is too much when being sculpture, parasitic device in second recess 7 bottom is easily opened for transistor electrical property is not good.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a transistor structure, including: providing a substrate comprising a first region and a second region; etching the base of the first region to form a first substrate and a plurality of first fin parts which are separated from the first substrate, wherein a first groove is formed between every two adjacent first fin parts; etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove; doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor; and after ions are doped, forming an isolation layer in the first groove and the second groove.
In the embodiment of the invention, the base of the first area is etched to form a first substrate and a plurality of first grooves which are separated from the first substrate; etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove; doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor; and after ions are doped, forming an isolation layer in the first groove and the second groove. The transistor structure also typically includes a gate structure formed in the first recess and the second recess, the gate structure including a work function layer. The material of the first substrate and the second substrate is generally a semiconductor, the material of the isolation layer is generally a dielectric material, and the material of the work function layer is generally a metal material; therefore, the first substrate, the isolation layer and the work function layer form a parasitic device, but the parasitic device formed by the first substrate, the isolation layer and the work function layer is difficult to open because the isolation layer on the first substrate is thick. The second substrate, the isolation layer and the work function layer form a parasitic device, because the isolation layer on the second substrate is thin, the parasitic device formed by the second substrate, the isolation layer and the work function layer is easy to start, the doped ions are doped on the bottom surface of the second groove, namely in the second substrate, so that the Fermi level of the parasitic device tends to change towards the top of a valence band or tends to change towards the bottom of a conduction band, the Fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is improved, the parasitic device at the bottom of the second groove is not easy to start, and the electrical performance of the transistor is optimized.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to fig. 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a transistor structure according to the embodiment of the invention.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 including a first region I and a second region II.
The first area I is used for forming a first device, the second area II is used for forming a second device, and the power of the second device is higher than that of the first device.
A substrate 100 is provided, the substrate 100 providing a process platform for subsequently forming a first recess and a second recess.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, in order to improve the performance of the device, a SiGe channel technology may be used, that is, the material of the substrate includes silicon germanium, and the material of the corresponding subsequently formed fin and channel layer is SiGe. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the first region I and the second region II are adjacent regions. In other embodiments, the first region I and the second region II may also be spaced apart regions.
In this embodiment, the method for forming the transistor structure includes: forming the second groove in a second area II, and then forming the first groove in the first area I.
Specifically, a step of forming a second recess is performed, and referring to fig. 5 to 9, the base 100 in the second region II is etched to form a second substrate 200 (as shown in fig. 9) and a plurality of second fins discrete from the second substrate 200, and a second recess 202 (as shown in fig. 9) is formed between adjacent second fins.
The second recess 202 is used to provide a space for filling the isolation layer in the subsequent process.
As shown in fig. 5, the step of forming the second groove 202 includes: a masking material layer 110 is formed overlying the substrate 100, and a plurality of discrete core layers 120 are formed on the masking material layer 110.
The masking material layer 110 is used to prepare a subsequently formed masking layer. The core layer 120 is used to provide a process foundation for the subsequent formation of a mask sidewall covering the sidewall of the core layer 120.
In this embodiment, the material of the core layer 120 is polysilicon. In other embodiments, the material of the core layer 120 may also be amorphous carbon, ODL material, DARC material or BARC material.
The core layer 120 is etched at a rate greater than that of the mask material layer 110, so that damage to the mask material layer 110 can be reduced when the core layer 120 is removed.
As shown in fig. 6, a mask sidewall spacer 130 covering the sidewall of the core layer 120 is formed.
The mask sidewall 130 in the second region II is used to define the position and width of the second fin portion.
In the subsequent process, the mask material layer 110 is etched by using the mask sidewall spacers 130 as masks to form a mask layer.
The material of the mask side wall 130 is different from the material of the mask material layer 110, and the material of the mask side wall 130 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride and boron nitride. In this embodiment, the mask sidewall spacer 130 is made of silicon nitride.
As shown in fig. 7, a mask protection layer 140 is formed on the exposed mask material layer 110 of the core layer 120 and the mask sidewall spacers 130.
In this embodiment, the mask protection layer 140 is made of bottom anti-reflective coating.
As shown in fig. 8, a shielding layer 150 exposing the second region II is formed on the mask sidewall spacer 130.
In this embodiment, the material of the shielding layer 150 is different from the material of the mask protection layer 140 and the core layer 120, and the material of the shielding layer 150 is amorphous carbon. In other embodiments, the material of the shielding layer may also be ODL material or DARC material.
As shown in fig. 9, the substrate is etched using the shielding layer 150 as a mask to form a second groove 202.
Since the mask sidewall spacers 130 are used to define the position and width of the fin during the subsequent etching of the substrate. Correspondingly, a second groove 202 formed by etching the substrate of the second region with the mask sidewall spacers 130 as masks is located between the subsequently formed second fin portions.
The second recess 202 provides a space for a subsequently formed isolation layer. A first substrate and a first fin portion located on the first substrate are formed subsequently, the first substrate and the first fin portion form a first groove, and the depth of the second groove 202 is smaller than that of the first groove, that is, the second substrate 200 is closer to an external space than the first substrate. Therefore, the heat dissipation performance of the devices in the second region I is better than that of the devices in the first region.
In this embodiment, a second groove 202 is formed in the substrate 100 by etching the substrate 100. Specifically, in order to improve the topographic quality of the second groove 202, the substrate 100 is etched by using a dry etching process to form the second groove 202. In other embodiments, the substrate material may be removed by a wet etching process or a process combining wet etching and dry etching.
It should be noted that the second groove 202 cannot be too deep or too shallow, and if the second groove 202 is too deep, the aspect ratio of the second groove 202 is too large, which is not favorable for heat dissipation; if the second recess 202 is too shallow, the process space reserved for the isolation layer at the later stage becomes smaller, so that the parasitic device is easy to open. In this embodiment, the depth of the second groove 202 is 600 to 900 angstroms.
It should be noted that the method for forming a transistor structure according to this embodiment further includes: after the second groove 202 is formed, the mask protection layer 140 and the blocking layer 150 are removed. The mask protection layer 140 and the blocking layer 150 are removed in preparation for the subsequent formation of the first recess.
In this embodiment, the mask protection layer 140 and the blocking layer 150 are removed by an ashing process.
Referring to fig. 10, the bottom surface of the second recess 202 is doped with ions, which are opposite to the transistor.
In this embodiment, the fact that the type of the doping ions is opposite to the type of the doping ions of the transistor means that when the transistor is a PMOS, the doping ions are N-type ions; when the transistor is NMOS, the doped ions are P-type ions.
After doping ions, an isolation layer is subsequently formed in the first and second grooves 202, the top surfaces in the first and second grooves 202 are flush, because the depth of the second groove 202 is smaller than that of the first groove, and therefore the thickness of the isolation layer in the second groove 202 is smaller than that of the isolation layer in the first groove. The method of forming the transistor structure generally further includes forming a gate structure across the first and second fins, the gate structure further formed in the first and second recesses 202, the gate structure including a work function layer. The material of the second substrate 200 is typically a semiconductor, the material of the isolation layer is typically a dielectric layer, and the material of the work function layer is typically a metal material; the second substrate 200, the isolation layer and the work function layer form a parasitic device, because the isolation layer on the second substrate 200 is thin, the parasitic device formed by the second substrate 200, the isolation layer and the work function layer is easy to turn on, the doped ions are doped at the bottom surface of the second groove 202, that is, doped in the second substrate 200, so that the fermi level of the parasitic device tends to change towards the top of the valence band or tends to change towards the bottom of the conduction band, the fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is increased, the parasitic device at the bottom of the second groove 202 is not easy to turn on, and the electrical performance of the transistor is optimized.
In this embodiment, the second region II is used to form a PMOS transistor, and the doped ions include phosphorus. In other embodiments, the dopant ion may also be arsenic or antimony.
In other embodiments, the second region may further form an NMOS transistor, and the doped ions include boron, gallium, or indium.
In this embodiment, the bottom surface of the second groove 202 is doped with ions by ion implantation. Specifically, in the present embodiment, the mask sidewall spacers 130 and the mask material layer 110 are used as masks, and the ion implantation is performed on the bottom of the second groove 202.
Specifically, the process parameters of the doped ions include: the implantation dose is 1.0E13 atoms per square centimeter to 2.0E14 atoms per square centimeter, the implantation energy is 15KeV to 60KeV, and the angle between the ion implantation direction and the normal is 0 degree to 15 degrees.
In the process of doping ions, the injection dosage is not too large or too small, if the injection dosage is too large, crystal lattice damage is caused, and the crystal lattice is difficult to repair after damage is caused; if the implantation dose is too small, the threshold voltage of the parasitic device in the second groove 202 is not significantly increased.
In the process of doping ions, the injection energy is not too large or too small, if the injection energy is too large, crystal lattice damage is easily caused, and the crystal lattice damage is difficult to repair; if the implantation energy is too small, the position of the implanted ions is too shallow to reach the predetermined region, so that the threshold voltage of the parasitic device in the second groove 202 is not increased significantly.
It should be noted that, in this embodiment, before doping ions, the blocking layer 150 and the mask protection layer 140 are removed, and in the process of doping ions, ion implantation is performed by using the mask material layer 110 and the mask sidewall 130 as masks. In other embodiments, the shielding layer and the mask protection layer may be removed after the ions are doped, and in the process of doping the ions, ion implantation is performed with the shielding layer and the mask protection layer as masks.
Referring to fig. 11 to 12, etching the base 100 in the first region I to form a first substrate 300 (as shown in fig. 12) and a plurality of first fins 301 (as shown in fig. 12) separated from the first substrate 300, wherein a first groove 302 (as shown in fig. 12) is formed between adjacent first fins 301; the depth of the second recess 202 (shown in fig. 9) is less than the depth of the first recess 302. The first recess 302 is used to provide a spatial location for filling an isolation layer in a subsequent process.
As shown in fig. 11, the step of forming the first groove 302 includes: a groove protection layer 203 is formed in the second groove 202.
The groove protection layer 203 is used for protecting the second groove 202 doped with ions in the process of etching the substrate of the first region I to form the first groove.
In this embodiment, the groove protection layer 203 is made of bottom anti-reflective coating, silicon oxide, silicon nitride, or silicon oxynitride.
As shown in fig. 12, the substrate 100 in the first region I is etched by using the mask sidewall spacers 130 as a mask, so as to form the first groove 302. Between the first grooves 302 are first fins 301, and at the bottom of the first grooves 302 is a first substrate 300.
The first groove 302 is used for providing a space for an isolation layer to be formed later, the depth of the first groove 302 is large, so that the thickness of the filled isolation layer is large, and the opening of a parasitic device can be inhibited due to the large thickness of the isolation layer.
It should be noted that, the step of etching the substrate 100 with the mask sidewall spacers 130 as the mask, and forming the first groove 302 further includes: and etching the mask material layer 110 by using the mask side wall 130 as a mask to form a mask layer 160.
It should be further noted that the first groove 302 cannot be too deep or too shallow, and if the first groove 302 is too deep, the aspect ratio of the first groove 302 is too large to facilitate heat dissipation; if the first groove 302 is too shallow, the process space reserved for the isolation layer at the later stage is reduced, which is not beneficial to reducing the probability of opening the parasitic device. In this embodiment, the depth of the first groove 302 is 1000 to 1500 angstroms.
In this embodiment, the first region I and the second region II are adjacent regions, the substrate 100 is etched by using the mask sidewall 130 as a mask, and the step of forming the first groove 302 further includes: in the second region II, the second fin portion 201 is formed at a position close to a boundary between the first region I and the second region II.
It should be noted that, in this embodiment, besides the first groove 302 between the first fin 301 and the first fin 301, the groove between the first fin 301 and the second fin 201 close to the first region I is also the first groove 302.
In this embodiment, the first region I and the second region II are adjacent regions, and a boundary between the first region I and the second region II is exactly the position of the sidewall of the second fin 201. In other embodiments, the boundary between the first region and the second region may be a substrate with any height.
Referring to fig. 13, some of the first fin 301 and the second fin 201 are dummy fins 303. The forming method of the transistor structure further comprises the following steps: after the second fin portion 201 and the first fin portion 301 are formed, and before the isolation layer is formed, the dummy fin portion 303 is removed.
Referring to fig. 14, after doping ions, an isolation layer 204 is formed in the first recess 302 (shown in fig. 12) and the second recess 202 (shown in fig. 9). The isolation layer 204 is used to isolate adjacent devices.
The step of forming the isolation layer 204 in the first recess 302 and the second recess 202 comprises: forming an isolation material layer covering the first groove 302 and the second groove 202 respectively, and carrying out planarization treatment on the isolation material layer; after the planarization process, the isolation material layer with a partial thickness is etched back, the remaining isolation material layer in the first groove 302 is used as the first isolation layer 206, the remaining isolation material layer in the second groove 202 is used as the second isolation layer 205, and the first isolation layer 206 and the second isolation layer 205 form the isolation layer 204.
In this embodiment, the density of the second isolation layer 205 is greater than that of the first isolation layer 206.
In the subsequent process, the dummy gate oxide layer is formed on the first fin portion 301 and the second fin portion 201, the material of the dummy gate oxide layer is usually silicon oxide, and when the dummy gate oxide layer is removed, because the density of the second isolation layer 205 is greater than that of the first isolation layer 206, the etching rate of the second isolation layer 205 is less than that of the dummy gate oxide layer, so that the second isolation layer 205 is damaged less, the probability of opening a parasitic device at the bottom of the second groove 202 is reduced, and the electrical performance of the transistor structure is improved.
Specifically, the material of the second isolation layer 205 is silicon nitride, and the material of the first isolation layer 206 is silicon oxide. In other embodiments, other insulating materials may also be used.
It should be noted that the thickness of the second isolation layer 205 in the second groove 202 cannot be too thick or too thin. If the second isolation layer 205 is too thick, it is not favorable for the heat dissipation of the device in the second region II; if the thickness of the second isolation layer 205 is too thin, the parasitic devices at the bottom of the second recess 202 are easily turned on. Thus, the thickness in the second isolation layer 205 is 25 nm to 50 nm.
In the subsequent process, the method for forming the transistor further comprises the following steps: forming a gate structure (not shown) crossing the first fin portion 301 and the second fin portion 201, where the gate structure includes a work function layer, and the second substrate 200, the second isolation layer 205 and the work function layer constitute a parasitic device, and the doped ions are doped at the bottom surface of the second recess 202, that is, doped in the second substrate 200, so that the fermi level of the parasitic device tends to change towards the top of the valence band, or tends to change towards the bottom of the conduction band, the fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is increased, the parasitic device at the bottom of the second recess 202 is not easily turned on, and the electrical performance of the transistor is optimized.
In other embodiments, the first groove may be formed first, and then the second groove may be formed, which is not described herein again.
The step of forming the first groove includes: forming a masking material layer overlying the substrate, forming a plurality of discrete core layers on the masking material layer; forming a mask side wall covering the side wall of the core layer; forming a mask protective layer on the exposed mask material layer of the core layer and the exposed mask side wall; forming a shielding layer exposing the first region on the mask side wall; etching the substrate by taking the shielding layer as a mask to form a first groove; and after the first groove is formed, removing the shielding layer, the core layer and the mask protective layer.
The step of forming the second groove includes: forming a groove protection layer in the first groove; etching the substrate of the second region by taking the mask side wall as a mask to form the second groove; the forming method of the transistor structure comprises the following steps: and removing the groove protection layer after the second groove is formed.
The invention also provides a transistor structure. Referring to fig. 14, a schematic diagram of an embodiment of the transistor structure of the present invention is shown.
Referring to fig. 14, the transistor structure includes: a substrate 100, the substrate 100 comprising a second region II and a first region I; the first region I comprises a first substrate 300 and a plurality of first fins 301 separated from the first substrate 300, and a first groove 302 is formed between adjacent first fins 301 (as shown in fig. 12); the second region II includes a second substrate 200 and a plurality of second fins 201 separated from the second substrate 200, a second groove 202 (as shown in fig. 9) is formed between adjacent second fins 201, and a depth of the second groove 202 is smaller than a depth of the first groove 302; doped ions located at the bottom of the second groove 202, wherein the type of the doped ions is opposite to that of the transistor; and the isolation layer 204 is positioned in the second groove 202 and the first groove 302.
In this embodiment, the fact that the type of the doping ions is opposite to the type of the doping ions of the transistor means that when the transistor is a PMOS, the doping ions are N-type ions; when the transistor is NMOS, the doped ions are P-type ions.
The transistor structure typically further comprises a gate structure comprising a work function layer spanning the first fin 301 and the second recess 201.
The material of the first substrate 300 and the second substrate 200 is typically a semiconductor, the material of the isolation layer 204 is typically a dielectric material, and the material of the work function layer is typically a metal material; therefore, the first substrate 300, the isolation layer 204 and the work function layer constitute a parasitic device, but the parasitic device constituted by the first substrate 300, the isolation layer 204 and the work function layer is difficult to open because the isolation layer 204 on the first substrate 300 is thick. The second substrate 200, the isolation layer 204 and the work function layer form a parasitic device, because the isolation layer 204 on the second substrate 200 is thin, the parasitic device formed by the second substrate 200, the isolation layer 204 and the work function layer is easy to turn on, but because the doped ions are located at the bottom surface of the second groove 202, that is, doped in the second substrate 200, the fermi level of the parasitic device tends to change towards the top of the valence band, or tends to change towards the bottom of the conduction band, the fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is increased, the parasitic device at the bottom of the second groove 202 is not easy to turn on, and the electrical performance of the transistor is optimized.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
In this embodiment, the first region I and the second region II are adjacent regions. In other embodiments, the first region and the second region may also be isolated. In this embodiment, a boundary between the first region I and the second region II is exactly the position of the sidewall of the second fin portion 201. In other embodiments, the boundary between the first region and the second region may be a substrate with any height.
In this embodiment, the second groove 202 cannot be too deep or too shallow, if the second groove 202 is too deep, the distance from the second groove 202 to the external space is too far, so that the aspect ratio of the second groove 202 is too large to facilitate heat dissipation, and if the second groove 202 is too shallow, the second isolation layer 205 is thinner to facilitate increasing the turn-on voltage of the parasitic device. Accordingly, the depth of the second groove 202 is 600 to 900 angstroms.
In this embodiment, the first groove 302 cannot be too deep or too shallow, if the first groove 302 is too deep, the distance between the first groove 302 and the external space is too far, so that the aspect ratio of the first groove 302 is too large to facilitate heat dissipation, and if the first groove 302 is too shallow, the first isolation layer 206 is thin to facilitate improvement of the turn-on voltage of the parasitic device. Accordingly, the depth of the first recess 302 is 1000 to 1500 angstroms.
In this embodiment, the isolation layer 204 is formed in the first groove 302 and the second groove 202, the isolation layer 204 in the second groove 202 is the second isolation layer 205, and the isolation layer in the first groove 302 is the first isolation layer 206, because the depth of the second groove 202 is smaller than the depth of the first groove 302, and the thickness of the second isolation layer 205 is smaller than the thickness of the first isolation layer 206.
And the doped ions are located at the bottom surface of the second groove 202, the type of the doped ions is opposite to that of the transistor, and the doped ions enable the fermi level of the parasitic device at the bottom surface of the second groove 202 to tend to change towards the top of the conduction band, so that the fermi potential of the parasitic device is increased, the threshold voltage of the parasitic device is increased, the parasitic device at the bottom of the second groove 202 is not easy to turn on, and the electrical performance of the transistor is optimized.
In this embodiment, the second region II is used to form a PMOS transistor, and the doped ions are phosphorous ions. In other embodiments, the dopant ion may also be arsenic or antimony.
In other embodiments, the second region is used to form an NMOS transistor, and the doped ions are boron, gallium, or indium.
In this embodiment, the density of the second isolation layer 205 is higher than that of the first isolation layer 206.
In the subsequent process, a dummy gate structure (not shown in the figure) is formed to cross the first fin portion 301 and the second fin portion 201, the dummy gate structure includes a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer, and the dummy gate oxide layer is usually made of silicon oxide. When the dummy gate structure is removed, the etched rate of the second isolation layer 205 in the second groove 202 is less than the etched rate of the dummy gate oxide layer, and the second isolation layer 205 is damaged slightly, so that a parasitic device at the bottom of the second groove 202 is difficult to open, and the leakage probability of the parasitic device is reduced.
Specifically, the material of the first isolation layer 206 is silicon oxide, and the material of the second isolation layer 205 is silicon nitride.
It should be noted that the first recess 302 is deeper than the second recess 202, because the top surfaces of the first isolation layer and the second isolation layer are flush, and therefore, the thickness of the second isolation layer 205 is smaller than the thickness of the first isolation layer 206. The parasitic devices at the bottom of the first recess 302 are therefore difficult to turn on.
The transistor structure described in this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. In this embodiment, for specific description of the transistor structure, reference may be made to corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a transistor structure, comprising:
providing a substrate comprising a first region and a second region;
etching the base of the first region to form a first substrate and a plurality of first fin parts which are separated from the first substrate, wherein a first groove is formed between every two adjacent first fin parts;
etching the base of the second region to form a second substrate and a plurality of second fin parts which are separated from the second substrate, wherein a second groove is formed between every two adjacent second fin parts; the depth of the second groove is smaller than that of the first groove;
doping ions on the bottom surface of the second groove, wherein the type of the doping ions is opposite to that of the transistor;
and after ions are doped, forming an isolation layer in the first groove and the second groove.
2. The method of claim 1, wherein the step of doping ions at the bottom of the second recess comprises: and doping ions on the bottom surface of the second groove by adopting an ion implantation mode.
3. The method of claim 1, wherein the transistor is a PMOS transistor, and the doped ions comprise phosphorus, arsenic, or antimony; or, the transistor is an NMOS transistor, and the doped ions include boron, gallium, or indium.
4. The method of forming a transistor structure of claim 1, wherein the dopant ion process parameters comprise: the implantation dose is 1.0E13 atoms per square centimeter to 2.0E14 atoms per square centimeter, the implantation energy is 15KeV to 60KeV, and the angle between the ion implantation direction and the normal is 0 degree to 15 degrees.
5. The method of forming a transistor structure according to claim 1, wherein the step of forming an isolation layer in the first and second recesses comprises:
forming a first isolation layer in the first groove; and forming a second isolating layer in the second groove, wherein the density of the second isolating layer is higher than that of the first isolating layer.
6. The method according to claim 5, wherein a material of the first spacer is silicon oxide, and a material of the second spacer is silicon nitride.
7. The method of claim 1, wherein the second recess is formed first, and then the first recess is formed; or, the first groove is formed first, and then the second groove is formed.
8. The method of forming a transistor structure of claim 1,
the step of forming the second groove includes:
forming a masking material layer overlying the substrate, forming a plurality of discrete core layers on the masking material layer;
forming a mask side wall covering the side wall of the core layer;
forming a mask protective layer on the exposed mask material layer of the core layer and the exposed mask side wall;
forming a shielding layer exposing the second region on the mask side wall;
etching the substrate by taking the shielding layer as a mask to form a second groove;
after the second groove is formed, removing the shielding layer, the core layer and the mask protective layer;
the step of forming the first groove includes:
forming a groove protection layer in the second groove;
etching the substrate of the first region by taking the mask side wall as a mask to form the first groove;
the forming method of the transistor structure comprises the following steps: and removing the groove protection layer after the first groove is formed.
9. The method of claim 8, wherein the trench protection layer is made of BARC, silicon oxide, silicon nitride, or silicon oxynitride.
10. The method of forming a transistor structure according to claim 1, wherein a depth of the second recess is 600 to 900 angstroms.
11. The method of forming a transistor structure according to claim 1, wherein a depth of the first recess is 1000 to 1500 angstroms.
12. The method of forming a transistor structure of claim 1, wherein the gate structure comprises a work function layer during forming the gate structure across the first fin and the second fin.
13. A transistor structure, comprising:
a substrate comprising a second region and a first region;
the first region comprises a first substrate and a plurality of first fin parts separated from the first substrate, and a first groove is formed between every two adjacent first fin parts;
the second region comprises a second substrate and a plurality of second fin parts separated from the second substrate, a second groove is formed between every two adjacent second fin parts, and the depth of the second groove is smaller than that of the first groove;
the doped ions are positioned on the bottom surface of the second groove, and the type of the doped ions is opposite to that of the transistor;
and the isolation layer is positioned in the second groove and the first groove.
14. The transistor structure of claim 13, wherein a depth of said second recess is 600 to 900 angstroms.
15. The transistor structure of claim 13, wherein a depth of said first recess is from 1000 to 1500 angstroms.
16. The transistor structure of claim 13, wherein said transistor is a PMOS transistor and said second trench bottom surface is doped with ions comprising phosphorus, arsenic or antimony.
17. The transistor structure of claim 13, wherein said transistor is an NMOS transistor and said second trench bottom surface is doped with ions comprising boron, gallium, or indium.
18. The transistor structure of claim 13, wherein a thickness of the isolation layer in the second recess is 25 nm to 50 nm.
19. The transistor structure of claim 13, wherein said isolation layer in said first recess is a first isolation layer, and said isolation layer in said second recess is a second isolation layer, said second isolation layer having a density that is higher than a density of said first isolation layer.
20. The transistor structure of claim 19, wherein said first spacer material is silicon oxide and said second spacer material is silicon nitride.
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