CN111354677A - Preparation method of deep trench isolation structure and semiconductor device - Google Patents

Preparation method of deep trench isolation structure and semiconductor device Download PDF

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CN111354677A
CN111354677A CN202010156436.5A CN202010156436A CN111354677A CN 111354677 A CN111354677 A CN 111354677A CN 202010156436 A CN202010156436 A CN 202010156436A CN 111354677 A CN111354677 A CN 111354677A
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heavily doped
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CN111354677B (en
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许昭昭
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

The application discloses a preparation method of a deep trench isolation structure and a semiconductor device. In the preparation process of the LDMOS device, after a first groove corresponding to a deep groove isolation structure is etched and formed, phosphorus ion implantation is carried out on the first groove, an N-type heavily doped layer is formed on the side wall and the bottom of the first groove, and the N-type heavily doped layer can lead out an N-type buried region which is in contact with the N-type heavily doped layer, so that the deep N-type well is not required to be led out by high-temperature thermal propulsion in a long time when the deep N-type well is formed, the deep N-type well is diffused to be in contact with the N-type buried layer, the high-temperature thermal propulsion processing time is shortened, and the manufacturing cost is reduced; meanwhile, the high-temperature thermal propulsion time is shortened, so that the upward further diffusion of the N-type buried layer is prevented, the withstand voltage length in the longitudinal structure of the device is increased, and the longitudinal withstand voltage is improved.

Description

Preparation method of deep trench isolation structure and semiconductor device
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of a Deep Trench Isolation (DTI) structure and a semiconductor device.
Background
With the increasing application voltage of Lateral Double-diffused Metal-oxide semiconductor (LDMOS) devices, higher requirements are also put forward on the voltage endurance capability of the isolation structure between the high-voltage device and the low-voltage device. An isolation structure of a PN Junction (Positive Negative Junction) is widely used in a low-voltage BCD (Bipolar-CMOS-DMOS) process, but the size of the PN Junction isolation structure is sharply increased along with the increase of a withstand voltage, and a leakage current of the PN Junction isolation is also increased. Therefore, in order to reduce the size of the isolation structure and reduce the leakage effect, the deep trench isolation structure is gradually applied to the mid-high voltage BCD process. The greatest advantage of deep trench isolation structures is the smaller size compared to PN junction isolation.
Referring to fig. 1, which shows a schematic cross-sectional view of a device including a Deep trench isolation structure provided in the related art, as shown in fig. 1, in the device provided in the related art, a high-energy phosphorus ion implantation is performed on a surface of a P-type epitaxial Layer to extract an N-type Buried Layer (NBL) 106, and after the phosphorus ion implantation, the phosphorus ion implantation is performed downwards by a long-time high-temperature thermal process Drive (Drive-in), so that the phosphorus ion implantation is performed while the N-type Buried Layer 106 is diffused upwards to form a Deep N-type Well (DNW) 105 and the N-type Buried Layer 106 shown in fig. 1, and the N-type Buried Layer 106 is extracted to an electrode.
With the increasing of the application voltage of the LDMOS device, the thickness of the P-type epitaxial layer needs to be increased continuously, and in order to make the deep N-type well 105 and the N-type buried layer 106 fully contact, the time for high-temperature thermal propulsion needs to be increased continuously under the condition that the phosphorus ion implantation energy is limited, so that the manufacturing cost is increased; in addition, increasing the thermal process time may cause the N-type buried layer 106 to diffuse upward, reducing the longitudinal breakdown voltage of the deep trench isolation structure.
Disclosure of Invention
The application provides a preparation method of a deep trench isolation structure and the deep trench isolation structure, which can solve the problem that the manufacturing cost of the deep trench isolation structure provided in the related technology is high due to long high-temperature thermal propulsion time in the preparation process.
In one aspect, an embodiment of the present application provides a method for manufacturing a deep trench isolation structure, where the method is applied to a process for manufacturing an LDMOS device, and the method includes:
providing a P (Positive) type substrate, sequentially comprising a first region, a second region, a third region and a fourth region along the length direction of the section of the P type substrate, wherein N type buried layers are formed in the P type substrate of the second region and the third region, a P type epitaxial layer is formed on the P type substrate, deep N type wells are formed in the P type epitaxial layers of the second region and the third region, a first silicon oxide layer and a hard mask layer are sequentially formed on the P type epitaxial layer, an isolation dielectric layer is formed in the P type epitaxial layer of each region, a second silicon oxide layer is formed on the hard mask layer, and the deep N type wells are not in contact with the N type buried layers;
etching to form a first groove, exposing the P-type substrate at the bottom of the first groove, performing phosphorus ion implantation on the first groove by taking the second silicon oxide layer as a shielding layer, forming N-type heavily doped layers on the side wall and the bottom of the first groove, and enabling the N-type heavily doped layers of the second region and the third region to be in contact with the N-type buried layer and the deep N-type well;
forming a polysilicon layer on the side wall and the bottom of the first groove;
carrying out thermal oxidation treatment on the polycrystalline silicon layer to convert the polycrystalline silicon layer into silicon oxide, and etching the silicon oxide to expose the P-type substrate at the bottom of the first trench;
etching the first groove to a target depth below the P-type substrate by taking the second silicon oxide layer as a mask layer to form a second groove, and implanting boron ions into the P-type substrate at the bottom of the second groove to form a bottom P-type doped region;
performing thermal oxidation treatment on the polycrystalline silicon on the side wall and the bottom of the second trench to convert the polycrystalline silicon on the side wall and the bottom of the second trench into silicon oxide, wherein the silicon oxide converted on the side wall and the bottom of the second trench and the silicon oxide converted on the polycrystalline silicon layer form a third silicon oxide layer;
and filling polysilicon in the second Trench to form the deep Trench Isolation structure, and planarizing to remove the hard mask layer to form a Shallow Trench Isolation (STI) structure.
Optionally, in the process of performing phosphorus ion implantation on the first trench by using the second silicon oxide layer as the shielding layer, a value range of energy of the phosphorus ion implantation is 15 kilo-electron volts (KeV) to 75 kilo-electron volts.
Optionally, in the process of implanting phosphorus ions into the first trench by using the second silicon oxide layer as the shielding layer, a value range of a dose of the phosphorus ions is 1 × 1014Per square centimeter (cm)-2) To 5 × 1014Per square centimeter.
Optionally, in the process of performing phosphorus ion implantation on the first trench by using the second silicon oxide layer as the shielding layer, a value range of an angle of the phosphorus ion implantation is 7 to 45 degrees.
Optionally, the forming a polysilicon layer on the sidewall and the bottom of the first trench includes:
depositing the polysilicon layer on the sidewall and the bottom of the first trench by a Chemical Vapor Deposition (CVD) process; or, forming the polysilicon layer on the side wall and the bottom of the first trench by a silicon epitaxial process.
Optionally, in the process of performing phosphorus ion implantation on the first trench by using the second silicon oxide layer as the shielding layer, an angle of phosphorus ion implantation is 0 degree.
Optionally, after performing thermal oxidation treatment on the P-type substrate at the bottom of the second trench and before filling the second trench with polysilicon, the method further includes:
depositing silicon oxide in the second trench.
Optionally, before the etching to form the first trench, the method further includes:
carrying out antimony ion implantation on the P-type substrate, and carrying out high-temperature thermal propulsion to form the N-type buried layer in the P-type substrate;
carrying out epitaxial growth on the P-type substrate to form the P-type epitaxial layer;
performing high-energy phosphorus ion implantation on the P-type epitaxial layer, and performing high-temperature thermal propulsion to form the deep N-type well in the P-type epitaxial layer;
sequentially forming a fourth silicon oxide layer and a hard mask layer on the P-type epitaxial layer;
etching and forming a third groove between each region, and exposing the P-type epitaxial layer at the bottom of the third groove;
and forming the second silicon oxide layer in the exposed P-type epitaxial layer, filling a fifth silicon oxide layer in the first groove to form the isolation medium layer, and forming the second silicon oxide layer on the third silicon oxide layer and the hard mask layer.
Optionally, after the planarizing and removing the hard mask layer, the method further includes:
performing ion implantation, and forming a first P-type well and a first N-type well in the P-type epitaxial layer of the first region; forming a second N-type well in the P-type epitaxial layer of the second region, forming a third N-type well in the P-type epitaxial layer of the third region, forming a fourth N-type well and a second P-type well in the P-type epitaxial layer of the fourth region, wherein the first N-type well and the fourth N-type well are respectively in contact with the N-type heavily doped layer;
and carrying out ion implantation, forming a first P-type heavily doped region in the first P-type well, forming a first N-type heavily doped region in the first N-type well, forming a second N-type heavily doped region in the second N-type well, forming a third N-type heavily doped region in the third N-type well, forming a fourth N-type heavily doped region in the fourth N-type well, and forming a second P-type heavily doped region in the second P-type well.
Optionally, after the ion implantation, the method further includes:
forming an interlayer dielectric layer on the P-type epitaxial layer and the shallow trench isolation layer;
etching through holes in the interlayer dielectric layer, wherein the through holes respectively expose the first P-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, the fourth N-type heavily doped region and the second P-type heavily doped region;
filling a metal layer in the through hole, and carrying out planarization treatment on the metal layer to form a contact through hole;
and a lead is formed on each contact through hole, the contact through holes connected with the first P-type heavily doped region and the first N-type heavily doped region are connected with the same lead, and the contact through holes connected with the second P-type heavily doped region and the fourth N-type heavily doped region are connected with the same lead.
Optionally, the planarizing the metal layer to form a contact via includes:
the contact via is formed by planarizing the metal layer by a Chemical Mechanical Polishing (CMP) process.
Optionally, the thickness of the N-type heavily doped layer ranges from 100 angstroms
Figure BDA0002404213850000041
To 1000 angstroms.
Optionally, the hard mask layer includes silicon nitride.
In another aspect, the present application provides a semiconductor device comprising:
the P-type substrate sequentially comprises a first region, a second region, a third region and a fourth region along the length direction of a section, and N-type buried layers are formed in the P-type substrate of the second region and the P-type substrate of the third region;
the P-type epitaxial layer is formed on the P-type substrate, a shallow trench isolation structure is formed in the P-type epitaxial layer of each region, and deep N-type wells are formed in the P-type epitaxial layers of the second region and the third region;
the P-type epitaxial layers of the first region and the second region, the P-type epitaxial layers of the second region and the third region and the P-type epitaxial layers of the third region and the fourth region are formed with deep trench isolation structures, N-type heavily doped layers are formed in the P-type epitaxial layers on the peripheral sides of the deep trench isolation structures, the N-type heavily doped layers of the second region and the third region are in contact with the N-type buried layer and the deep N-type well, the outermost layer of the deep trench isolation structures comprises a third silicon oxide layer, polysilicon is filled in the third silicon oxide layer, and a bottom P-type doped region is formed in a P-type substrate in contact with the bottoms of the deep trench isolation structures;
a first P-type well and a first N-type well are formed in a P-type epitaxial layer of the first region, a first P-type heavily doped region is formed in the first P-type well, a first N-type heavily doped region is formed in the first N-type well, and the first N-type well is in contact with the N-type heavily doped region;
a second N-type well is formed in the P-type epitaxial layer of the second region, and a second N-type heavily doped region is formed in the second N-type well;
a third N-type well is formed in the P-type epitaxial layer of the third region, and a third N-type heavily doped region is formed in the third N-type well;
and a fourth N-type well and a second P-type well are formed in the P-type epitaxial layer of the fourth region, a fourth N-type heavily doped region is formed in the fourth N-type well, the fourth N-type well is in contact with the N-type heavily doped layer, and a second P-type heavily doped region is formed in the second P-type well.
Optionally, an interlayer dielectric layer is formed on the P-type epitaxial layer;
a contact through hole is formed in the interlayer dielectric layer, and the bottom end of the contact through hole is respectively connected with the first P-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, the fourth N-type heavily doped region and the second P-type heavily doped region;
and a lead is formed on each contact through hole, the contact through holes connected with the first P-type heavily doped region and the first N-type heavily doped region are connected with the same lead, and the contact through holes connected with the second P-type heavily doped region and the fourth N-type heavily doped region are connected with the same lead.
The technical scheme at least comprises the following advantages:
in the preparation process of the LDMOS device, after a first groove corresponding to the deep groove isolation structure is etched and formed, phosphorus ion implantation is carried out on the first groove, an N-type heavily doped layer is formed on the side wall and the bottom of the first groove, and the N-type heavily doped layer can lead out an N-type buried region which is in contact with the N-type heavily doped layer, so that the deep N-type well is not required to be led out due to the fact that long time is consumed for carrying out high-temperature thermal propulsion when the deep N-type well is formed, the deep N-type well is diffused to be in contact with the N-type buried layer, and the high-temperature thermal propulsion processing time; meanwhile, due to the fact that high-temperature thermal propulsion time is shortened, further upward diffusion of the N-type buried layer is prevented, breakdown voltage in a longitudinal structure of the device is increased, and longitudinal voltage-resisting capacity is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a device including a deep trench isolation structure provided in the related art;
FIG. 2 is a flow chart of a method for fabricating a deep trench isolation structure provided in an exemplary embodiment of the present application;
fig. 3 to 8 are flow charts of the preparation of the deep trench isolation structure provided in an exemplary embodiment of the present application;
fig. 9 is a flow chart of a method of fabricating a semiconductor device provided in an exemplary embodiment of the present application;
fig. 10 is a schematic cross-sectional view of an LDMOS device provided in an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flow chart of a method for manufacturing a deep trench isolation structure, which can be applied in a process for manufacturing an LDMOS device, according to an exemplary embodiment of the present application is shown, and the method includes:
step S1, providing a P-type substrate, sequentially including a first region, a second region, a third region and a fourth region along a length direction of a cross section of the P-type substrate, forming N-type buried layers in the P-type substrate of the second region and the third region, forming a P-type epitaxial layer on the P-type substrate, forming deep N-type wells in the P-type epitaxial layers of the second region and the third region, sequentially forming a first silicon oxide layer and a hard mask layer on the P-type epitaxial layer, forming an isolation dielectric layer in the P-type epitaxial layer of each region, forming a second silicon oxide layer on the hard mask layer, and making the deep N-type wells not contact with the N-type buried layers.
Referring to fig. 3, which shows a schematic cross-sectional view of a device formed with the structure provided in step S1, as shown in fig. 3, a P-type substrate 101 is sequentially formed with a first region 201, a second region 202, a third region 203 and a fourth region 204 along a cross-sectional length direction of the P-type substrate 101 (a direction indicated by an arrow in fig. 3), a P-type epitaxial layer 102 is formed on the P-type substrate 101 by epitaxial growth, an N-type buried layer 106 is formed in the P-type substrate 101, a deep N-type well 105 is formed in the P-type epitaxial layer 102, a fourth silicon oxide layer 1211 and a hard mask layer 120 are sequentially formed on the P-type epitaxial layer 102, an isolation dielectric layer (indicated by a dotted line in fig. 3) is formed in the P-type epitaxial layer 102 of each region (i.e., each of the first region 201, the second region 202, the third region 203 and the fourth region 204), a second silicon oxide layer 1213 is formed on the hard mask layer 120, wherein, deep N-well 105 is not in contact with buried N-type layer 106.
Illustratively, the first region 201 and the fourth region 204 are Low Voltage (V)Low) The device region, the second region 202 and the third region 203 are High Voltage (V)High) And a device region.
Optionally, in this embodiment, before step S1, the method further includes:
and step P1.1, carrying out antimony ion implantation on the P-type substrate 101, and carrying out high-temperature thermal propulsion to form an N-type buried layer 106 in the P-type substrate 101.
And P1.2, performing epitaxial growth on the P-type substrate 101 to form a P-type epitaxial layer 102.
And step P1.3, performing high-energy phosphorus ion implantation on the P-type epitaxial layer 102, and performing high-temperature thermal propulsion to form a deep N-type well 105 in the P-type epitaxial layer 102.
Exemplarily, referring to fig. 3, in step P1.3, since it is not necessary to diffuse deep N-well 105 into contact with N-type buried layer 106, it is not necessary to perform a high temperature drive-in process for a long time.
In step P1.4, a fourth silicon oxide layer 1211 and a hard mask layer 120 are sequentially formed on the P-type epitaxial layer 102.
Exemplarily, referring to fig. 3, the fourth silicon oxide layer 1211 may be formed by performing a thermal oxidation process on the P-type epitaxial layer 102; the hard mask layer 120 is formed by depositing silicon nitride on the fourth silicon oxide layer 1211 through a CVD process, such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
And step P1.5, etching and forming third grooves 205 between each region, and exposing the P-type epitaxial layer 102 at the bottoms of the third grooves 205.
Illustratively, referring to fig. 3, third trenches 205 may be formed for the shield layer by etching with the hard mask layer 120, and the P-type epitaxial layer 102 at the bottom of each third trench 205 is exposed. The third trench 205 is a shallow trench, which is used as a trench corresponding to the isolation dielectric layer.
Step P1.6 is to fill the fifth silicon oxide layer in the third trench, and form a second silicon oxide layer on the fifth silicon oxide layer and the hard mask layer.
Illustratively, referring to fig. 3, after depositing a thick fifth silicon oxide layer 1212 in the third trench 205, planarizing the fifth silicon oxide layer 1212 (e.g., planarizing by a CMP process) to planarize the surface and expose the hard mask layer 120, a second silicon oxide layer 1213 is deposited on the fifth silicon oxide layer 1212 and the hard mask layer 120.
It should be noted that the structure formed in step S1 can be prepared by the method provided in step P1.1 to step P1.6, or can be prepared by other methods, and the method provided in step P1.1 to step P1.6 is only an optional method.
Step S2, forming a first trench by etching, exposing the P-type substrate at the bottom of the first trench, implanting phosphorus ions into the first trench using the second silicon oxide layer as a shielding layer, forming N-type heavily doped layers on the sidewalls and the bottom of the first trench, and contacting the N-type heavily doped layers of the second region and the third region with the N-type buried layer and the deep N-type well.
In this embodiment, the trench corresponding to the deep trench isolation structure (shown by the dotted line in fig. 8) is formed by two-stage etching, wherein the trench formed by the first-stage etching is the first trench 206 etched in step S2.
Referring to fig. 4, which shows a schematic cross-sectional view of the structure formed in step S2, as shown in fig. 4, a photoresist may be covered in a predetermined region (other region except for the region to be etched) of the second silicon oxide layer 1213 by a photolithography process, the exposed region not covered by the photoresist is etched until the P-type substrate 101 is exposed, after the photoresist is removed, low-energy, high-dose, and high-angle phosphorus ion implantation is performed on the first trench 206 by using the second silicon oxide layer 1213 as a shielding layer, and an N-type heavily doped layer 116 is formed on the sidewall and the bottom of the first trench 206, wherein the N-type heavily doped layer 116 of the second region 202 is in contact with the N-type buried layer 106 and the deep N-type well 105, respectively, and the N-type heavily doped layer 116 of the third region 203 is in contact with the N-type buried layer 106 and the deep N-type well.
Optionally, in the step S2 of performing phosphorus ion implantation on the first trench by using the second silicon oxide layer as the shielding layer, the phosphorus ion implantation may be set to at least one of the following parameter ranges, where the energy of the phosphorus ion implantation ranges from 15 kev to 75 kev, and the dose of the phosphorus ion ranges from 1 × 10145 × 10 per square centimeter14The range of the angle of phosphorus ion implantation is 7 to 45 degrees per square centimeter.
In step S3, a polysilicon layer is formed on the sidewalls and bottom of the first trench.
Referring to fig. 5, a cross-sectional view of the polysilicon layer 122 formed on the sidewalls and bottom of the first trench 206 is shown. Optionally, in this embodiment, the polysilicon layer 122 may be deposited on the sidewalls and the bottom of the first trench 206 by a CVD process; alternatively, the polysilicon layer 122 is formed on the sidewalls and bottom of the first trench 206 by a silicon epitaxial process.
It should be noted that if the silicon epitaxy technique is used in step S3, polysilicon is formed on the surface and side of the insulating dielectric layer (e.g., the silicon oxide layer and the hard mask layer in the embodiment of the present application), and single crystal silicon is formed on the surface and side of the insulating dielectric layer, which is generally illustrated by the polysilicon layer 122 in the present application.
And step S4, performing thermal oxidation treatment on the polysilicon layer to convert the polysilicon layer into silicon oxide, and etching the silicon oxide to expose the P-type substrate at the bottom of the first trench.
Referring to fig. 6, which shows a schematic cross-sectional view of the silicon oxide 1101 formed after step S4 and after etching the first trench 206, as shown in fig. 6, the P-type substrate 101 is exposed after etching the first trench 206.
It should be noted that, in the thermal oxidation process, phosphorus impurities in the polysilicon of the heavily doped N-type region 116 are gradually diffused into the silicon sidewall of the deep trench isolation structure, and form the final heavily doped N-type layer 116 together with the injected phosphorus impurities, so that the on-resistance of the heavily doped N-type layer 116 is reduced. After the polysilicon is completely oxidized into silicon oxide, the silicon oxide is attached to the silicon surface of the sidewall of the deep trench isolation structure, so as to protect the N-type heavily doped layer 116 and prevent the sidewall silicon of the doped N-type heavily doped layer 116 from being excessively lost in the subsequent oxidation process.
Optionally, by controlling the thickness of the N-type heavily doped layer 116 to be in a range of 100 angstroms to 1000 angstroms, silicon oxide in the thermal oxidation process can be completely converted and can be attached to the surface of silicon on the sidewall of the deep trench isolation structure, so as to reduce the oxidation loss of the doped silicon.
Step S5, using the second silicon oxide layer as a mask layer to etch the first trench to a target depth below the P-type substrate, forming a second trench, and performing boron ion implantation on the P-type substrate at the bottom of the second trench, thereby forming a P-type doped region.
Referring to fig. 7, a schematic cross-sectional view of the second trench 207 and the P-type doped region 111 formed in step S5 is shown. The etching process in step S5 is a second-stage etching of the trench corresponding to the deep trench isolation structure, where the second-stage etching is to continuously etch the first trench 206 formed by the first-stage etching down to a target depth to form a second trench 207.
Step S6, performing thermal oxidation treatment on the polysilicon on the sidewall and the bottom of the second trench to convert the polysilicon on the sidewall and the bottom of the second trench into silicon oxide, where the silicon oxide converted on the sidewall and the bottom of the second trench and the silicon oxide converted on the polysilicon layer constitute a third silicon oxide layer.
Step S7, filling polysilicon in the second trench to form a deep trench isolation structure, and planarizing to remove the hard mask layer to form a shallow trench isolation structure.
Referring to fig. 8, a cross-sectional schematic view of the resulting device containing deep trench isolation structures (shown in dashed lines in fig. 8) is shown. Exemplarily, as shown in fig. 8, in step S7, the silicon of the lower half portion of the second trench 207 is thermally oxidized, the formed silicon oxide forms the third silicon oxide layer 110 with the silicon oxide 1101 formed in step S4, and the upper half portion of the third silicon oxide layer 110 is thicker than the lower half portion thereof since the upper half portion of the deep trench isolation structure is subjected to the thermal oxidation process twice before and after; in step S8, the third silicon oxide layer 110 may be thickened by depositing silicon oxide, and then the polysilicon layer 107 is deposited, and the hard mask layer 120 is used as a stop layer to perform a second planarization process (e.g., a planarization process by a CMP process) to planarize the surface, remove the hard mask layer 120, and planarize the isolation dielectric layer to form the shallow trench isolation structure 115.
In summary, in the embodiment of the application, in the process of manufacturing the LDMOS device, after the first trench corresponding to the deep trench isolation structure is etched and formed, phosphorus ions are implanted into the first trench, and the N-type heavily doped layer is formed on the sidewall and the bottom of the first trench, and can lead out the N-type buried region in contact with the N-type heavily doped layer, so that it is not necessary to spend a long time on high temperature thermal propulsion to diffuse the deep N-type well and contact the N-type buried layer for leading out when the deep N-type well is formed, thereby reducing the processing time of high temperature thermal propulsion and reducing the manufacturing cost; meanwhile, due to the fact that high-temperature thermal propulsion time is shortened, further upward diffusion of the N-type buried layer is prevented, breakdown voltage in a longitudinal structure of the device is increased, and longitudinal voltage-resisting capacity is improved.
Referring to fig. 9, which shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application, the method may be the method after step S7 in fig. 2, and the method includes:
step S8, performing ion implantation, forming a first P-type well and a first N-type well in the P-type epitaxial layer of the first region, forming a second N-type well in the P-type epitaxial layer of the second region, forming a third N-type well in the P-type epitaxial layer of the third region, forming a fourth N-type well and a second P-type well in the P-type epitaxial layer of the fourth region, and contacting the first N-type well and the fourth N-type well with the N-type heavily doped layer, respectively.
Referring to fig. 8, by ion implantation, a first P-type well 1031 and a first N-type well 1041 are formed in the P-type epitaxial layer 102 of the first region 201, a second N-type well 1042 is formed in the P-type epitaxial layer 102 of the second region 202, a third N-type well 1043 is formed in the P-type epitaxial layer 102 of the third region 203, and a fourth N-type well 1044 and a second P-type well 1032 are formed in the P-type epitaxial layer 102 of the fourth region 204, wherein the first N-type well 1041 is in contact with the N-type heavily doped layer 116 in the first region 201, and the fourth N-type well 1044 is in contact with the N-type heavily doped layer 116 in the fourth region 204.
Step S9, performing ion implantation to form a first P-type heavily doped region in the first P-type well, a first N-type heavily doped region in the first N-type well, a second N-type heavily doped region in the second N-type well, a third N-type heavily doped region in the third N-type well, a fourth N-type heavily doped region in the fourth N-type well, and a second P-type heavily doped region in the second P-type well.
Referring to fig. 9, by ion implantation, a first P-type heavily doped region 1091 is formed in the first P-type well 1031, a first N-type heavily doped region 1081 is formed in the first N-type well 1041, a second N-type heavily doped region 1082 is formed in the second N-type well 1042, a third N-type heavily doped region 1083 is formed in the third N-type well 1043, a fourth N-type heavily doped region 1084 is formed in the fourth N-type well 1044, and a second P-type heavily doped region 1092 is formed in the second P-type well 1032.
In step S10, an interlayer dielectric layer is formed on the P-type epitaxial layer and the shallow trench isolation layer.
Referring to fig. 10, a cross-sectional view of an isolation structure of an LDMOS device formed after a subsequent process from step S10 to step S13 is shown. Illustratively, as shown in fig. 10, the interlayer dielectric layer 114 comprises a low dielectric constant (dielectric constant is lower than 4) material (e.g., silicon dioxide), and the interlayer dielectric layer 114 may be formed on the P-type epitaxial layer 102 and the shallow trench isolation layer 115 by a CVD process. Optionally, the first region 201 and the fourth region 204 are low-voltage device regions, and the second region 202 and the third region 203 are high-voltage device regions.
Step S11, through holes are formed in the interlayer dielectric layer in an etching mode, and the through holes respectively enable the first P-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, the fourth N-type heavily doped region and the second P-type heavily doped region to be exposed.
Illustratively, a plurality of through holes may be formed in the interlayer dielectric layer by etching through a photolithography process, and each through hole of the plurality of through holes exposes a partial region of the first P-type heavily doped region 1091, the first N-type heavily doped region 1081, the second N-type heavily doped region 1082, the third N-type heavily doped region 1083, the fourth N-type heavily doped region 1084, and the second P-type heavily doped region 1092, respectively, so as to facilitate extraction.
In step S12, the via hole is filled with a metal layer, and the metal layer is planarized to form a contact via hole.
Illustratively, as shown in fig. 10, the via hole may be filled with a metal layer by electroplating (e.g., electroplating metal copper) or CVD (e.g., CVD depositing metal tungsten), and the contact via hole 112 may be formed by planarizing the metal layer by CMP.
Step S13, forming a lead on each contact via, the contact vias connected to the first P-type heavily doped region and the first N-type heavily doped region being connected to the same lead, and the contact vias connected to the second P-type heavily doped region and the fourth N-type heavily doped region being connected to the same lead.
For example, as shown in fig. 10, after a metal (e.g., aluminum metal or copper metal) layer is deposited on the interlayer dielectric layer 114 and the contact via by a Physical Vapor Deposition (PVD) process, the metal layer is etched by a photolithography process to form a lead 113, wherein the contact via 112 respectively connected to the first P-type heavily doped region 1091 and the first N-type heavily doped region 1081 is connected to the same lead 113, and the contact via 112 respectively connected to the second P-type heavily doped region 1092 and the fourth N-type heavily doped region 1084 is connected to the same lead 113.
Referring to fig. 8, which shows a cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application, the device being fabricated by the above-described method embodiment, as shown in fig. 8, the device including a deep trench isolation structure (shown in dashed lines in fig. 8), the device comprising:
the P-type substrate 101 sequentially comprises a first region 201, a second region 202, a third region 203 and a fourth region 204 along the length direction of the cross section of the P-type substrate 101, and an N-type buried layer 106 is formed in the P-type substrate 101 of the second region 202 and the third region 203.
The P-type epitaxial layer 102 and the P-type epitaxial layer 102 are formed on the P-type substrate 101, a shallow trench isolation structure 115 is formed in the P-type epitaxial layer 102 of each region, a deep N-type well 105 is formed in the P-type epitaxial layer 102 of the second region 202 and the third region 203, and the deep N-type well 105 is not in contact with the N-type buried layer 106.
Deep trench isolation structures (shown by dotted lines in fig. 8) are formed between the P-type epitaxial layers 102 of the first region 201 and the second region 202, between the P-type epitaxial layers 102 of the second region 202 and the third region 203, and between the P-type epitaxial layers 102 of the third region 203 and the fourth region 204, N-type heavily doped layers 116 are formed in the P-type epitaxial layers 102 on the peripheral sides of the deep trench isolation structures, the N-type heavily doped layers 116 of the second region 202 and the third region 203 are respectively in contact with the N-type buried layer 106 and the deep N-type well 105, the outermost layer of the deep trench isolation structures includes a third silicon oxide layer 110, the third silicon oxide layer 110 is filled with polysilicon 107, and a bottom P-type doped region 111 is formed in the P-type substrate 101 in contact with the bottom of the deep trench isolation structures.
A first P-type well 1031 and a first N-type well 1041 are formed in the P-type epitaxial layer 102 of the first region 201, a first P-type heavily doped region 1091 is formed in the first P-type well 1031, a first N-type heavily doped region 1081 is formed in the first N-type well 1041, and the first N-type well 1041 is in contact with the N-type heavily doped layer 116.
A second N-type well 1042 is formed in the P-type epitaxial layer 102 of the second region 202, and a second heavily N-doped region 1082 is formed in the second N-type well 1042.
A third N-type well 1043 is formed in the P-type epitaxial layer 102 of the third region 203, and a third heavily doped N-type region 1083 is formed in the third N-type well 1043.
A fourth N-type well 1044 and a second P-type well 1032 are formed in the P-type epitaxial layer 102 of the fourth region 204, a fourth heavily doped N-type region 1084 is formed in the fourth N-type well 1044, the fourth N-type well 1044 is in contact with the heavily doped N-type layer 116, and a second heavily doped P-type region 1092 is formed in the second P-type well 1032.
Referring to fig. 10, which shows a cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present application, the device may be fabricated by the above-described method embodiment, as shown in fig. 10, which differs from the device of the embodiment of fig. 8 in that:
an interlayer dielectric layer 114 is formed on the P-type epitaxial layer 102, contact through holes 112 are formed in the interlayer dielectric layer 114, and the bottom end of each contact through hole 112 is connected with the first P-type heavily doped region 1091, the first N-type heavily doped region 1081, the second N-type heavily doped region 1082, the third N-type heavily doped region 1083, the fourth N-type heavily doped region 1084 and the second P-type heavily doped region 1092 respectively.
A lead 113 is formed on each contact via 112, the contact vias 112 connected to the first P type heavily doped region 1091 and the first N type heavily doped region 1081 are connected to the same lead 113, and the contact vias 112 connected to the second P type heavily doped region 1092 and the fourth N type heavily doped region 1084 are connected to the same lead 113.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (15)

1. A preparation method of a deep trench isolation structure is applied to a manufacturing process of an LDMOS device, and comprises the following steps:
providing a P-type substrate, sequentially comprising a first region, a second region, a third region and a fourth region along the length direction of the cross section of the P-type substrate, wherein N-type buried layers are formed in the P-type substrate of the second region and the P-type substrate of the third region, a P-type epitaxial layer is formed on the P-type substrate, deep N-type wells are formed in the P-type epitaxial layers of the second region and the third region, a first silicon oxide layer and a hard mask layer are sequentially formed on the P-type epitaxial layer, an isolation medium layer is formed in the P-type epitaxial layer of each region, a second silicon oxide layer is formed on the hard mask layer, and the deep N-type wells are not in contact with the N-type buried layers;
etching to form a first groove, exposing the P-type substrate at the bottom of the first groove, performing phosphorus ion implantation on the first groove by taking the second silicon oxide layer as a shielding layer, forming N-type heavily doped layers on the side wall and the bottom of the first groove, and enabling the N-type heavily doped layers of the second region and the third region to be in contact with the N-type buried layer and the deep N-type well;
forming a polysilicon layer on the side wall and the bottom of the first groove;
carrying out thermal oxidation treatment on the polycrystalline silicon layer to convert the polycrystalline silicon layer into silicon oxide, and etching the silicon oxide to expose the P-type substrate at the bottom of the first trench;
etching the first groove to a target depth below the P-type substrate by taking the second silicon oxide layer as a mask layer to form a second groove, and implanting boron ions into the P-type substrate at the bottom of the second groove to form a bottom P-type doped region;
performing thermal oxidation treatment on the polycrystalline silicon on the side wall and the bottom of the second trench to convert the polycrystalline silicon on the side wall and the bottom of the second trench into silicon oxide, wherein the silicon oxide converted on the side wall and the bottom of the second trench and the silicon oxide converted on the polycrystalline silicon layer form a third silicon oxide layer;
and filling polysilicon in the second trench to form the deep trench isolation structure, and flattening to remove the hard mask layer to form the shallow trench isolation structure.
2. The method of claim 1, wherein during the phosphorus ion implantation of the first trench by using the second silicon oxide layer as the shielding layer, an energy of the phosphorus ion implantation ranges from 15 kEV to 75 kEV.
3. The method of claim 2, wherein a dose of phosphorus ions during the phosphorus ion implantation of the first trench using the second silicon oxide layer as the shielding layer is in a range of 1 × 10145 × 10 per square centimeter14Per square centimeter.
4. The method of claim 3, wherein during the phosphorus ion implantation of the first trench by using the second silicon oxide layer as the shielding layer, an angle of the phosphorus ion implantation ranges from 7 degrees to 45 degrees.
5. The method of claim 1, wherein forming a polysilicon layer on sidewalls and a bottom of the first trench comprises:
depositing and forming the polycrystalline silicon layer on the side wall and the bottom of the first groove through a CVD (chemical vapor deposition) process; or, forming the polysilicon layer on the side wall and the bottom of the first trench by a silicon epitaxial process.
6. The method of claim 1, wherein an angle of phosphorus ion implantation is 0 degree during the phosphorus ion implantation of the first trench with the second silicon oxide layer as the shielding layer.
7. The method of claim 1, wherein after the thermal oxidation treatment of the P-type substrate at the bottom of the second trench and before the second trench is filled with polysilicon, further comprising:
depositing silicon oxide in the second trench.
8. The method of any of claims 1 to 7, wherein before the etching to form the first trench, further comprising:
carrying out antimony ion implantation on the P-type substrate, and carrying out high-temperature thermal propulsion to form the N-type buried layer in the P-type substrate;
carrying out epitaxial growth on the P-type substrate to form the P-type epitaxial layer;
performing high-energy phosphorus ion implantation on the P-type epitaxial layer, and performing high-temperature thermal propulsion to form the deep N-type well in the P-type epitaxial layer;
sequentially forming a fourth silicon oxide layer and a hard mask layer on the P-type epitaxial layer;
etching and forming a third groove between each region, and exposing the P-type epitaxial layer at the bottom of the third groove;
and forming the second silicon oxide layer in the exposed P-type epitaxial layer, filling a fifth silicon oxide layer in the first groove to form the isolation medium layer, and forming the second silicon oxide layer on the third silicon oxide layer and the hard mask layer.
9. The method of claim 8, wherein after the planarizing removes the hard mask layer, further comprising:
performing ion implantation, and forming a first P-type well and a first N-type well in the P-type epitaxial layer of the first region; forming a second N-type well in the P-type epitaxial layer of the second region, forming a third N-type well in the P-type epitaxial layer of the third region, forming a fourth N-type well and a second P-type well in the P-type epitaxial layer of the fourth region, wherein the first N-type well and the fourth N-type well are respectively in contact with the N-type heavily doped layer;
and carrying out ion implantation, forming a first P-type heavily doped region in the first P-type well, forming a first N-type heavily doped region in the first N-type well, forming a second N-type heavily doped region in the second N-type well, forming a third N-type heavily doped region in the third N-type well, forming a fourth N-type heavily doped region in the fourth N-type well, and forming a second P-type heavily doped region in the second P-type well.
10. The method of claim 9, further comprising, after said performing ion implantation:
forming an interlayer dielectric layer on the P-type epitaxial layer and the shallow trench isolation layer;
etching through holes in the interlayer dielectric layer, wherein the through holes respectively expose the first P-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, the fourth N-type heavily doped region and the second P-type heavily doped region;
filling a metal layer in the through hole, and carrying out planarization treatment on the metal layer to form a contact through hole;
and a lead is formed on each contact through hole, the contact through holes connected with the first P-type heavily doped region and the first N-type heavily doped region are connected with the same lead, and the contact through holes connected with the second P-type heavily doped region and the fourth N-type heavily doped region are connected with the same lead.
11. The method of claim 10, wherein planarizing the metal layer to form contact vias comprises:
and carrying out planarization treatment on the metal layer through a CMP (chemical mechanical polishing) process to form the contact through hole.
12. The method according to any one of claims 1 to 7, wherein the thickness of the N-type heavily doped layer ranges from 100 angstroms to 1000 angstroms.
13. The method of any of claims 1 to 7, wherein the hard mask layer comprises silicon nitride.
14. A semiconductor device, comprising:
the P-type substrate sequentially comprises a first region, a second region, a third region and a fourth region along the length direction of the cross section of the P-type substrate, and N-type buried layers are formed in the P-type substrate of the second region and the P-type substrate of the third region;
the P-type epitaxial layer is formed on the P-type substrate, a shallow trench isolation structure is formed in the P-type epitaxial layer of each region, deep N-type wells are formed in the P-type epitaxial layers of the second region and the third region, and the deep N-type wells are not in contact with the N-type buried layer;
the P-type epitaxial layers of the first region and the second region, the P-type epitaxial layers of the second region and the third region and the P-type epitaxial layers of the third region and the fourth region are formed with deep trench isolation structures, N-type heavily doped layers are formed in the P-type epitaxial layers on the peripheral sides of the deep trench isolation structures, the N-type heavily doped layers of the second region and the third region are in contact with the N-type buried layer and the deep N-type well, the outermost layer of the deep trench isolation structures comprises a third silicon oxide layer, polysilicon is filled in the third silicon oxide layer, and a bottom P-type doped region is formed in a P-type substrate in contact with the bottoms of the deep trench isolation structures;
a first P-type well and a first N-type well are formed in a P-type epitaxial layer of the first region, a first P-type heavily doped region is formed in the first P-type well, a first N-type heavily doped region is formed in the first N-type well, and the first N-type well is in contact with the N-type heavily doped region;
a second N-type well is formed in the P-type epitaxial layer of the second region, and a second N-type heavily doped region is formed in the second N-type well;
a third N-type well is formed in the P-type epitaxial layer of the third region, and a third N-type heavily doped region is formed in the third N-type well;
and a fourth N-type well and a second P-type well are formed in the P-type epitaxial layer of the fourth region, a fourth N-type heavily doped region is formed in the fourth N-type well, the fourth N-type well is in contact with the N-type heavily doped layer, and a second P-type heavily doped region is formed in the second P-type well.
15. The device of claim 14, wherein an interlayer dielectric layer is formed on the P-type epitaxial layer;
a contact through hole is formed in the interlayer dielectric layer, and the bottom end of the contact through hole is respectively connected with the first P-type heavily doped region, the first N-type heavily doped region, the second N-type heavily doped region, the third N-type heavily doped region, the fourth N-type heavily doped region and the second P-type heavily doped region;
and a lead is formed on each contact through hole, the contact through holes connected with the first P-type heavily doped region and the first N-type heavily doped region are connected with the same lead, and the contact through holes connected with the second P-type heavily doped region and the fourth N-type heavily doped region are connected with the same lead.
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