CN117542889A - Laterally diffused metal oxide semiconductor device and method of manufacturing the same - Google Patents

Laterally diffused metal oxide semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
CN117542889A
CN117542889A CN202311413777.6A CN202311413777A CN117542889A CN 117542889 A CN117542889 A CN 117542889A CN 202311413777 A CN202311413777 A CN 202311413777A CN 117542889 A CN117542889 A CN 117542889A
Authority
CN
China
Prior art keywords
region
layer
doping type
forming
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311413777.6A
Other languages
Chinese (zh)
Inventor
姚国亮
吴涛
孙样慧
陈洪雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Shilan Jixin Microelectronics Co ltd
Hangzhou Silan Microelectronics Co Ltd
Original Assignee
Hangzhou Shilan Jixin Microelectronics Co ltd
Hangzhou Silan Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Shilan Jixin Microelectronics Co ltd, Hangzhou Silan Microelectronics Co Ltd filed Critical Hangzhou Shilan Jixin Microelectronics Co ltd
Priority to CN202311413777.6A priority Critical patent/CN117542889A/en
Publication of CN117542889A publication Critical patent/CN117542889A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present disclosure provides a lateral diffusion metal oxide semiconductor device and a method of manufacturing the same, the lateral diffusion metal oxide semiconductor device including: a substrate; the epitaxial layer is of a first doping type and is positioned on the substrate; the first drift region is of a second doping type and is positioned in the epitaxial layer, and the first doping type is opposite to the second doping type; and the field oxide layer is at least partially positioned above the first drift region, and the edge of the field oxide layer is a beak, wherein the doping concentration of the first drift region positioned below the field oxide layer is greater than that of the first drift region at the beak. The first drift region is formed before the field oxide layer is formed, so that the first drift region is provided with the concentration distribution that the doping concentration below the field oxide layer is larger than that at the beak, the electric field at the beak in the lateral diffusion metal oxide semiconductor device can be remarkably reduced, and the HCI reliability is improved.

Description

Laterally diffused metal oxide semiconductor device and method of manufacturing the same
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a lateral diffusion metal oxide semiconductor device and a manufacturing method thereof.
Background
BCD (Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor) technology is generally classified into high voltage BCD, high density BCD and high power BCD according to industry standards. Different BCD processes can continue to be subdivided according to different voltage rules, wherein BCD processes with voltage specifications of 45V-100V are widely used for development and manufacture of DC-DC power supplies and motor drive products.
In the BCD process, an LDMOS (Laterally Diffused Metal Oxide Semiconductor, lateral diffusion metal oxide semiconductor) device is a power device with electrodes on the surface of a silicon wafer, has good compatibility with a Bipolar process and a CMOS process, has high voltage resistance and high current output capacity, and is an important device in the BCD process.
For products with the voltage specification of 45V-100V, the smaller the specific on-resistance of the LDMOS device is, the lower the output loss is under the high-power application scene. The LDMOS device with the voltage specification needs to handle various complicated working conditions in application, has strict requirements on a safe working area, and is a troublesome problem of HCI (Hot Carrier Injection ) degradation.
Based on the demands for high performance and high reliability devices and processes, a new ldmos device and a method for manufacturing the same are needed to effectively solve the above-mentioned technical problems.
Disclosure of Invention
In view of the foregoing, it is an object of the present disclosure to provide a laterally diffused metal oxide semiconductor device and a method for fabricating the same, so as to achieve the purpose of optimizing HCI characteristics of an LDMOS device while reducing the specific on-resistance of the LDMOS device.
According to a first aspect of the present disclosure, there is provided a laterally diffused metal oxide semiconductor device comprising:
a substrate;
the epitaxial layer is of a first doping type and is positioned on the substrate;
the first drift region is of a second doping type and is positioned in the epitaxial layer, and the first doping type is opposite to the second doping type;
the field oxide layer is at least partially positioned above the first drift region, the edge of the field oxide layer is a beak,
wherein the doping concentration of the first drift region below the field oxide layer is greater than the doping concentration of the first drift region at the beak.
Optionally, the method further comprises:
and the second drift region is of a first doping type, is positioned in the epitaxial layer and is positioned below the first drift region, and the first drift region and the second drift region form a RESURF structure.
Optionally, the method further comprises:
the isolation structure is partially or completely located in the epitaxial layer, the isolation structure is annular, and the first drift region is located on the inner side of the isolation structure.
Optionally, the method further comprises:
the first buried layer is of a second doping type, is located in the substrate and located on the inner side of the isolation structure, and the epitaxial layer is located on the substrate and the first buried layer.
Optionally, the method further comprises:
the body region is of a first doping type and is positioned in the first drift region;
the source ohmic contact region is a first doped region positioned in the body region;
the source electrode ohmic contact area is electrically connected with the body region ohmic contact area;
the drain ohmic contact region is a first doped region in the epitaxial layer positioned on the inner side of the isolation structure, wherein the first doped region is of a second doped type, and the second doped region is of a first doped type;
the gate oxide layer is positioned on the surface of the active region between the source ohmic contact region and the drain ohmic contact region; and
and the gate conductor is positioned on the surface of the gate oxide layer and extends to part of the surface of the field oxide layer.
Optionally, the method further comprises:
the first well region is of a second doping type, is positioned in the epitaxial layer inside the isolation structure and is adjacent to the first drift region;
The second well region is of a first doping type and is positioned on one side, far away from the first well region, of the first drift region, and the body region is positioned in the second well region and the first drift region;
and the third well region is of a second doping type and is positioned in the first well region, and the drain ohmic contact region is positioned in the third well region.
Optionally, the method further comprises:
the second well region is positioned in the epitaxial layer outside the isolation structure and is of a first doping type; and
and the second doping region is positioned in a second well region in the epitaxial layer outside the isolation structure so as to draw out the potential of the substrate, and the second doping region is of the first doping type.
Optionally, the source ohmic contact region is located between two of the drain ohmic contact regions or the drain ohmic contact region is located between two of the source ohmic contact regions.
Optionally, the isolation structure is an isolation trench, and the isolation trench includes:
a trench penetrating the epitaxial layer and reaching the substrate;
the first dielectric layer covers the side wall and the bottom of the groove; and
and the polysilicon layer is positioned on the first dielectric layer and fills the groove.
Optionally, the method further comprises:
the second buried layer is of the first doping type and is located in the substrate at the bottom of the groove.
Optionally, the substrate is an SOI substrate, the SOI substrate includes an insulating layer therein, the epitaxial layer is formed on the insulating layer, and the isolation trench extends into the insulating layer.
Optionally, the isolation structure is an isolation junction, the isolation junction comprising:
the first well region is of a second doping type, is positioned in the epitaxial layer, is positioned above the first buried layer and is in contact with the first buried layer;
the third well region is of a second doping type and is positioned in the first well region; and
the first doping region is of a second doping type and is located in the third well region.
Optionally, the method further comprises:
the pad oxide layer is positioned on the surface of the epitaxial layer and covers the surface of the active region;
the second dielectric layer is positioned on the surfaces of the field oxide layer, the pad oxide layer and the gate conductor;
a via penetrating at least the second dielectric layer to the first doped region, the second doped region, and the gate conductor;
and the metal layer fills the through hole and extends to part of the surface of the second dielectric layer to form an electrode.
Optionally, the lateral diffusion metal oxide semiconductor device has a voltage range of 25V to 120V.
According to another aspect of the present disclosure, there is provided a method of manufacturing a lateral diffusion metal oxide semiconductor device, including:
forming an epitaxial layer of a first doping type on a substrate;
forming a first drift region of a second doping type in the epitaxial layer, wherein the first doping type is opposite to the second doping type;
forming a field oxide layer, wherein at least part of the field oxide layer is positioned above the first drift region, the edge of the field oxide layer is a beak,
wherein the doping concentration of the first drift region below the field oxide layer is greater than the doping concentration of the first drift region at the beak.
Optionally, forming the first drift region of the second doping type in the epitaxial layer includes:
forming a pad oxide layer on the surface of the epitaxial layer;
forming a patterned silicon nitride layer on the surface of the pad oxide layer;
forming a first photoresist on a part of the silicon nitride layer and a part of the pad oxide layer;
and implanting ions of a second doping type at least once by taking the first photoresist and the silicon nitride layer as masks to form the first drift region in the epitaxial layer.
Optionally, the method further comprises:
and implanting first doping type ions once by taking the first photoresist and the silicon nitride layer as masks to form a second drift region of a first doping type which is positioned in the epitaxial layer and below the first drift region, wherein the first drift region and the second drift region form a RESURF structure.
Optionally, the method further comprises:
and forming an isolation structure which is partially or completely positioned in the epitaxial layer, wherein the isolation structure is annular, and the first drift region is positioned on the inner side of the isolation structure.
Optionally, the method further comprises:
and forming a first buried layer of a second doping type in the substrate, wherein the first buried layer is positioned on the inner side of the isolation structure, and the epitaxial layer is positioned on the substrate and the first buried layer.
Optionally, the method further comprises:
forming a body region of a first doping type in the first drift region by taking the second photoresist as a mask;
forming a first doped region in the body region to serve as a source ohmic contact region;
forming a second doped region in the body region to serve as a body region ohmic contact region, wherein the source ohmic contact region is electrically connected with the body region ohmic contact region;
forming a first doping region in the epitaxial layer to serve as a drain ohmic contact region, wherein the drain ohmic contact region is located on the inner side of the isolation structure, the first doping region is of a second doping type, and the second doping region is of a first doping type;
Forming a gate oxide layer on the surface of the active region between the source ohmic contact region and the drain ohmic contact region by using the second photoresist as a mask; and
and forming a gate conductor which is positioned on the surface of the gate oxide layer and extends to part of the surface of the field oxide layer.
Optionally, the method further comprises:
forming a first well region of a second doping type adjacent to the first drift region in the epitaxial layer, wherein the first well region is positioned on the inner side of the isolation structure;
forming a second well region of a first doping type on one side of the first drift region away from the first well region, wherein the body region is positioned in the second well region and the first drift region;
and forming a third well region with a second doping type in the first well region, wherein the drain ohmic contact region is positioned in the third well region.
Optionally, the method further comprises:
forming a second well region in the epitaxial layer outside the isolation structure, wherein the second well region is of a first doping type; and
and forming a second doped region in a second well region in the epitaxial layer outside the isolation structure to draw out the potential of the substrate, wherein the second doped region is of the first doping type.
Optionally, the source ohmic contact region is located between two of the drain ohmic contact regions or the drain ohmic contact region is located between two of the source ohmic contact regions.
Optionally, the isolation structure is an isolation trench, and forming the isolation structure partially or completely in the epitaxial layer includes:
forming a trench penetrating the epitaxial layer and reaching into the substrate;
forming a first dielectric layer which covers the side wall and the bottom of the groove and is positioned on the surface of the epitaxial layer;
filling a polysilicon layer in the groove, wherein the polysilicon layer is positioned on the first dielectric layer; and
and removing part of the first dielectric layer positioned on the surface of the epitaxial layer.
Optionally, before removing a portion of the first dielectric layer located on the surface of the epitaxial layer, the method further includes:
forming a protective layer on the surface of the polycrystalline silicon layer and part of the surface of the first dielectric layer, wherein the protective layer is a photoresist layer; and
and removing the first dielectric layer exposed to the outside by the protective layer, and removing the protective layer.
Optionally, the method further comprises:
and forming a second buried layer of the first doping type in the substrate at the bottom of the groove.
Optionally, the substrate is an SOI substrate, the SOI substrate includes an insulating layer therein, the epitaxial layer is formed on the insulating layer, and the isolation trench extends into the insulating layer.
Optionally, the isolation structure is an isolation junction, and forming the isolation structure partially or completely in the epitaxial layer includes:
forming a first well region of a second doping type above and in contact with the first buried layer in the epitaxial layer;
forming a third well region of a second doping type in the first well region; and
and a first doped region of a second doping type formed in the third well region.
Optionally, the method further comprises:
forming a pad oxide layer covering the surface of the active region on the surface of the epitaxial layer;
forming a second dielectric layer on the surfaces of the field oxide layer, the pad oxide layer and the gate conductor;
forming a through hole penetrating at least the second dielectric layer to reach the first doped region, the second doped region and the gate conductor;
and forming a metal layer which fills the through hole and extends to part of the surface of the second dielectric layer to form an electrode.
Optionally, implanting ions of a second doping type three times by taking the first photoresist and the silicon nitride layer as masks to form the first drift region in the epitaxial layer, wherein the implantation energy of the first ion implantation is 10-150 keV, the implantation energy of the second ion implantation is 250-450 keV, and the implantation energy of the third ion implantation is 600-1000 keV.
According to the lateral diffusion metal oxide semiconductor device and the manufacturing method thereof, the first drift region is formed before the field oxide layer is formed, so that the first drift region is provided with the concentration distribution that the doping concentration below the field oxide layer is larger than that at the beak, the electric field intensity at the beak in the LDMOS device is obviously reduced while the specific on-resistance is reduced, and the HCI reliability is improved.
Further, the present disclosure implants at least one second doping type ion with the first photoresist and the silicon nitride layer as a mask to form a first drift region in the epitaxial layer, and implants one first doping type ion with the first photoresist and the silicon nitride layer as a mask to form a second drift region of the first doping type in the epitaxial layer and below the first drift region. Namely, the first drift region and the second drift region can be formed by only one photoetching plate, so that the manufacturing cost is reduced, and the pressure resistance of the lateral diffusion metal oxide semiconductor device is improved.
Further, the drain ohmic contact region in the present disclosure can lead out the potential of the first buried layer at the same time, because the thermal process of the first well region in contact with the first buried layer is much, the concentration distribution is more gentle, and the depletion of the drift region is not affected.
Further, after the photoresist mask of the body region is formed, the gate conductor which is not covered by the photoresist mask of the body region is etched first, so that when the body region is injected, alignment deviation between the photoresist and the gate conductor does not exist, and the dispersion of the starting threshold voltage of the LDMOS device is small.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a first embodiment of the present disclosure;
fig. 2 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a second embodiment of the present disclosure;
fig. 3 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a third embodiment of the present disclosure;
fig. 4 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a fourth embodiment of the present disclosure;
fig. 5 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a fifth embodiment of the present disclosure;
fig. 6 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a sixth embodiment of the present disclosure;
Fig. 7 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a seventh embodiment of the present disclosure;
fig. 8 shows a flow diagram of a method of fabricating a laterally diffused metal oxide semiconductor device provided in accordance with a first embodiment of the present disclosure;
fig. 9 a-9 u illustrate schematic cross-sectional views of a laterally diffused metal oxide semiconductor device provided in accordance with a first embodiment of the present disclosure during various fabrication processes;
fig. 10 is a schematic flow chart of step S204 in the method for manufacturing a lateral diffusion metal oxide semiconductor device according to the first embodiment of the present disclosure;
fig. 11a shows a schematic doping concentration distribution diagram of a first drift region located in different regions in a laterally diffused metal oxide semiconductor device according to an embodiment of the present disclosure;
fig. 11b shows a schematic diagram of electric field intensity distribution of a first drift region located in different regions in a laterally diffused metal oxide semiconductor device according to an embodiment of the present disclosure.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples.
Fig. 1 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a first embodiment of the present disclosure. It should be noted that fig. 1 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary in fig. 1. As shown in fig. 1, the present embodiment provides an HS-LDMOS device (high-side-lateral diffusion metal oxide semiconductor device), further comprising: a substrate 101 of a first doping type, an epitaxial layer 103 of the first doping type on the substrate 101, a first drift region 117 of a second doping type in the epitaxial layer 103, a field oxide layer 118 (LOCOS, local Oxidation of Silicon, local oxidation of silicon) at least partially above the first drift region 117. Further, a field oxide layer 118 is formed on the first drift region 117 of the inactive region. The edge of the field oxide layer 118 is a bird's beak, specifically, a bird's beak is formed at the junction between the field oxide layer 118 and the active region. The doping concentration of the first drift region 117 located under the field oxide layer 118 is greater than the doping concentration of the first drift region 117 at the beak. Wherein the first doping type is opposite to the second doping type. Illustratively, the first doping type is P-type and the second doping type is N-type.
Further, the HS-LDMOS device also includes a second drift region 116. The second drift region 116 is of the first doping type, is located in the epitaxial layer 103 and is located below the first drift region 117. The first drift region 117 and the second drift region 116 form a RESURF structure. Illustratively, the first drift region 117 is formed via at least one ion implantation of a second doping type (e.g., phosphorus ions). Illustratively, the second drift region 116 is formed via a single implantation of first doping type ions (e.g., boron ions).
Further, the HS-LDMOS device further comprises: a first buried layer 102 of a second doping type located in the substrate 101 and below the epitaxial layer 103, a first well region 104 of a second doping type located in the epitaxial layer 103 and above the first buried layer 102 and in contact with the first buried layer 102, a third well region 120 of a second doping type located in the first well region 104, a first doped region 125 of a second doping type located in the third well region 120. Wherein the epitaxial layer 103 is located on the substrate 101 and the first buried layer 102, and the first well region 104 adjoins the first drift region 117 and the second drift region 116. The first well region 104, the third well region 120 located in the first well region 104, and the first doped region 125 located in the third well region 120 together function as a drain structure, and the first doped region 125 functions as a drain ohmic contact region.
Further, the HS-LDMOS device further comprises: a second well region 119 of the first doping type located in the first drift region 117 on the side remote from the first well region 104, a body region 124 of the first doping type located in the second well region 119 and the first drift region 117, a first doping region 125 and a second doping region 126 located in the body region 124 and in contact with each other. The first doped region 125 is of a second doping type, the second doped region 126 is of a first doping type, the first doped region 125 is a source ohmic contact region, the second doped region 126 is a body ohmic contact region, and the source ohmic contact region is in contact with the body ohmic contact region to realize electrical connection. In alternative embodiments, the first doped region 125 and the second doped region 126 may not be in contact, both of which are drawn through the metal layer and electrically connected through the same electrode. The body region 124, the first doped region 125 and the second doped region 126 located in the body region 124 and contacting each other together function as a source structure.
In other embodiments, the HS-LDMOS device may not include the first well region 104, the second well region 119, and the third well region 120, and then the body region 124 is located in the first doped region 117 and the drain ohmic contact region is located in the epitaxial layer 103.
Further, the HS-LDMOS device further includes a gate stack over the first drift region 117, the gate stack including: a gate oxide layer 121 on the surface of the active region between the source ohmic contact region and the drain ohmic contact region, and a gate conductor 122 on the surface of the gate oxide layer 121 and extending to a portion of the surface of the field oxide layer 118. Wherein the mutually adjacent sides of the gate conductor 122 and the first doped region 125 in the body region 124 are coplanar.
Further, the HS-LDMOS device further comprises an isolation structure partially or entirely located in the epitaxial layer 103, the isolation structure being annular, and the first buried layer 102, the first drift region 117, the second drift region 116 and the first well region 104 being located inside the isolation structure. Further comprises: a second well region 119 in the epitaxial layer 103 outside the isolation structure, a second doped region 126 in the second well region 119 in the epitaxial layer 103 outside the isolation structure to draw out the potential of the substrate 101. Wherein the first well region 104 and the body region 124 are formed inside the isolation structure, and the second doped region 126 in the second well region 119, which draws the potential of the substrate 101, is located outside the isolation structure. Illustratively, the source structure and the drain structure are located inside the isolation structure, and the drain ohmic contact region (drain structure) is located between the two source ohmic contact regions (source structures).
Further, the isolation structure is, for example, an isolation trench, and the isolation trench includes: a trench penetrating the epitaxial layer 103 and reaching the substrate 101, a second buried layer 107 of the first doping type in the substrate 101 at the bottom of the trench, a first dielectric layer covering the trench sidewalls and bottom, a polysilicon layer 111 on the first dielectric layer and filling the trench. Further, the first dielectric layer includes: a first oxide layer 109 located on the side wall and bottom of the trench, and a second oxide layer 110 located on the surface of the first oxide layer 109. Wherein the light transmittance of the first oxide layer 109 is different from that of the second oxide layer 110.
Further, the depth-to-width ratio of the groove is between 5:1 and 20:1. Preferably, the width of the trench is 1.0 μm to 3.0 μm, and preferably, the depth of the trench is 10 μm to 30 μm.
Further, the method further comprises the following steps: and a pad oxide layer 113 located on the surface of the epitaxial layer 103 and covering the surface of the active region. Illustratively, a portion of the field oxide 118 is located between the isolation trench and the second doped region 126, a portion is located between the isolation trench and the source ohmic contact region, and a portion is located between the gate oxide 121 and the drain ohmic contact region and is spaced apart from the source ohmic contact region. The field oxide layer 118 on both sides of the isolation trench can relieve the stress of the isolation trench and satisfy the withstand voltage.
Further, the method further comprises the following steps: the second dielectric layer 127 is located on the pad oxide layer 113, the field oxide layer 118 and the gate conductor 122, penetrates the second dielectric layer 127 and the pad oxide layer 113 to reach the first doped region 125, the through hole 128 of the second doped region 126, penetrates the second dielectric layer 127 to reach the through hole 128 of the gate conductor 122, and fills the through hole 128 and extends to a part of the surface of the second dielectric layer 127. The portions of the metal layers filled in the different through holes 128 extending to the surface of the second dielectric layer 127 serve as a first electrode 129, a second electrode 130 and a third electrode 131, and are not in contact with each other. Specifically, the first electrode 129 is in contact with the second doped region 126 in the second well region 119 outside the isolation structure, as a substrate electrode; the second electrode 130 contacts the first doped region 125 and the second doped region 126 in the body region 124 as a source electrode; the third electrode 131 contacts the first doped region 125 in the third well region 120 as a drain electrode. Further, a fourth electrode (not shown) in contact with the gate conductor 122 is also included as a gate electrode. The isolation structure isolates the substrate electrode from the gate electrode, the source electrode, and the drain electrode.
Fig. 2 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a second embodiment of the present disclosure. It should be noted that fig. 2 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary in fig. 2.
As shown in fig. 2, the present embodiment provides an LS-LDMOS (low-side-lateral diffusion metal oxide semiconductor device). The difference between the second embodiment and the first embodiment is that the second embodiment does not include the first buried layer 102, the epitaxial layer 103 is located on the substrate, and other structures are the same as those of the first embodiment, and will not be described herein.
Fig. 3 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a third embodiment of the present disclosure. It should be noted that fig. 3 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary in fig. 3.
As shown in fig. 3, the present embodiment provides an LS-LDMOS (low-side-lateral diffusion metal oxide semiconductor device). The difference between the third embodiment and the second embodiment is that the second drift region 116 is not included in the third embodiment, and other structures are the same as those in the first embodiment, and will not be described herein. It is understood that the isolation structures in the second embodiment and the third embodiment may be isolation junctions.
Fig. 4 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a fourth embodiment of the present disclosure. It should be noted that fig. 4 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary of fig. 4.
As shown in fig. 4, the present embodiment provides an LS-LDMOS (low-side-lateral diffusion metal oxide semiconductor device). The difference between the fourth embodiment and the second embodiment is that the isolation structure and the second well region 119 in the epitaxial layer 103 outside the isolation structure and the second doped region 126 in the second well region 119 are not included in the fourth embodiment, and other structures are the same as those in the second embodiment, and are not described herein.
Fig. 5 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a fifth embodiment of the present disclosure. It should be noted that fig. 5 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary in fig. 5.
As shown in fig. 5, the present embodiment provides an HS-LDMOS (high-side-lateral diffusion metal oxide semiconductor device). The difference between the fifth embodiment and the first embodiment is that the substrate 101 in the fifth embodiment is a SOI (Silicon On Insulator) substrate, the insulating layer 540 is formed in the SOI substrate, the epitaxial layer 103 is located on the insulating layer 540, and the isolation trench penetrates through the epitaxial layer 103 and enters the insulating layer 540, and other structures are the same as those in the first embodiment and will not be described herein.
Fig. 6 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a sixth embodiment of the present disclosure. It should be noted that fig. 6 only shows half of the ldmos device, and the other half is a structure mirrored along the right-most boundary of fig. 6.
As shown in fig. 6, the present embodiment provides an HS-LDMOS (high-side-lateral diffusion metal oxide semiconductor device). The difference between the sixth embodiment and the first embodiment is that the isolation structure in the sixth embodiment is an isolation junction, and the isolation junction is located in the epitaxial layer 103 and located above the first buried layer 102 and is in contact with the first buried layer 102. The isolation junction includes: a first well region 104 of a second doping type located in the epitaxial layer 103 and above the first buried layer 102 and in contact with the first buried layer 102, a third well region 120 of the second doping type located in the first well region 104, and a first doping region 125 of the second doping type located in the third well region 120. The first drift region 117, the second drift region 116, and the second well region 119 are each separated from the isolation junction. Other structures of this embodiment are the same as those of the first embodiment, and will not be described here again.
In the HS-LDMOS device described above, only the first drift region 117 may be provided, or the first drift region 117 and the second drift region 116 may be provided. The LS-LDMOS device described above is not provided with the first buried layer 102, and further, may be selectively provided or not provided with an isolation structure, and in addition, the LS-LDMOS device described above may be provided with only the first drift region 117, or may be provided with the first drift region 117 and the second drift region 116. The isolation structure in the LS-LDMOS device is not limited to the isolation trench, but can be an isolation junction or a structure in which the isolation trench is combined with the SOI substrate.
Fig. 7 shows a schematic cross-sectional view of a laterally diffused metal oxide semiconductor device provided according to a seventh embodiment of the present disclosure. It should be noted that fig. 7 only shows one half of the ldmos device, and the other half is a structure mirrored along the right-most boundary in fig. 7.
In other alternative embodiments, as shown in fig. 7, the source structure and the drain structure of the HS-LDMOS device in the seventh embodiment are located inside the isolation structure, and the source ohmic contact region (source structure) is located between the two drain ohmic contact regions (drain structures).
Note that the difference between the first embodiment and the seventh embodiment is that the positions of the entire source structure and the drain structure are interchanged. The lateral diffusion metal oxide semiconductor device provided in the first embodiment has the drain structure between two source structures, and has the main advantage of relatively simple structure, and is generally used for LDMOS devices with high voltage levels (65V-120V). The source structure of the LDMOS device provided in the seventh embodiment is located between two drain structures, and has the main advantage that the pitch (the distance from the center point of the source ohmic contact region to the center point of the drain ohmic contact region) of the LDMOS device is smaller, and in the finger structure, the drain structures can be regularly arranged according to the minimum active region, so that the cost can be reduced, and the LDMOS device is generally used for LDMOS devices with low voltage levels (25V to 65V).
Note that the positional relationship of the source structure and the drain structure in each of the second to sixth embodiments may be set in the manner of the seventh embodiment.
Fig. 8 shows a flow chart of a method of manufacturing a laterally diffused metal oxide semiconductor device according to a first embodiment of the present disclosure. Fig. 9 a-9 u illustrate schematic cross-sectional views of a laterally diffused metal oxide semiconductor device provided in accordance with a first embodiment of the present disclosure during various fabrication processes. Fig. 10 is a schematic flow chart of step S204 in the method for manufacturing a lateral diffusion metal oxide semiconductor device according to the first embodiment of the present disclosure.
The method for manufacturing a laterally diffused metal oxide semiconductor device according to the present embodiment may prepare the above-described various laterally diffused metal oxide semiconductor devices, and the method for manufacturing a laterally diffused metal oxide semiconductor device will be specifically described below with reference to the laterally diffused metal oxide semiconductor device according to the first embodiment as an example.
As shown in fig. 8 and 9 a-9 u, the method of manufacturing the lateral diffusion metal oxide semiconductor device includes the following steps.
In step S201, a first buried layer 102 is formed in a substrate 101. As shown in fig. 9a, a first buried layer 102 is formed in a substrate 101, for example, using photolithography, an ion implantation process, and the first buried layer 102 is activated by a push junction after formation. Wherein the push junction activation is performed by a high temperature annealing process, for example. The substrate 101 is of a first doping type and the first buried layer 102 is of a second doping type. Illustratively, the first doping type is P-type and the second doping type is N-type. The first buried layer 102 may provide isolation and floating capabilities. Note that the first buried layer 102 is not prepared during the fabrication of the LS-LDMOS device.
In step S202, an epitaxial layer 103 is formed on the substrate 101 and the first buried layer 102. As shown in fig. 9b, an epitaxial layer 103 is deposited on the substrate 101 and on the first buried layer 102 by an epitaxial process, the thickness of the epitaxial layer 103 being, for example, 5 μm to 10 μm. Epitaxial layer 103 is of a first doping type. Among them, the epitaxial processes include molecular beam Epitaxy (Molecular Beam Epitaxy, MBE), ultra-high vacuum chemical vapor deposition (Ultra High Vacuum Chemical Vapor Deposition, UHVCVD), atmospheric and vacuum Epitaxy (ATM & RP epi axy), and the like. Epitaxial layer 103 is, for example, a monocrystalline silicon layer.
In step S203, a first well region 104 in contact with the first buried layer 102 is formed in the epitaxial layer 103. As shown in fig. 9c, a high-voltage first well region 104 is formed in the epitaxial layer 103 by an implantation process, for extracting the potential of the first buried layer 102. The first well region 104 is of a first doping type. Wherein the first buried layer 102 is brought into contact with the first well region 104, for example by diffusion.
In step S204, isolation trenches are formed in the epitaxial layer 103 and the substrate 101. It should be noted that when the LS-LDMOS device is fabricated, isolation structures such as isolation trenches may be alternatively not fabricated. Specific manufacturing processes and structures will be described in detail below. Referring to fig. 10, step S204 includes the steps of:
In step 401, a hard mask 105 is formed over the epitaxial layer 103 and the first well region 104. As shown in fig. 9d, a hard mask 105 is deposited over the epitaxial layer 103 and the first well region 104. The hard mask 105 is, for example, a silicon oxide layer or a silicon nitride layer, and the thickness of the hard mask 105 is, for example, 0.5 μm to 1.5 μm.
In step S402, a trench is formed. As shown in fig. 9e, a photoresist 106 for etching the trench is formed by photoresist coating, photolithography. The hard mask 105 is then etched using the photoresist 106 as a mask and the epitaxial layer 103 and the substrate 101 continue to be etched to form trenches through the epitaxial layer 103 and into the substrate 101. In a preferred embodiment, the etching of the trench may be formed using a RIE (Reactive Ion Etching ) process, the aspect ratio of the trench being, for example, between 5:1 and 20:1. The width of the trench is, for example, 1.0 μm to 3.0 μm, and the depth of the trench is, for example, 10 μm to 30 μm.
In step S403, a second buried layer 107 is formed in the substrate 101 based on the patterned hard mask 105. As shown in fig. 9f, the photoresist 106 is removed first, and then a second buried layer 107 is formed by self-aligning and ion implantation of the patterned hard mask 105 at the bottom of the trench, so as to reduce the resistivity of the substrate 101 at the bottom of the trench, and achieve better isolation. Wherein the second buried layer 107 is of the first doping type.
In a preferred embodiment, step S404 is also included. In step S404, a sacrificial oxide layer 108 is formed on the trench sidewall and bottom. As shown in fig. 9g, a sacrificial oxide layer 108 is formed on the trench sidewall and bottom using a furnace tube to treat the interface defects formed by etching. The thickness of the sacrificial oxide layer 108 is, for example, 0.1 μm to 0.3 μm.
In step S405, a first dielectric layer is formed on the trench sidewall, the bottom, and the surfaces of the epitaxial layer 103 and the first well region 104, and the polysilicon layer 111 is filled in the trench. As shown in fig. 9h, the patterned hard mask 105 and sacrificial oxide layer 108 are first removed using a wet etch process. Thereafter, a furnace thermal process is used to form a first oxide layer 109 on the trench sidewalls and bottom. The thickness of the first oxide layer 109 is, for example, 0.1 μm to 0.5 μm as an interface pad oxide layer. And then a second oxide layer 110 is deposited on the surface of the first oxide layer 109, the second oxide layer 110 and the first oxide layer 109 together form a first dielectric layer on the side wall and the bottom of the trench, and the first oxide layer 109 and the second oxide layer 110 also cover the epitaxial layer 103 and the surface of the first well region 104. Wherein, the first oxide layer 109 is an oxide layer formed by thermal growth, has compact structure and good interface state, but is slow to grow; the second oxide layer 110 is formed by chemical vapor deposition or by utilizing tetraethoxysilane dehydrogenation reaction, has loose structure and high forming speed, and can relieve stress mismatch between the polysilicon layer 111 formed later and the epitaxial layer 103 and the substrate 101. The light transmittance of the first oxide layer 109 and the second oxide layer 110 is different. A polysilicon layer 111 is then deposited on the surface of the second oxide layer 110 to fill the trench and to be higher than the surface of the epitaxial layer 103. The polysilicon layer 111 is further etched so that the distance t1 of the upper surface of the polysilicon layer 111 from the surface of the epitaxial layer 103 is 0.3 μm to 0.5 μm. As shown in fig. 9i, the second oxide layer 110 and the polysilicon layer 111 are then polished together above the surface of the epitaxial layer 103, for example by a CMP (Chemical Mechanical Polishing ) process, the upper surfaces of the second oxide layer 110 and the polysilicon layer 111 being at a distance t2 from the upper surface of the epitaxial layer 103 of 0.1 μm to 0.3 μm. As shown in fig. 9j, the polysilicon layer 111 is then etched back again, for example, so that the upper surface of the polysilicon layer 111 is flush with the surface of the epitaxial layer 103.
In step S406, the protective layer 112 is formed on the surface of the polysilicon layer 111 and a portion of the surface of the first dielectric layer. As shown in fig. 9k, a photoresist coating and photolithography process is used to form a protective layer 112 on the surface of the polysilicon layer 111 and a portion of the surface of the second oxide layer 110. The protective layer 112 is, for example, a photoresist layer, and has a thickness of, for example, 0.5 μm to 1.0 μm. Wherein the use of a photoresist layer may save processing steps and optimize stress mismatch as compared to using a hard mask as the protective layer 112.
In step S407, the first dielectric layer and the protective layer 112 not covered by the protective layer 112 are removed. As shown in fig. 9l, the first oxide layer 109, the second oxide layer 110, which are not covered by the protective layer 112, are removed, for example, by a wet etching process, and then the protective layer 112 is removed.
Next, in step S205, a pad oxide layer 113 is formed on the surface of the epitaxial layer 103, the isolation trench, and the first well region 104. As shown in FIG. 9m, a thermal oxidation process is used to form an epitaxial layer 103 and isolation trenchesA pad oxide layer 113 is formed on the surface of the first well region 104, and the thickness of the pad oxide layer 113 is, for exampleNote that, since the surface of the isolation trench includes the first dielectric layer higher than the surface of the epitaxial layer 103 (fig. 9 l), the thickness of the pad oxide layer 113 formed on the surface of the isolation trench is slightly higher than the thickness of the pad oxide layer 113 located on the surface of the epitaxial layer 103 and the first well region 104 (not shown in fig. 9 m).
In step S206, a patterned silicon nitride layer 114 is formed on the surface of the pad oxide layer 113. As shown in fig. 9n, a silicon nitride layer is deposited on the surface of the pad oxide layer 113, and then the silicon nitride layer in the non-active region of the ldmos device is etched away by photolithography and etching processes to form a patterned silicon nitride layer 114, so as to expose the non-active region of the ldmos device, i.e., the silicon nitride layer 114 covers the surface of the active region.
In step S207, the first drift region 117 located in the epitaxial layer 103 is formed through at least one ion implantation. As shown in fig. 9o, a photoresist 115 for the first drift region implant is first applied, and lithographically formed. The photoresist 115 covers, for example, the first well region 104, the isolation trench, and the outside of the isolation trench. Preferably, first doping type ions (e.g., boron ions) are implanted once with the photoresist 115 and the silicon nitride layer 114 as a mask to form a second drift region 116 in the epitaxial layer 103. And implanting ions of a second doping type (e.g., phosphorus ions) at least once with the photoresist 115 and the silicon nitride layer 114 to form a first drift region 117 in the epitaxial layer 103 on the second drift region 116, the first drift region 117 and the second drift region 116 together constituting a drift region. The first drift region 117 and the second drift region 116 form a RESURF (Reduced Surface Field, surface field reduction) structure of the drift region of the LDMOS device, so that the specific on-resistance of the LDMOS device can be effectively reduced while maintaining the voltage withstand value unchanged. In other embodiments, only the first drift region 117 may be formed.
Illustratively, the first drift region 117 and the second drift region 116 are located on either side of the first well region 104. In other embodiments, the first drift region 117 and the second drift region 116 are located between the two first well regions 104. Wherein the first drift region 117 is of the second doping type and the second drift region 116 is of the first doping type. The first drift region 117 is formed by implanting, illustratively, tertiary phosphorus ions. Further, the implantation energy of the first phosphorus ion implantation is 10 to 150keV, the implantation energy of the second phosphorus ion implantation is 250 to 450keV, and the implantation energy of the third phosphorus ion implantation is 600 to 1000keV, but is not limited thereto. The first phosphorus ion implantation adopts a low-energy implantation mode, and phosphorus ions are blocked by the patterned silicon nitride layer 114 located in the active region, so that no phosphorus ion implantation is performed in the active region, and phosphorus ions are implanted in the non-active region (the region where the field oxide layer 118 is formed later) exposed by the silicon nitride layer 114. Further, the first drift region 117 formed in this embodiment has a concentration distribution in which the doping concentration below the field oxide layer 118 is greater than the doping concentration below the active region. In an alternative embodiment, the first drift region 117 is formed by a first phosphorus ion implantation as described above.
In step S208, thermal oxidation is performed to form the field oxide layer 118. As shown in fig. 9p, the photoresist 115 is first removed, and then an oxide is thermally grown based on the patterned silicon nitride layer 114 on the basis of the exposed pad oxide layer 113 to form a LOCOS (Local Oxidation of Silicon ) structure, i.e., a field oxide layer 118, the field oxide layer 118 covering the surface of the non-active region.
In step S209, a second well region 119 is formed in the first drift region. As shown in fig. 9q, the patterned silicon nitride layer 114 is removed. A low-voltage second well region 119 is then formed in the first drift region 117 using a photolithographic and implantation process, while a low-voltage second well region 119 is formed in the epitaxial layer 103 outside the isolation trench. The second well region 119 is of the first doping type, and the second well region 119 is located inside and outside the isolation trench respectively. Illustratively, a second well region 119, located inboard of the isolation trenches, is located in the first drift region 117 on a side proximate to the isolation trenches.
Further, a third well region 120 is also formed in the first well region 104 in this step. The third well region 130 is a well region having the second doping type. The third well region 120 is used to reduce on-resistance and mitigate Kirk (base stretching) effects.
In step S210, a gate stack is formed over the first drift region. As shown in fig. 9r, a gate oxide layer 121 is grown on the surface of the first drift region 117 not covered by the field oxide layer 118 by a thermal oxidation process. A layer of polysilicon is then deposited and a gate conductor 122 is formed as a gate field plate structure by doping, photolithography and etching processes on the surface of the gate oxide 121 and extending to the surface of a portion of the field oxide 118.
In step S211, a body region, a source ohmic contact region, and a drain ohmic contact region are formed. As shown in fig. 9s, photoresist 123 for body implant is first photoresist coated, lithographically formed. As shown in fig. 9t, the gate stack (including the gate conductor 122 and the gate oxide 121) exposed by the photoresist 123 is etched away with the photoresist 123 as a mask, and then the second well region 119 located in the first drift region 117 and the first drift region 117 are implanted and diffused with the photoresist 123 as a mask to form the body region 124. Body region 124 is of a first doping type. As shown in fig. 9u, the first doped region 125 and the second doped region 126 are then formed using photolithography and implantation processes. Wherein the first doped region 125 located in the body region 124 is a source ohmic contact region, the second doped region 126 is a body ohmic contact region, and the source ohmic contact region and the body ohmic contact region are in contact and electrically connected, in an alternative embodiment, the first doped region 125 and the second doped region 126 located in the body region 124 may not be in contact, both are led out through the metal layer and are electrically connected through the same electrode; the first doped region 125 located in the third well region 120 serves as a drain ohmic contact region; the second doped region 126 in the second well region 119 in the epitaxial layer 103 outside the isolation trench is used to pull out the substrate 101 potential. The first doped region 125 is of a second doping type, the second doped region 126 is of a first doping type, and the first doped region 125 and the second doped region 126 are both heavily doped regions. Wherein the mutually adjacent sides of the gate conductor 122 and the first doped region 125 in the body region 124 are coplanar.
Further, forming the second dielectric layer 127 and the electrode is also included. As shown in fig. 1, first, a second dielectric layer 127 is formed on the pad oxide 113, the field oxide 118, and the gate stack. Thereafter, a via 128 penetrating the dielectric layer 127, the pad oxide layer 113 to the first doped region 125, the second doped region 126, a via 128 penetrating the dielectric layer 127 to the gate conductor 122, and a metal layer deposited in the via 128 and extending to the surface of the second dielectric layer 127 are formed by photolithography and etching processes, wherein the first electrode 129 in contact with the second doped region 126 located in the second well region 119 outside the isolation trench, the second electrode 130 in contact with the source ohmic contact region, the third electrode 131 in contact with the drain ohmic contact region, and the fourth electrode in contact with the gate conductor 122 are not in contact with each other.
Fig. 11a shows a schematic doping concentration distribution diagram of a first drift region located in different regions in a laterally diffused metal oxide semiconductor device according to an embodiment of the present disclosure. Fig. 11b shows a schematic diagram of electric field intensity distribution of a first drift region located in different regions in a laterally diffused metal oxide semiconductor device according to an embodiment of the present disclosure.
As shown in fig. 11a, the doping concentrations of the first drift regions 117 in different positions in the ldmos device manufactured by the above manufacturing method are different. The first drift region 117 is located below the field oxide layer 118, at the bird's beak (the junction between the field oxide layer 118 and the gate oxide layer 121), and below the gate oxide layer 121. Fig. 11a shows concentration profiles of impurities of the second doping type from the interface of the gate oxide 121 with the first drift region 117 to the inside of the first drift region 117 at positions a, B, C (wherein the abscissa represents the distance from the interface of the gate oxide 121 with the first drift region 117). In this embodiment, the first drift region 117 is formed after the patterned silicon nitride layer 114 is formed and before the field oxide layer 118 is formed, so that the first drift region 117 has a concentration distribution with a higher doping concentration below the field oxide layer 118 than below the active region, so that the doping concentration of the bird's beak of the first drift region 117 between the two is smaller than the doping concentration below the field oxide layer 118, and the electric field intensity of the bird's beak of the LDMOS device can be significantly reduced while the specific on-resistance is reduced, thereby improving the HCI reliability. This is due to LD The MOS device is a lateral withstand voltage, which can be approximately regarded as a drift region withstand voltage in a depletion state, and holes for depleting ions of the second doping type mainly come from the body region 124, the second well region 119, and the first drift region 117. According to the poisson equation of PN junction depletion region The method can obtain the following steps: maximum electric field strength E under the same applied voltage and depletion region width max In proportion to the doping concentration N. Wherein E is max For the maximum electric field strength of the depletion region, q is the electron charge amount, N is the doping concentration of the first drift region 117, ε s The relative permittivity, vbi, is the applied bias voltage across the depletion region, k is the boltzmann constant, and T is the thermodynamic temperature (kelvin scale). In addition, the experimental results also prove that when the implantation dosage of the first doped region 117 is higher, the degradation degree of the specific on-resistance of the LDMOS device is also higher in the reliability test. In addition, HCI is understood to be that when carriers move in an electric field, they are accelerated by the electric field, and at the beak, due to the structural specificity, there are a transverse electric field and a longitudinal electric field, and when carriers obtain a certain energy, they pass through the interface between the field oxide layer 118 and the first drift region 117 and are trapped by traps in the field oxide layer 118, thereby affecting the device characteristics. The magnitude of the HCI effect is strongly related to the electric field strength. The embodiment reduces the electric field strength and thus the HCI effect by reducing the doping concentration at the beak.
Fig. 11b shows the electric field intensity distribution of the surface of the first drift region 117 from the center of the first doped region 125 of the drain ohmic contact region to the center of the second doped region 126 of the source ohmic contact region in the reverse withstand voltage of the LDMOS device under the concentration distribution shown in fig. 11 a. The dashed line X in fig. 11b is a tangent to the electric field, and the abscissa indicates the distance from the left side wall of the first doped region 125 of the drain ohmic contact region, and the waveform in fig. 11b represents the electric field on the dashed line X. The first peak (left peak) in FIG. 11b isThe second peak (right peak) in fig. 11b is the electric field strength at the dashed line X below the beak, which is lower than 3.5×10 5 V/cm. It should be noted that 3.8×10 5 V/cm is taken as an upper limit for the acceptable surface electric field strength of the LDMOS device within the specification of 100V. That is, the electric field strength at the beak obtained in this embodiment does not exceed the upper limit, but the doping concentration of the first drift region 117 at the beak in the prior art is higher than that of the first drift region 117 under the field oxide layer 118, if the on-resistance is to be obtained as in this embodiment, the electric field strength at the beak is further increased, so that the HCI effect is affected, so that the on-resistance is not reduced, and the electric field strength at the beak in the LDMOS device is significantly reduced, so that the reliability problem caused by the HCI effect is alleviated.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (30)

1. A laterally diffused metal oxide semiconductor device, comprising:
a substrate;
the epitaxial layer is of a first doping type and is positioned on the substrate;
the first drift region is of a second doping type and is positioned in the epitaxial layer, and the first doping type is opposite to the second doping type;
the field oxide layer is at least partially positioned above the first drift region, the edge of the field oxide layer is a beak,
wherein the doping concentration of the first drift region below the field oxide layer is greater than the doping concentration of the first drift region at the beak.
2. The laterally diffused metal oxide semiconductor device of claim 1, further comprising:
And the second drift region is of a first doping type, is positioned in the epitaxial layer and is positioned below the first drift region, and the first drift region and the second drift region form a RESURF structure.
3. The laterally diffused metal oxide semiconductor device of claim 1, further comprising:
the isolation structure is partially or completely located in the epitaxial layer, the isolation structure is annular, and the first drift region is located on the inner side of the isolation structure.
4. The laterally diffused metal oxide semiconductor device of claim 3, further comprising:
the first buried layer is of a second doping type, is located in the substrate and located on the inner side of the isolation structure, and the epitaxial layer is located on the substrate and the first buried layer.
5. The laterally diffused metal oxide semiconductor device of claim 3 or 4, further comprising:
the body region is of a first doping type and is positioned in the first drift region;
the source ohmic contact region is a first doped region positioned in the body region;
the source electrode ohmic contact area is electrically connected with the body region ohmic contact area;
The drain ohmic contact region is a first doped region in the epitaxial layer positioned on the inner side of the isolation structure, wherein the first doped region is of a second doped type, and the second doped region is of a first doped type;
the gate oxide layer is positioned on the surface of the active region between the source ohmic contact region and the drain ohmic contact region; and
and the gate conductor is positioned on the surface of the gate oxide layer and extends to part of the surface of the field oxide layer.
6. The laterally diffused metal oxide semiconductor device of claim 5, further comprising:
the first well region is of a second doping type, is positioned in the epitaxial layer inside the isolation structure and is adjacent to the first drift region;
the second well region is of a first doping type and is positioned on one side, far away from the first well region, of the first drift region, and the body region is positioned in the second well region and the first drift region;
and the third well region is of a second doping type and is positioned in the first well region, and the drain ohmic contact region is positioned in the third well region.
7. The laterally diffused metal oxide semiconductor device of claim 3 or 4, further comprising:
the second well region is positioned in the epitaxial layer outside the isolation structure and is of a first doping type; and
And the second doping region is positioned in a second well region in the epitaxial layer outside the isolation structure so as to draw out the potential of the substrate, and the second doping region is of the first doping type.
8. The ldmos device of claim 5 wherein the source ohmic contact region is located between two of the drain ohmic contact regions or the drain ohmic contact region is located between two of the source ohmic contact regions.
9. The ldmos device of claim 3 wherein the isolation structure is an isolation trench comprising:
a trench penetrating the epitaxial layer and reaching the substrate;
the first dielectric layer covers the side wall and the bottom of the groove; and
and the polysilicon layer is positioned on the first dielectric layer and fills the groove.
10. The laterally diffused metal oxide semiconductor device of claim 9, further comprising:
the second buried layer is of the first doping type and is located in the substrate at the bottom of the groove.
11. The ldmos device of claim 9 wherein the substrate is an SOI substrate including an insulating layer therein, the epitaxial layer being formed on the insulating layer, the isolation trench extending into the insulating layer.
12. The ldmos device of claim 4 wherein the isolation structure is an isolation junction comprising:
the first well region is of a second doping type, is positioned in the epitaxial layer, is positioned above the first buried layer and is in contact with the first buried layer;
the third well region is of a second doping type and is positioned in the first well region; and
the first doping region is of a second doping type and is located in the third well region.
13. The laterally diffused metal oxide semiconductor device of claim 5, further comprising:
the pad oxide layer is positioned on the surface of the epitaxial layer and covers the surface of the active region;
the second dielectric layer is positioned on the surfaces of the field oxide layer, the pad oxide layer and the gate conductor;
a via penetrating at least the second dielectric layer to the first doped region, the second doped region, and the gate conductor;
and the metal layer fills the through hole and extends to part of the surface of the second dielectric layer to form an electrode.
14. The ldmos device of claim 1 wherein the voltage of the ldmos device ranges from 25V to 120V.
15. A method of fabricating a laterally diffused metal oxide semiconductor device, comprising:
forming an epitaxial layer of a first doping type on a substrate;
forming a first drift region of a second doping type in the epitaxial layer, wherein the first doping type is opposite to the second doping type;
forming a field oxide layer, wherein at least part of the field oxide layer is positioned above the first drift region, the edge of the field oxide layer is a beak,
wherein the doping concentration of the first drift region below the field oxide layer is greater than the doping concentration of the first drift region at the beak.
16. The method of manufacturing a laterally diffused metal oxide semiconductor device of claim 15, wherein forming a first drift region of a second doping type in the epitaxial layer comprises:
forming a pad oxide layer on the surface of the epitaxial layer;
forming a patterned silicon nitride layer on the surface of the pad oxide layer;
forming a first photoresist on a part of the silicon nitride layer and a part of the pad oxide layer;
and implanting ions of a second doping type at least once by taking the first photoresist and the silicon nitride layer as masks to form the first drift region in the epitaxial layer.
17. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 16, further comprising:
and implanting first doping type ions once by taking the first photoresist and the silicon nitride layer as masks to form a second drift region of a first doping type which is positioned in the epitaxial layer and below the first drift region, wherein the first drift region and the second drift region form a RESURF structure.
18. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 15, further comprising:
and forming an isolation structure which is partially or completely positioned in the epitaxial layer, wherein the isolation structure is annular, and the first drift region is positioned on the inner side of the isolation structure.
19. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 18, further comprising:
and forming a first buried layer of a second doping type in the substrate, wherein the first buried layer is positioned on the inner side of the isolation structure, and the epitaxial layer is positioned on the substrate and the first buried layer.
20. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 18 or 19, further comprising:
Forming a body region of a first doping type in the first drift region by taking the second photoresist as a mask;
forming a first doped region in the body region to serve as a source ohmic contact region;
forming a second doped region in the body region to serve as a body region ohmic contact region, wherein the source ohmic contact region is electrically connected with the body region ohmic contact region;
forming a first doping region in the epitaxial layer to serve as a drain ohmic contact region, wherein the drain ohmic contact region is located on the inner side of the isolation structure, the first doping region is of a second doping type, and the second doping region is of a first doping type;
forming a gate oxide layer on the surface of the active region between the source ohmic contact region and the drain ohmic contact region by using the second photoresist as a mask; and
and forming a gate conductor which is positioned on the surface of the gate oxide layer and extends to part of the surface of the field oxide layer.
21. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 20, further comprising:
forming a first well region of a second doping type adjacent to the first drift region in the epitaxial layer, wherein the first well region is positioned on the inner side of the isolation structure;
Forming a second well region of a first doping type on one side of the first drift region away from the first well region, wherein the body region is positioned in the second well region and the first drift region;
and forming a third well region with a second doping type in the first well region, wherein the drain ohmic contact region is positioned in the third well region.
22. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 18 or 19, further comprising:
forming a second well region in the epitaxial layer outside the isolation structure, wherein the second well region is of a first doping type; and
and forming a second doped region in a second well region in the epitaxial layer outside the isolation structure to draw out the potential of the substrate, wherein the second doped region is of the first doping type.
23. The method of manufacturing a ldmos device of claim 20 wherein the source ohmic contact region is located between two of the drain ohmic contact regions or the drain ohmic contact region is located between two of the source ohmic contact regions.
24. The method of manufacturing a ldmos device of claim 18 wherein the isolation structures are isolation trenches, and forming isolation structures partially or fully in the epitaxial layer comprises:
Forming a trench penetrating the epitaxial layer and reaching into the substrate;
forming a first dielectric layer which covers the side wall and the bottom of the groove and is positioned on the surface of the epitaxial layer;
filling a polysilicon layer in the groove, wherein the polysilicon layer is positioned on the first dielectric layer; and
and removing part of the first dielectric layer positioned on the surface of the epitaxial layer.
25. The method of fabricating a ldmos device of claim 24 wherein removing the portion of the first dielectric layer on the surface of the epitaxial layer comprises:
forming a protective layer on the surface of the polycrystalline silicon layer and part of the surface of the first dielectric layer, wherein the protective layer is a photoresist layer; and
and removing the first dielectric layer exposed to the outside by the protective layer, and removing the protective layer.
26. The method of manufacturing a laterally diffused metal oxide semiconductor device according to claim 24, further comprising:
and forming a second buried layer of the first doping type in the substrate at the bottom of the groove.
27. The method of manufacturing a ldmos device according to claim 24, wherein the substrate is an SOI substrate including an insulating layer therein, the epitaxial layer being formed on the insulating layer, the isolation trench extending into the insulating layer.
28. The method of manufacturing a ldmos device of claim 19 wherein the isolation structure is an isolation junction, and forming the isolation structure partially or entirely in the epitaxial layer comprises:
forming a first well region of a second doping type above and in contact with the first buried layer in the epitaxial layer;
forming a third well region of a second doping type in the first well region; and
and a first doped region of a second doping type formed in the third well region.
29. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 20, further comprising:
forming a pad oxide layer covering the surface of the active region on the surface of the epitaxial layer;
forming a second dielectric layer on the surfaces of the field oxide layer, the pad oxide layer and the gate conductor;
forming a through hole penetrating at least the second dielectric layer to reach the first doped region, the second doped region and the gate conductor;
and forming a metal layer which fills the through hole and extends to part of the surface of the second dielectric layer to form an electrode.
30. The method of manufacturing a ldmos device according to claim 16, wherein ions of the second doping type are implanted three times with the first photoresist and the silicon nitride layer as masks to form the first drift region in the epitaxial layer, the implantation energy of the first ion implantation is 10keV to 150keV, the implantation energy of the second ion implantation is 250keV to 450keV, and the implantation energy of the third ion implantation is 600keV to 1000keV.
CN202311413777.6A 2023-10-27 2023-10-27 Laterally diffused metal oxide semiconductor device and method of manufacturing the same Pending CN117542889A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311413777.6A CN117542889A (en) 2023-10-27 2023-10-27 Laterally diffused metal oxide semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311413777.6A CN117542889A (en) 2023-10-27 2023-10-27 Laterally diffused metal oxide semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
CN117542889A true CN117542889A (en) 2024-02-09

Family

ID=89781523

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311413777.6A Pending CN117542889A (en) 2023-10-27 2023-10-27 Laterally diffused metal oxide semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN117542889A (en)

Similar Documents

Publication Publication Date Title
US9466700B2 (en) Semiconductor device and method of fabricating same
US7981783B2 (en) Semiconductor device and method for fabricating the same
US8987112B2 (en) Semiconductor device and method for fabricating the same
US6777745B2 (en) Symmetric trench MOSFET device and method of making same
KR20020086726A (en) Method of forming a trench dmos having reduced threshold voltage
US9806190B2 (en) High voltage drain extension on thin buried oxide SOI
CN112397591B (en) Semiconductor device comprising LDMOS transistor and manufacturing method
EP1353368A1 (en) Semiconductor structure and method for manufacturing the same
JP2002076112A (en) Semiconductor element capable of reducing junction leakage current and narrow width effect and its manufacturing method
CN111354677B (en) Preparation method of deep trench isolation structure and semiconductor device
CN113257889B (en) LDMOS device and method for forming LDMOS device
WO2019109823A1 (en) Mosfet structure, and manufacturing method thereof
CN117542889A (en) Laterally diffused metal oxide semiconductor device and method of manufacturing the same
US20020022352A1 (en) Method for manufacturing semiconductor device with power semiconductor element and diode
EP0685882A1 (en) Semiconductor device incorporating an isolation trench and manufacture thereof
US20060220179A1 (en) Method for forming an improved isolation junction in high voltage LDMOS structures
US9966265B2 (en) Method of high voltage device fabrication
CN113964038B (en) Method for manufacturing trench gate MOSFET device
CN116884837B (en) Semiconductor device and method for manufacturing the same
KR101483721B1 (en) Power mosfet having recessed cell structure and fabrication method thereof
CN117542880B (en) Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit
CN107808827B (en) Trench type power semiconductor element and manufacturing method thereof
EP3690952A1 (en) Trench gate semiconductor device and method of manufacture
CN117936385A (en) Method for manufacturing body region of semiconductor device and method for manufacturing semiconductor device
CN114709268A (en) Junction field effect transistor and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination