CN111354638B - Manufacturing method of SONOS device - Google Patents

Manufacturing method of SONOS device Download PDF

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CN111354638B
CN111354638B CN202010159625.8A CN202010159625A CN111354638B CN 111354638 B CN111354638 B CN 111354638B CN 202010159625 A CN202010159625 A CN 202010159625A CN 111354638 B CN111354638 B CN 111354638B
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CN111354638A (en
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董立群
刘政红
奇瑞生
黄冠群
陈昊瑜
邵华
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention provides a manufacturing method of an SONOS device, which is characterized in that after a non-SONOS area is opened, a blocking oxide layer of an ONO layer of the non-SONOS area is removed firstly, then a nitride layer of the ONO layer of the non-SONOS area is removed, and then a sacrificial oxide layer of the non-SONOS area and a first blocking oxide layer of the SONOS area are removed together, so that the problem of insufficient etching window of the current ONO layer is solved, the step height difference between different areas in the SONOS device is optimized, and the reliability of the device is improved.

Description

Manufacturing method of SONOS device
Technical Field
The invention relates to the technical field of manufacturing of semiconductor devices, in particular to a manufacturing method of a Silicon Oxide Nitride Oxide Semiconductor (SONOS) device.
Background
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, also known as Silicon-Oxide-Nitride-Oxide-Silicon) flash memory has the characteristics of small unit size, good storage retentivity, low operating voltage, compatibility with CMOS (complementary metal Oxide semiconductor) process and the like. The existing SONOS flash memory structure generally includes two devices, namely, a select transistor (SG) and a storage transistor (CG), where the storage transistor is located in a SONOS region (i.e., CG region), and the select transistor is located in a non-SONOS region (i.e., SG region), where the SONOS region requires an ONO (Oxide-Nitride-Oxide) structure, and the non-SONOS region does not require an ONO structure. The ONO etching of the SONOS flash memory usually adopts dry etching, and the specific process usually comprises the steps of removing an ON layer in a non-SONOS region (namely an SG region) and stopping ON a bottom oxide layer; then oxide layer growth precleaning is carried out, and the oxide layer of the non-SONOS region is removed; and growing an oxide layer by an ISSG process, namely taking the oxide layer regrown on the non-SONOS region as a gate oxide layer, and taking the oxide layer regrown on the SONOS region as a barrier oxide layer at the top of the retained ONO layer structure.
However, as the feature size of the semiconductor device is further reduced, the problem of insufficient etching window also occurs in the dry etching of the ONO, and SIN etching residue is easily caused when the ON layer ON the non-SONOS region is removed at a later stage at the lower limit of the etching window, so that the function and reliability of the device are affected, and the method is not suitable for mass production; meanwhile, the problem of steps of the SG region and the CG region is easily caused because a window of the ONO dry etching is insufficient, and the larger the step height is, the more easily the problem of the outward expansion of the metal silicide is generated when the metal silicide is formed subsequently. For example, when a substrate of a non-SONOS region is exposed after ONO dry etching, over-etching is easily generated, and the over-etching may cause a problem of substrate damage (silicon damage), so that a phenomenon of metal silicide outdiffusion is more likely to occur when a metal silicide is subsequently formed on the substrate, and the function and reliability of a device are affected.
Disclosure of Invention
The invention aims to provide a manufacturing method of an SONOS device, which aims to solve the problem of insufficient window of the current ONO etching process, optimize the step height between different areas in the SONOS device and improve the reliability of the device.
In order to achieve the above objects and other related objects, the present invention provides a method for fabricating a SONOS device, including the steps of:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate is defined with an SONOS area and a non-SONOS area connected with the SONOS area, a sacrificial oxide layer and an ONO layer are sequentially formed on the semiconductor substrate, the sacrificial oxide layer and the ONO layer cover the SONOS area and the non-SONOS area, and the ONO layer comprises a tunneling oxide layer, a nitride layer and a first blocking oxide layer which are sequentially stacked on the sacrificial oxide layer;
step S2: coating photoresist above the ONO layer and developing to open a non-SONOS region;
step S3: removing the first blocking oxide layer of the non-SONOS region;
step S4: removing the photoresist and removing the nitride layer in the non-SONOS region;
step S5: removing the sacrificial oxide layer of the non-SONOS region and the first blocking oxide layer of the SONOS region;
step S6: and forming a gate oxide layer on the semiconductor substrate of the non-SONOS region, and forming a second blocking oxide layer above the nitride layer of the SONOS region.
Optionally, in the method for manufacturing a SONOS device, the step of forming the ONO layer includes:
step S11: pre-cleaning the sacrificial oxide layer and the semiconductor substrate;
step S12: and sequentially depositing a tunneling oxide layer, a nitride layer and a first blocking oxide layer on the pre-cleaned sacrificial oxide layer to form an ONO layer.
Optionally, in the method for manufacturing the SONOS device, the thickness of the ONO layer is
Figure BDA0002405295720000021
Optionally, in the manufacturing method of the SONOS device, in step S6, the method for forming the gate oxide layer and the second blocking oxide layer includes an ISSG process.
Optionally, in the manufacturing method of the SONOS device, the temperature of the ISSG process is 800 to 1300 ℃, and the gas used by the ISSG process includes hydrogen.
Optionally, in the manufacturing method of the SONOS device, in step S4, the method for removing the nitride layer in the non-SONOS region includes wet etching.
Optionally, in the manufacturing method of the SONOS device, the wet etching reagent includes a phosphoric acid solution.
Optionally, in the manufacturing method of the SONOS device, in step S5, the same wet etching process is used to remove the sacrificial oxide layer in the non-SONOS region and the first blocking oxide layer in the SONOS region together.
Optionally, in the manufacturing method of the SONOS device, a reagent used in the wet etching process includes hydrofluoric acid.
Optionally, in the manufacturing method of the SONOS device, in step S4, the method for removing the photoresist includes:
step S41: etching the photoresist by adopting dry etching;
step S42: and (5) carrying out surface cleaning by adopting wet etching.
In summary, the present invention provides a method for fabricating a SONOS device, which includes first providing a semiconductor substrate, where the semiconductor substrate defines a SONOS region and a non-SONOS region connected to the SONOS region, the semiconductor substrate is sequentially formed with a sacrificial oxide layer and an ONO layer, the sacrificial oxide layer and the ONO layer cover the SONOS region and the non-SONOS region, and the ONO layer includes a tunneling oxide layer, a nitride layer, and a first blocking oxide layer; secondly, coating photoresist above the ONO layer and developing to open a non-SONOS region; then, removing the first blocking oxide layer of the non-SONOS region; next, removing the photoresist and removing the nitride layer of the non-SONOS region; removing the sacrificial oxide layer of the non-SONOS region and the first blocking oxide layer of the SONOS region; and finally, respectively forming a gate oxide layer and a second blocking oxide layer above the substrate and the nitride layer of the SONOS region. The method comprises the steps of firstly removing a blocking oxide layer of an ONO layer in a non-SONOS region after the non-SONOS region is opened, then removing a nitride layer of the ONO layer in the non-SONOS region, and then removing a sacrificial oxide layer in the non-SONOS region and a first blocking oxide layer in the SONOS region together.
Drawings
FIGS. 1A-1F are process diagrams of a method for fabricating a SONOS device;
fig. 2 is an ETA diagram of metal silicide flaring caused by an over-high step between an SG area and a CG area in the manufacturing method of the SONOS device in fig. 1A to 1F;
FIG. 3A is a TEM image of the lower limit of the window of the ONO layer dry etching in the method for manufacturing the SONOS device in FIGS. 1A to 1F;
FIG. 3B is a TEM image of step heights between different regions formed after dry etching in the method for manufacturing the SONOS device in FIGS. 1A-1F;
fig. 4A to 4F are schematic process diagrams of a method for fabricating a SONOS device according to an embodiment of the invention;
FIG. 5A is a TEM image of the upper limit of the window for dry etching of the ONO layer in the method for fabricating the SONOS device of FIGS. 4A-4F;
fig. 5B is a TEM image (middle) of a step between the SG region and the CG region formed after dry etching in the method for manufacturing the SONOS device in fig. 4A to 4F;
fig. 5C is a TEM image (edge) of a step between the SG region and the CG region formed after dry etching in the method for manufacturing the SONOS device in fig. 4A to 4F;
wherein, in fig. 1A to 3B:
01-a semiconductor substrate, 02-a sacrificial oxide layer, 03-an oxide-nitride-oxide (ONO) layer, 031-a tunneling oxide layer, 032-a nitride layer, 033-a first blocking oxide layer, 04-photoresist, 051-a gate oxide layer, 052-a second blocking oxide layer, 06-a metal silicide diffusion region, and 07-residual nitride;
in FIGS. 4A-5C:
10-semiconductor substrate, 20-sacrificial oxide layer, 30-ONO layer, 301-tunneling oxide layer, 302-nitride layer, 303-first blocking oxide layer, 40-photoresist, 501-gate oxide layer, 502-second blocking oxide layer.
Detailed Description
The existing structure of the SONOS flash memory generally comprises two devices, namely a selection tube and a storage tube, wherein the area where the storage tube is located is a SONOS area (namely, CG area), and the area where the selection tube is located is a non-SONOS area (namely, SG area), wherein the SONOS area needs an ONO structure, and the non-SONOS area does not need the ONO structure. The ONO etching of the SONOS flash memory generally adopts dry etching, and the specific process is as shown in fig. 1A to 1F: step S01, as shown in fig. 1A, a semiconductor substrate 01 is provided, wherein the semiconductor substrate 01 is defined with a SONOS region (i.e., region a) and a SONOS layerA sacrificial oxide layer 02 and an ONO layer 03 are sequentially formed on the semiconductor substrate 01, the sacrificial oxide layer 02 and the ONO layer 03 cover the SONOS region and the non-SONOS region, the ONO layer 03 comprises a tunneling oxide layer 031, a nitride layer 032 and a first blocking oxide layer 033 which are sequentially stacked on the sacrificial oxide layer 02, and the thickness of the ONO layer 03 is equal to that of the SONOS region (namely, the region B)
Figure BDA0002405295720000051
An active region and a Shallow Trench Isolation (STI) structure are formed in the semiconductor substrate 01, and the STI structure is filled with silicon oxide; step S02, as shown in fig. 1B, removing the first blocking oxide layer 033 at the top of the ONO layer 03 by wet etching; step S03, as shown in fig. 1C, applying a photoresist 04 on the upper surface of the ONO layer 03, performing exposure and development to open the photoresist in the non-SONOS region, and then performing dry etching on the ONO layer 03 in the non-SONOS region by using the photoresist 04 as a mask to remove the nitride layer 032 in the non-SONOS region, and stopping on the tunneling oxide layer 031; step 04, as shown in fig. 1D, removing the sacrificial oxide layer 02 in the non-SONOS region by wet etching; step S05, as shown in fig. 1E, removing the photoresist 04; step S06, as shown in fig. 1F, pre-cleaning the gate oxide layer 051 before growing, removing the oxide layer in the non-SONOS region, growing the gate oxide layer 051 and the second blocking oxide layer 052 by the ISSG process, wherein the thickness is
Figure BDA0002405295720000052
However, with the further reduction of the characteristic size of the semiconductor device, the problem of insufficient etching window also occurs in the dry etching of the ONO, and SiN etching residue is easily caused when the ON layer ON the non-SONOS region is removed at a later stage by the lower limit of the etching window, so that the function and reliability of the device are affected, and the method is not suitable for mass production; meanwhile, because the window of the ONO dry etching is insufficient, the ONO layer 03 on the non-SONOS region is easy to damage the semiconductor substrate 01, so that the problem of step difference between the semiconductor substrate 01 in the SG region and the semiconductor substrate 01 in the CG region is caused, and the two regions are not etched in the ONO dry etchingThe larger the step difference between the domains, the more likely the metal silicide will expand when forming metal silicide on the semiconductor substrate 01 later (see fig. 2, the metal silicide expansion region 06 is marked in the figure), which affects the function and reliability of the device. For example, the lower limit of the ONO etch window may cause SiN residues, such as residual nitride 07 in fig. 3A, when the ON layer ON the non-SONOS region is removed later and the tunnel oxide layer 031 in that region is exposed. Referring to FIG. 3B, after ONO etching, a step height h is generated between the semiconductor substrate of the SONOS region and the non-SONOS region 1 (i.e., step difference) of about
Figure BDA0002405295720000061
After a non-SONOS area is opened, firstly, only etching a first blocking oxide layer of an ONO layer of the non-SONOS area by dry etching, then removing a nitride layer of the ONO layer of the non-SONOS area, and then removing a sacrificial oxide layer of the non-SONOS area and the first blocking oxide layer of the SONOS area together.
The method for manufacturing the SONOS device comprises the following specific steps:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate is defined with an SONOS region and a non-SONOS region connected with the SONOS region, a sacrificial oxide layer and an ONO layer are sequentially formed on the semiconductor substrate, the sacrificial oxide layer and the ONO layer cover the SONOS region and the non-SONOS region, and the ONO layer comprises a tunneling oxide layer, a nitride layer and a first blocking oxide layer which are sequentially stacked on the sacrificial oxide layer;
step S2: coating photoresist above the ONO layer and developing to open a non-SONOS region;
step S3: removing the first blocking oxide layer of the non-SONOS region;
step S4: removing the photoresist and removing the nitride layer in the non-SONOS region;
step S5: removing the sacrificial oxide layer of the non-SONOS region and the first blocking oxide layer of the SONOS region;
step S6: and forming a gate oxide layer on the semiconductor substrate of the non-SONOS region, and forming a second blocking oxide layer above the nitride layer of the SONOS region.
Referring to fig. 4A, in step S1, first, a semiconductor substrate 10 is provided, where the semiconductor substrate 10 defines a SONOS region (region a) and a non-SONOS region (region B) connected to the SONOS region, and the semiconductor substrate 10 may be a silicon substrate or other semiconductor substrate. The corresponding region of the semiconductor substrate 10 has been subjected to IMP implantation (ion implantation), such as well ion implantation, threshold voltage adjustment implantation, etc., an active region and a shallow trench structure are formed in the semiconductor substrate 10, and the material filled in the shallow trench structure is preferably silicon oxide. A sacrificial oxide layer 20 is formed on the semiconductor substrate 10, and then an ONO layer 30 is formed on the sacrificial oxide layer 20. The step of forming the ONO layer 30 includes:
step S11: pre-cleaning the sacrificial oxide layer 20 and the semiconductor substrate 10;
step S12: the tunnel oxide layer 301, the nitride layer 302 and the first blocking oxide layer 303 are sequentially deposited on the sacrificial oxide layer 20 after the pre-cleaning to form the ONO layer 30.
Referring to fig. 4B, in step S2, a photoresist 40 is applied over the ONO layer 30 and developed to open non-SONOS regions. After the photoresist 40 is coated on the ONO layer 30, photolithography development is performed according to process requirements, the photoresist 40 in the non-SONOS region is removed by photolithography, and the remaining photoresist 40 in the SONOS region is remained.
Referring to fig. 4C, in step S3, the first blocking oxide layer 303 in the non-SONOS region is removed by using the photoresist 40 as a mask. Preferably, the first blocking oxide layer 303 of the non-SONOS region is etched away by a dry etching method.
Referring to fig. 4D, in step S4, the photoresist 40 is removed, and the nitride layer 302 in the non-SONOS region is removed. The method for removing the photoresist 40 comprises the following steps:
step S41: etching away the photoresist 40 by dry etching;
step S42: and (5) carrying out surface cleaning by adopting wet etching.
The photoresist 40 is the photoresist for removing the SONOS region. After the photoresist 40 is removed, the nitride layer 302 in the non-SONOS region is removed, preferably, by using a wet etching method, and the wet etching reagent is preferably a phosphoric acid solution.
Referring to fig. 4E, in step S5, the sacrificial oxide layer 20 in the non-SONOS region and the first blocking oxide layer 303 in the SONOS region are removed. Preferably, the same wet etching process is used to remove the sacrificial oxide layer 20 in the non-SONOS region and the first blocking oxide layer 303 in the SONOS region together. Further, the sacrificial oxide layer 20 of the non-SONOS region is removed, and at the same time, the tunneling oxide layer 301 of the non-SONOS region is also removed. In the prior art, the removal of the sacrificial oxide layer 20 in the non-SONOS region and the first blocking oxide layer 303 in the SONOS region is performed in two steps. In this embodiment, a two-in-one wet etching method is adopted, specifically, the process of removing the sacrificial oxide layer 20 in the non-SONOS region and the first blocking oxide layer 303 in the SONOS region is combined into one (it can be said that the process of removing the first blocking oxide layer 303 in the SONOS region and the pre-cleaning process before the growth of the gate oxide layer are combined into one), and only one-step wet etching is used to implement the two-in-one wet etching, so that the cost is saved, and the efficiency is improved. The two-in-one wet etching reagent is preferably hydrofluoric acid, and the final cleaning amount is about
Figure BDA0002405295720000081
Referring to fig. 4F, in step S6, a same oxide layer forming process is performed to form corresponding oxide layers on the non-SONOS region and the SONOS region, specifically, a gate oxide layer 501 is formed on the semiconductor substrate 10 in the non-SONOS region, and a second blocking oxide layer 502 is formed on the nitride layer 302 in the SONOS region. The same oxide layer forming process is preferably an ISSG (in-situ steam generation, low-pressure rapid oxidation thermal annealing) process. The temperature of the ISSG process is preferably 800-1300 ℃, the used gas comprises hydrogen and/or oxygen, and the ISSG process can effectively improve the compactness of an oxide layer film.
Referring to fig. 5A to 5C, the step height h between different regions is finally obtained by using the method for manufacturing the SONOS device of the present embodiment 2 In that
Figure BDA0002405295720000082
(edge step height)
Figure BDA0002405295720000083
(intermediate step height) compared to the step height h between different regions in the prior art 1 Is composed of
Figure BDA0002405295720000084
The improvement is at least 30%.
The invention relates to a manufacturing method of an SONOS device, namely a process method for increasing an ONO layer etching window and optimizing step height difference between different areas.
Finally, it should be noted that the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the content of the claims of the present invention should be within the technical scope of the present invention.

Claims (10)

1. A manufacturing method of a SONOS device is characterized by comprising the following steps:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate is defined with an SONOS area and a non-SONOS area connected with the SONOS area, the step of the semiconductor substrate in the non-SONOS area at the initial stage is not lower than that of the SONOS area, a sacrificial oxide layer and an ONO layer are sequentially formed on the semiconductor substrate, the sacrificial oxide layer and the ONO layer cover the SONOS area and the non-SONOS area, and the ONO layer comprises a tunneling oxide layer, a nitride layer and a first blocking oxide layer which are sequentially stacked on the sacrificial oxide layer;
step S2: coating photoresist above the ONO layer and developing to open a non-SONOS region;
step S3: removing the first blocking oxide layer of the non-SONOS region;
step S4: removing the photoresist and removing the nitride layer in the non-SONOS region;
step S5: removing the sacrificial oxide layer of the non-SONOS region and the first blocking oxide layer of the SONOS region;
step S6: and forming a gate oxide layer on the semiconductor substrate of the non-SONOS region, and forming a second blocking oxide layer above the nitride layer of the SONOS region.
2. The method of fabricating the SONOS device of claim 1, wherein the step of forming the ONO layer comprises:
step S11: pre-cleaning the sacrificial oxide layer and the semiconductor substrate;
step S12: and sequentially depositing a tunneling oxide layer, a nitride layer and a first blocking oxide layer on the pre-cleaned sacrificial oxide layer to form an ONO layer.
3. The method of fabricating the SONOS device of claim 1, wherein the ONO layer has a thickness of
Figure FDA0003640157770000011
4. The method of fabricating the SONOS device of claim 1, wherein in the step S6, the method of forming the gate oxide layer and the second blocking oxide layer includes an ISSG process.
5. The method of claim 4, wherein the ISSG process has a temperature of 800-1300 ℃ and the gas used in the ISSG process comprises hydrogen.
6. The method of fabricating the SONOS device of claim 1, wherein the removing the nitride layer in the non-SONOS region comprises wet etching in step S4.
7. The method of fabricating the SONOS device of claim 6, wherein the wet etching reagent comprises a phosphoric acid solution.
8. The method of claim 1, wherein in step S5, the same wet etching process is used to remove the sacrificial oxide layer in the non-SONOS region and the first blocking oxide layer in the SONOS region together.
9. The method of fabricating the SONOS device of claim 8, wherein the reagent used in the wet etching process comprises hydrofluoric acid.
10. The method of fabricating the SONOS device of claim 1, wherein in step S4, the method of removing the photoresist comprises:
step S41: etching the photoresist by adopting dry etching;
step S42: and (5) carrying out surface cleaning by adopting wet etching.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946349B1 (en) * 2004-08-09 2005-09-20 Chartered Semiconductor Manufacturing Ltd. Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
JP2007067027A (en) * 2005-08-30 2007-03-15 Ememory Technology Inc Manufacturing method of built-in non-volatile memory
CN109461739A (en) * 2018-10-18 2019-03-12 上海华力微电子有限公司 A method of improving the polysilicon membrane deposition characteristics of SONOS memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946349B1 (en) * 2004-08-09 2005-09-20 Chartered Semiconductor Manufacturing Ltd. Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses
JP2007067027A (en) * 2005-08-30 2007-03-15 Ememory Technology Inc Manufacturing method of built-in non-volatile memory
CN109461739A (en) * 2018-10-18 2019-03-12 上海华力微电子有限公司 A method of improving the polysilicon membrane deposition characteristics of SONOS memory

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