CN111342836A - Two-bus code sending drive circuit with protection control function - Google Patents

Abstract

The embodiment of the invention provides a two-bus driving code sending circuit, which comprises: the bus driving circuit is used for outputting high-current power supply to the code sending circuit at the rear stage and the circuit for receiving the short-circuit signal and performing power-off protection. The bus driving circuit of the heavy current power supply output provides a heavy current bus level for the post-stage circuit, and the operation of the post-stage circuit is guaranteed; after the circuit receives the level signal with short-circuit fault, the circuit can effectively protect the rear-stage circuit from being burnt out in time.

Description

A two-bus code-transmitting drive circuit with protection control function

technical field

The invention relates to the technical field of fire protection intelligent inspection, in particular to a two-bus code sending drive circuit with a protection control function.

Background technique

With the continuous acceleration of the modernization process, in the process of developing and constructing a modern city, some hidden problems have gradually emerged. In particular, fire safety has received more and more attention. Due to the geographical isolation of various buildings, fire management is scattered, and dangerous situations cannot be detected. There are also many hidden worries in urban firefighting, which leads to the spread of fire in a timely manner. The smart fire protection system based on the new generation of information technologies such as the Internet of Things, cloud computing, big data and mobile Internet can effectively integrate all forces, find out the danger of fire, ensure fire safety, and take the initiative in disaster relief.

With the development of the fire protection industry, the original input and output modules and sound and light alarm products are connected by four wires of power lines and communication lines. The power consumption of the product is greatly reduced, and it is possible for modules and acousto-optic bands to be loaded on the second bus of fire protection.

With the current T3 protocol, the power supply capability of the second bus for fire protection is too weak to meet the requirements of the module and the second bus device of sound and light. By improving the existing product circuit and selecting components with low power consumption, the power supply capability of the second bus is improved. The short circuit of the bus loop card used by the T3 protocol is protected by a self-recovery fuse element. The general low-current bus loop card realizes short-circuit protection through self-recovery fuse elements. However, only when the short-circuit current of the bus is several times the rated current, the self-recovery fuse can realize fast action. In the case of small short-circuit current, the device cannot realize fast action to protect the current network.

SUMMARY OF THE INVENTION

In view of the above problems, embodiments of the present invention are proposed to provide a two-bus code sending circuit with a protection control function that overcomes the above problems or at least partially solves the above problems.

In order to solve the above problems, an embodiment of the present invention discloses a two-bus code sending circuit with a protection control function, including:

Two bus code transmission drive circuit module, level signal conversion circuit module and level signal inversion circuit module;

The two-bus code-transmitting drive circuit module is connected to the output end of the BUSP, and the level-signal conversion circuit module receives the control signal and converts it to a preset level, and controls the two-bus drive code-transmitting circuit module to output BUS+ level;

The level signal conversion circuit module receives the QDL level and the QDH level, and is converted into a low level and a high level or a high level and a low level through the level signal conversion circuit module, and is connected to the two buses to drive and send codes. The control terminal of the circuit module;

The level signal inversion circuit module receives the START level issued by the external single-chip microcomputer and the SHORT-CHECK level issued by the external short-circuit detection circuit; the second output of the level signal inversion circuit module is connected to the SHORT level of the single-chip microcomputer. Position and connect the input end of the first inversion module of the level signal inversion circuit module, the first output of the level signal inversion circuit module is connected to the level signal conversion circuit module and is connected to the second inversion module. input.

Preferably, the two-bus code transmission drive circuit module is a high-current power supply circuit, and the two-bus code transmission drive circuit module includes: a PMOS transistor (Positive channel-Metal-Oxide-Semiconductor, PMOS) and an NMOS transistor ( Negative channel-Metal-Oxide-Semiconductor, NMOS), the S pole of the PMOS is connected to the BUSP position, the D pole of the PMOS and the D pole of the NMOS are connected as the output terminal of the BUS+ level, the S of the NMOS is grounded in the loop, the BUSP is provided for external circuits, and the control terminal of the two-bus driving code sending circuit module includes: the G pole of the PMOS and the G pole of the NMOS.

Preferably, the bus-driven code sending circuit according to claim 1 is characterized in that, the level signal inversion circuit module is a 74HC00 gate circuit chip, and there are at least 4 independent modules in it, including: a first lead The first inversion module of the pin input end, the 2nd pin input end and the 3rd pin output end, the second inversion module of the 4th pin input end, the 5th pin input end and the 6th pin output end; One output includes: the output end of the first inversion module, the second output includes: the output end of the second inversion module; the third pin output end is connected to the fifth The pin input end, the 6th pin output end is connected to the 2nd pin input end.

Preferably, the level signal conversion circuit module comprises: a first conversion module, a second conversion module and a clamping circuit module; wherein the first conversion module comprises: a first transistor, a second transistor and The third transistor, the second conversion module includes: a fourth transistor; the clamping circuit includes: a first diode and a second diode.

Preferably, the first triode, the second triode and the fourth triode are NPN-type triodes, and the third triode is a PNP-type triode. According to the working characteristics of the triodes, the The E poles of the NPN transistor are all grounded in the loop; the first conversion module includes: the B pole of the first transistor is connected to the QDL level output end and is connected to the output end of the first inversion module connection; the C pole of the first triode is connected in parallel with the C pole of the second triode, and is connected to the B pole of the third triode; the E pole of the third triode is connected The power supply terminal in the loop is DC36V, the C pole of the third transistor is connected to the G pole of the PMOS transistor, and the C pole of the fourth transistor is connected to the G pole of the NMOS and the second three poles. The B pole of the transistor; the B pole of the fourth transistor is connected to the QDH level output terminal, and the DC36V is the externally provided loop power supply terminal.

Preferably, the QDL level and the QDH level are provided by an external microcontroller.

Preferably, the cathode of the first diode of the clamp circuit module is connected to the DC36V power supply terminal in the loop, the anode of the first diode is connected to the cathode of the second diode, and the second diode is connected to the cathode of the second diode. The anode of the diode is grounded in the loop, which is used to protect the voltage between the two diodes from exceeding the voltage range of the loop: 0-DC36V (regardless of the voltage drop of diode conduction).

Compared with the prior art, the present invention has the following beneficial effects:

The single-chip microcomputer sends a signal to control the low internal resistance, high-power MOS tube to provide a large current power supply level for the subsequent circuit, and the short circuit detection in the circuit is controlled by the single-chip level signal. If there is no short circuit, the power supply is normal; if there is a short circuit Appears, the fast and timely control circuit allows the MOS tube to turn off the power supply output to the subsequent circuit to protect the circuit from being burned in the case of a short circuit.

The circuit module directly composed of the signal terminal of the single-chip microcomputer and some electronic components controls and protects the current circuit and the subsequent code sending circuit. Due to the fast response speed of the electronic components, it can ensure the fastest speed after receiving the signal. The output of the shutdown circuit starts the protection circuit in time.

Description of drawings

1 is a flowchart of an embodiment of a two-bus code sending circuit device with a protection control function of the present invention;

2 is a circuit diagram of an embodiment of a two-bus code sending circuit device with a protection control function according to the present invention;

Fig. 3 is the gate circuit structure diagram that the present invention uses;

Figure 4 is a truth table of the gate junction used in the present invention.

Detailed ways

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments, but does not constitute any limitation to the present invention. The limited number of modifications made are still within the scope of the claims of the present invention.

Referring to FIG. 1, a flowchart of an embodiment of a two-bus code sending circuit device with a protection control function of the present invention is shown, which may specifically include:

Because when the circuit is working normally, there is a first state in which PMOS is turned on and NMOS is turned off or a second state in which PMOS is turned off and NMOS is turned on in the two-bus code sending drive circuit. To supply power to subsequent circuits, the specific steps are as follows:

S101 obtains the QDL, QDH level and START level of the first state sent by the microcontroller:

QDL is low level, QDH is high level and START is high level; wherein QDL low level is output to the B pole of the first transistor [T12] of the level signal conversion module to control its C pole and E pole The cut-off between the two, thereby controlling the B pole current of the third triode [T8]. According to the working characteristics of the PNP type triode, it can be known that the change of the B pole current of the third transistor [T8] controls the difference between the E pole and the C pole. When the time is cut off, the C pole generates a low level, and the G pole of the PMOS [T11] of the two-bus code sending drive circuit module is connected to the C pole of the third transistor [T8]. According to the working characteristics of the PMOS, it can be known that at this time The S pole and the D pole are in a conductive state, and the PMOS and NMOS are in the first state at this time;

The QDH high level is output to the B pole of the fourth transistor [T14] of the level signal conversion module to control the conduction between the C pole and the E pole. At this time, the C pole level becomes a low level, so The G pole of the NMOS [T13] of the two-bus code-transmitting drive circuit module is connected to the C pole of the fourth transistor [T14]. According to the working characteristics of the NMOS, it can be known that the D pole and the S pole of the NOMS are in an off state at this time;

The START high level is output to the 4th pin input terminal of the second inversion module [U7B] of the level signal inversion circuit module. At this time, the output terminal of the 6th pin output SHORT level will not interrupt the microcontroller; the first The input terminal of the first pin of the flip module [U7A] is connected to the external short circuit detection circuit SHORT-CHECK as a high level signal, and the output terminal of the third pin outputs a low level to the B pole of the first transistor [T12]. The low level of the output will not change the working state of the PMOS;

To sum up, when the PMOS and NMOS are in the first state, the two-bus code sending circuit outputs the BUS+ level of a large current.

S102 obtains the QDL, QDH level and START level of the second state sent by the microcontroller:

QDL is high level, QDH is low level, START is low level; wherein QDL high level is output to the first transistor [T12] of the level signal conversion module. The B pole controls its C pole and E The conduction between the poles, so as to control the B pole current of the third transistor [T8]. According to the working characteristics of the PNP type transistor, it can be known that the change of the B pole current of the third transistor [T8] controls its own E pole and C pole. The conduction between the poles makes the C pole generate a high level. According to the working characteristics of the PMOS, it can be known that the S pole and the D pole are in the off state at this time, and the PMOS and NMOS are in the second state at this time;

The QDH low level is output to the fourth transistor [T14] of the level signal conversion module. The B pole controls the connection between the C pole and the E pole to be cut off. The G pole of the NMOS [T13] of the two-bus code sending drive circuit module is connected to the C pole of the fourth transistor [T14]. According to the working characteristics of the NMOS, it can be known that the D pole and the S pole of the NOMS are in a conducting state at this time;

The START low level is output to the 4th pin input terminal of the second inversion module [U7B] of the level signal inversion circuit module. At this time, the output terminal of the 6th pin output SHORT level will cause the MCU program to be interrupted, and the MCU program will be interrupted. Interrupt the short-circuit signal in the execution detection circuit;

S103 detects whether there is a short circuit in the circuit:

If it is detected that there is no short circuit in the circuit, skip to step S101 and continue to execute; when it is detected that there is a short circuit in the circuit, execute the following steps;

S104 performs protection, and the steps are as follows:

The SHORT-CHECK level of the external detection circuit is set to a low level, which is connected to the first pin input end of the first inversion module [U7A], and outputs a high level to the level signal through the first inversion module The B pole of the first transistor [T12] of the conversion module;

The B pole of the first transistor [T12] is at a very high level, so that the C pole and the E pole are connected so that the B pole level of the third transistor [T8] is connected to a low level, so that the third transistor E is connected. The conduction between the pole and the pole C makes the pole C become a high level. At this time, the pole G of the PMOS of the two-bus code sending circuit is connected to the pole C of the third transistor [T8], which will also become high level;

According to the working characteristics of the PMOS, the S pole and the D pole of the PMOS are in the off state at this time, and the BUS+ level output is stopped;

Based on the above steps: when there is no short circuit, the single-chip microcomputer controls the two-bus-driven code-transmitting circuit module to output a large current BUS+ level to provide driving power for the subsequent circuits; when there is a short circuit, the circuit handles the short-circuit power supply. Level the signal and shut down the output of the PMOS in time to stop the power supply output, so as to prevent the circuit from being burned by the high current power supply in the case of a short circuit, and achieve the purpose of protection.

2-4, there is shown a circuit diagram of an embodiment of a two-bus code sending circuit device with a protection control function of the present invention.

One of the core concepts of the embodiments of the present invention is a two-bus code sending circuit device with a protection control function, including:

The S pole of the PMOS[T11] of the two-bus code sending drive circuit is connected to the position of the output BUSP, and the G pole of the PMOS[T11] of the two-bus code sending drive circuit module is connected to the level signal conversion circuit module. The C pole of the third transistor [T8] controls the on or off of the PMOS by changing the level of the C pole; the G pole of the NMOS [T13] is connected to the fourth transistor [ The C pole of T14] is controlled by controlling the level of the C pole to control the cut-off or conduction of the NMOS; the PMOS[T11] and the G pole of the NMOS[T13] are connected in series with the seventh resistor [R41]; The D pole of the PMOS of the code driving circuit module is connected to the D pole of the NMOS, and is used as the output terminal of the BUS+ level;

The C level of the first transistor [T12] of the level signal conversion circuit module is connected to the C pole of the second transistor [T15] and one end of the sixth resistor [R40], the first transistor [T12] The B pole is connected in parallel with two resistors, the first resistor [R45] and the second resistor [R49], wherein the first resistor [R45] is connected to the QDL level output terminal of the microcontroller, and the second resistor [R49] is connected to the level inversion circuit module. The output end of the first inversion module [U7A] of [74HC00]; the B pole of the fourth transistor [T14] of the level signal conversion circuit module is connected in parallel with the third resistor [R47] and the fourth resistor [R50], The other end of the third resistor [R47] is connected to the QDH level output end of the microcontroller, the other end of the fourth resistor [R50] is grounded in the loop, the E pole of the fourth transistor [T14] is grounded in the loop, and the fourth The C pole of the transistor [T14] is connected to the G pole of the NMOS [T13] of the bus code sending drive circuit module; the E pole of the third transistor [T8] is the output of the DC36V power supply, and is connected with the third transistor [T8]. The B stage of [T8] is connected in parallel with the fifth resistor [R33], the B pole of the third transistor [T8] is connected to the sixth resistor [R40], and the other end of the sixth resistor is connected to the C of the first transistor. pole and the C level of the second transistor; one end of the eighth resistor [R46] is connected to the G pole of the NMOS, and the other end is connected to the B level of the second transistor [T15], the second transistor The E pole of [T15] is grounded in the loop;

The level signal inversion circuit module The third pin output end of the first inversion module [U7A] is connected to the fifth pin input end of the second inversion module [U7B] and is connected with the second resistor [R49] Connect, the 1st pin input end of the described first inversion module [U7A] is connected to the output end of the short-circuit detection signal SHORT-CHECK of the external circuit; the 6th pin output end of the second inversion module [U7B] is connected to The second pin input end of the first flip module [U7A] is connected to the ninth resistor [R53], and the ninth resistor [R53] is connected to the SHORT level terminal of the single-chip microcomputer, and the second flip module [U7B] The 4th pin input end of ] is connected to the START level signal input end of the microcontroller.

The two-bus code-transmitting drive circuit module is a high-current power supply circuit, and the two-bus code-transmitting drive circuit module includes: high-power, low-resistance PMOS transistors and NMOS transistors, which can be greatly reduced when outputting high currents. The voltage drop caused by the element itself; the S pole of the PMOS is connected to the BUSP position, the D pole of the PMOS and the D pole of the NMOS are connected as the output terminal of the BUS+ level, and the S of the NMOS is grounded in the loop.

The level signal inversion circuit module is a 74HC00 gate circuit chip with at least 4 independent modules inside, including: the first inversion module of the first pin input end, the second pin input end and the third pin output end [U7A], the second inversion module [U7B] of the 4th pin input end, the 5th pin input end and the 6th pin output end; the first output includes: the output end of the first inversion module, the The second output includes: the output end of the second flip module, the third pin output end is connected to the fifth pin input end, the sixth pin output end is connected to the second pin input end, the connection in this way The working efficiency of the level signal inversion module can be improved, the 14th pin of the 74HC00 gate circuit chip is the chip power supply terminal connected to the VCC5V power supply, and the 7th pin is the ground terminal.

The level signal conversion circuit module includes: a first conversion sub-module, a second conversion sub-module and a clamping circuit module; wherein the first conversion module includes: a first triode, a second triode and a third triode The second conversion module includes: a fourth transistor; the clamping circuit includes: a first diode and a second diode.

The first triode, the second triode and the fourth triode are NPN triodes, and the third triode is a PNP triode. According to the working characteristics of the triodes, the E pole of the NPN triode is at The loops are all grounded; the first conversion module is characterized in that: the B pole of the first transistor is connected to the QDL level output terminal and is connected to the output terminal of the first flip module, and the C pole of the first transistor is connected to the output terminal of the QDL level. The pole is connected in parallel with the C pole of the second transistor, and is connected to the B pole of the third transistor, the E pole of the third transistor is connected to the power supply terminal DC36V in the loop, and the C pole of the third transistor is connected to the The G pole of the PMOS transistor and the C pole of the fourth transistor are connected to the G pole of the NMOS and the B pole of the second transistor; the B pole of the fourth transistor is connected to the QDH level output terminal.

The QDL level and the QDH level are provided by an external microcontroller.

The clamping circuit module includes: a first diode [D7] and a second diode [D11] connected in the loop; the first diode [D7] cathode is connected to the DC36V anode in the loop to connect the two bus lines to send codes The G pole of the PMOS of the driving circuit is connected, the negative pole of the second diode [D11] is connected to the G pole of the NMOS of the two-bus code transmitting driving circuit, and the positive pole of the second diode [D11] is grounded, and the The clamp circuit composed of the first diode [D7] and the second diode [D11] can protect the level value of the G pole of the PMOS and the G pole of the NMOS from exceeding the power supply loop 0-DC36V (regardless of the diode conduction voltage drop).

It should be noted that, for the sake of simple description, the device embodiments are expressed as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequences, because According to the embodiments of the present invention, certain steps may be performed in other sequences or in parallel sequences. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

This embodiment can not only provide a large current driving level for the code sending circuit, but also can detect faults in the circuit in time and detect whether there is a short circuit, so as to timely and effectively protect the code sending circuit from being burned out.

As for the circuit embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the partial description of the method embodiment.

The embodiments in this specification are described in a progressive manner, but the execution process and sequence are not completely equivalent to the sequence of actions. The sequence described in the embodiments is only to illustrate the principle of its implementation and does not limit the execution sequence of each action. .

It should be understood by those skilled in the art that embodiments of the embodiments of the present invention may be provided as circuit products. Embodiments of the present invention are described with reference to methods, circuits, and circuit diagrams according to embodiments of the present invention. The descriptions of these components, functional modules and basic circuit diagrams, those skilled in the art can realize the specified functions with reference to these descriptions.

Although preferred embodiments of the embodiments of the present invention have been described, additional changes and modifications to these embodiments may be made by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the embodiments of the present invention.

Finally, it should also be noted that in this article, the relational terms such as the level signal sent from the first module or component to the second module or component are only used to express the signal level transfer relationship, not necessarily Any direct connection or sequence between these modules or components is required or implied. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or terminal device comprising a list of elements includes not only those elements, but also a non-exclusive list of elements. other elements, or also include elements inherent to such a process, method, article or terminal equipment. Without further limitation, an element defined by the phrase "comprises a..." does not preclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

The two-bus code sending circuit with protection and control function provided by the present invention has been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are only used to help understanding The method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be It is construed as a limitation of the present invention.

3 and 4 are used in conjunction with FIG. 2 to make it easier to understand the implementation of the circuit diagram, and are not used for other purposes.

Claims (7)

1. A bus driver code transmitting circuit, comprising:

the two buses transmit a code driving circuit module, a level signal conversion circuit module and a level signal turnover circuit module;

the two-BUS code sending driving circuit module is connected to the output end of the BUSP, receives a control signal and converts the control signal into a preset level through the level signal conversion circuit module, and controls the two-BUS code sending driving circuit module to output a BUS + level;

the level signal conversion circuit module receives a QDL level and a QDH level, converts the QDL level and the QDH level into a low level and a high level or a high level and a low level through the level signal conversion circuit module, and is connected to the control end of the two-bus driving code sending circuit module;

the level signal turning circuit module receives a START level sent by an external single chip microcomputer and a SHORT-CHECK level sent by an external SHORT circuit detection circuit; the second output of the level signal turnover circuit module is connected to the SHORT level position of the single chip microcomputer and is connected with the input end of the first turnover module of the level signal turnover circuit module, and the first output of the level signal turnover circuit module is connected to the level signal conversion circuit module and is connected with the input end of the second turnover module.

2. The bus driver code transmitting circuit of claim 1, wherein the two-bus code transmitting driver circuit module is a high current power supply circuit, the two-bus code transmitting driver circuit module comprising: PMOS transistor (PMOS) and NMOS transistor (NMOS), PMOS 'S S utmost point connection BUSP position, PMOS' S D utmost point and NMOS 'S D utmost point connect as the output of BUS + level, NMOS' S S ground connection in the return circuit, BUSP provides for external circuit, the control end of two BUS drive code sending circuit module includes: and the G pole of the PMOS and the G pole of the NMOS are connected.

3. The bus driving code transmitting circuit as claimed in claim 1, wherein the level signal flipping circuit module is a 74HC00 gate chip with at least 4 independent modules inside, comprising: the first overturning module is arranged at the input end of the No. 1 pin, the input end of the No. 2 pin and the output end of the No. 3 pin, and the second overturning module is arranged at the input end of the No. 4 pin, the input end of the No. 5 pin and the output end of the No. 6 pin; the first output comprises: the output end of the first flipping module, the second output includes: the output end of the second overturning module; the output end of the 3 rd pin is connected with the input end of the 5 th pin, and the output end of the 6 th pin is connected with the input end of the 2 nd pin.

4. The bus driving code sending circuit of claim 1, wherein the level signal converting circuit module comprises: the circuit comprises a first conversion module, a second conversion module and a clamping circuit module; wherein the first conversion module comprises: the first triode, second triode and third triode, the second conversion module contain: a fourth triode; the clamping circuit comprises: a first diode and a second diode.

5. The bus driving code transmitting circuit according to claims 1, 2, 3 and 4, wherein the first, second and fourth transistors are NPN transistors, the third transistor is PNP transistor, and according to the operating characteristics of the transistors, the E poles of the NPN transistors are all grounded in the loop; the first conversion module includes: the B pole of the first triode is connected with the QDL level output end and is connected with the output end of the first overturning module; the C electrode of the first triode is connected with the C electrode of the second triode in parallel and is connected to the B electrode of the third triode; the E pole of the third triode is connected with a power supply terminal DC36V in a loop, the C pole of the third triode is connected with the G pole of the PMOS tube, and the C pole of the fourth triode is connected with the G pole of the NMOS and the B pole of the second triode; the B pole of the fourth triode is connected with the QDH level output end, and the DC36V is a loop power supply end provided by the outside.

6. The bus driver code sending circuit of claim 1, wherein the QDL level and the QDH level are provided by an external single chip.

7. The bus driving code sending circuit of claim 4, wherein the cathode of the first diode of the clamping circuit module is connected to the DC36V power supply terminal in the loop, the anode of the first diode is connected to the cathode of the second diode, and the anode of the second diode is grounded in the loop.

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