CN111342778A - Capacitance amplifying circuit - Google Patents
Capacitance amplifying circuit Download PDFInfo
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- CN111342778A CN111342778A CN201811552625.3A CN201811552625A CN111342778A CN 111342778 A CN111342778 A CN 111342778A CN 201811552625 A CN201811552625 A CN 201811552625A CN 111342778 A CN111342778 A CN 111342778A
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- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 101000986989 Naja kaouthia Acidic phospholipase A2 CM-II Proteins 0.000 description 3
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- 101710152694 Cysteine synthase 2 Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/42—Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
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Abstract
The invention discloses a capacitance amplifying circuit which comprises an amplifier and a resistor-capacitor circuit. The amplifier has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The first input terminal receives a first input signal and the second input terminal receives a second input signal. The amplifier further comprises a first current source and a second current source. The first current source is coupled to the first output terminal and the second current source is coupled to the second output terminal. The resistor-capacitor circuit is coupled to the first output terminal, the second output terminal and the ground terminal. The resistor-capacitor circuit comprises a resistor, a capacitor and a node. The node is located between the resistor and the capacitor and is coupled to the second current source through the second output terminal. The invention can achieve the effect of amplifying the capacitor under the condition of not influencing the output voltage.
Description
Technical Field
The present invention relates to amplifiers, and more particularly, to a capacitor amplifying circuit.
Background
In an amplifier circuit, a capacitor is used at the output of the amplifier to compensate the output signal. However, the area of the capacitor with large capacitance is quite large, and generally, in an integrated circuit, a capacitor with small capacitance is often used in combination with a capacitor amplifying circuit to avoid using a capacitor with an excessively large capacitance, so as to reduce the area of an integrated circuit chip.
However, the conventional capacitance amplifying circuit has a complicated circuit design and is difficult to reduce the chip area. In addition, in the prior art, a small current passes through a capacitor with a small capacitance value, so that the capacitor is easily influenced by element errors, and the amplified capacitance value generates errors. The above problems are all urgently needed to be solved.
Disclosure of Invention
Accordingly, the present invention is directed to a capacitor amplifying circuit, which effectively solves the above-mentioned problems encountered in the prior art.
An embodiment of the invention is a capacitor amplifying circuit. In this embodiment, the capacitor amplifying circuit includes an amplifier and a resistor-capacitor circuit. The amplifier has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The first input terminal receives a first input signal and the second input terminal receives a second input signal. The amplifier further comprises a first current source and a second current source. The first current source is coupled to the first output terminal and the second current source is coupled to the second output terminal. The resistor-capacitor circuit is coupled to the first output terminal, the second output terminal and the ground terminal. The resistor-capacitor circuit comprises a resistor, a capacitor and a node. The node is located between the resistor and the capacitor and is coupled to the second current source through the second output terminal.
In one embodiment, the capacitor amplifying circuit utilizes the first current source and the second current source to make the resistance current flowing through the resistor △ I, the capacitance current flowing through the capacitor △ I/(1+ K), K being a positive integer, the resistance current being a difference value related to the first input signal and the second input signal.
In one embodiment, the resistor is coupled between the first output terminal and the second output terminal, and the capacitor is coupled between the second output terminal and the ground terminal.
In one embodiment, the compensation current provided by the second current source is K △ I/(1+ K), and the compensation current flows from the node to the second current source.
In one embodiment, the second current source includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit provides a first current. The second current mirror circuit provides a second current, and the second current is the sum of the compensation current and the first current. The first current mirror circuit is coupled with the first input end; the second current mirror circuit is coupled to the second input terminal.
In one embodiment, the second current source includes a first current mirror circuit and a second current mirror circuit. The first current mirror circuit provides a first current. The second current mirror circuit provides a second current, and the second current is the sum of the compensation current and the first current. The first current mirror circuit and the second current mirror circuit are coupled to the first input terminal and the second input terminal at the same time.
In one embodiment, the capacitor is coupled between the first output terminal and the second output terminal, and the resistor is coupled between the second output terminal and the ground terminal.
In one embodiment, the compensation current provided by the second current source is K △ I/(1+ K), which flows from the second current source to the node.
In one embodiment, the second current source is a current mirror circuit for generating a capacitance current amplified by K times as a compensation current.
Compared with the prior art, the capacitor amplifying circuit of the invention is provided with an additional current mirror as a current source to generate an output current related to the voltage difference between two input signals received by the amplifier, and the capacitor current flowing through the capacitor is reduced to △ I/(1+ K) through pumping/sinking most of the current K △ I/(1+ K) at a node coupled with the capacitor, and the resistance current flowing through the resistor can be maintained at △ I, so that the effect of amplifying the capacitor by (1+ K) times can be achieved without affecting the output voltage VCOMP.
The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a capacitance amplifying circuit according to a preferred embodiment of the invention.
FIG. 2 is a diagram of a resistor and a capacitor as the first element of the RC circuit.
Fig. 3 is a diagram illustrating an embodiment of the capacitor amplifying circuit in fig. 2.
Fig. 4 is another embodiment using the capacitance amplifying circuit of fig. 2.
FIG. 5 is a diagram illustrating a first element in a RC circuit being a capacitor and a second element being a resistor.
Fig. 6 is a diagram illustrating an embodiment of the capacitor amplifying circuit in fig. 5.
Description of the main element symbols:
1. 2, 3: capacitance amplifying circuit
10. 20, 30: amplifier with a high-frequency amplifier
32: resistor-capacitor circuit
IN 1: a first input terminal
IN 2: second input terminal
OUT: output end
OUT 1: a first output terminal
OUT 2: second output terminal
CS 1: a first current source
CS 2: a second current source
320: first element
322: second element
N: node point
GND: grounding terminal
VCOMP: output voltage
S1: first input signal
S2: second input signal
Δ V: voltage difference
R, KR: resistance (RC)
C: capacitor with a capacitor element
K: positive integer
Δ I, Δ I/(1+ K), K Δ I/(1+ K): electric current
I. KI, (1+ K) I: current source
VF: voltage follower
M1-M15: transistor with a metal gate electrode
CM: current mirror circuit
CM 1: first current mirror circuit
CM 2: second current mirror circuit
IP: first input current
IN: second input current
Isource: first current
Isink: the second current
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. The same or similar numbered elements/components used in the drawings and the embodiments are used to represent the same or similar parts.
An embodiment of the invention is a capacitor amplifying circuit. Referring to fig. 1, fig. 1 is a schematic diagram of a capacitance amplifying circuit in this embodiment. As shown in fig. 1, the capacitance amplification circuit 3 includes an amplifier 30 and a resistor-capacitor circuit 32. Amplifier 30 is coupled to a resistor-capacitor circuit 32.
The amplifier 30 has a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1 and a second output terminal OUT 2. the first input terminal IN1 receives the first input signal S1 and the second input terminal IN2 receives the second input signal S2. the voltage difference between the first input signal S1 and the second input signal S2 is △ V. the amplifier 30 further includes a first current source CS1 and a second current source CS2, and the first current source CS1 and the second current source CS2 are both related to the voltage difference △ V. the first current source CS1 is coupled to the first output terminal OUT1 and the second current source CS2 is coupled to the second output terminal OUT 2.
The rc circuit 32 is coupled to the first output terminal OUT1, the second output terminal OUT2 and the ground GND. The RC circuit 32 includes a first element 320, a second element 322, and a node N. The node N is located between the first device 320 and the second device 322 and is coupled to the second current source CS2 through the second output terminal OUT 2.
In practical applications, the first element 320 is a resistor and the second element 322 is a capacitor, or the first element 320 is a capacitor and the second element 322 is a resistor. Further, the amplifier 30 may be an error amplifier in the power conversion circuit. If the first input signal S1 received by the first input terminal IN1 and the second input signal S2 received by the second input terminal IN2 are the feedback Voltage (VFB) and the reference Voltage (VREF), respectively, the voltage difference Δ V is the difference between the feedback Voltage (VFB) and the reference Voltage (VREF), and the output voltage is VCOMP.
Referring to fig. 2, fig. 2 is a diagram illustrating the first element 320 of the rc circuit 32 as a resistor R and the second element 322 as a capacitor C.
As shown in fig. 2, the first current source CS1 is coupled between the first output terminal OUT1 and the ground terminal GND, and the second current source CS2 is coupled between the second output terminal OUT2 and the ground terminal GND. The resistor R is coupled between the first output terminal OUT1 and the node N, and the capacitor C is coupled between the node N and the ground GND. A node N between the resistor R and the capacitor C is coupled to the second output terminal OUT 2.
In this embodiment, the current Δ I provided by the first current source CS1 is related to the voltage difference Δ V, i.e., the current Δ I is related to the difference between the first input signal S1 and the second input signal S2. the current Δ I flows to the resistor R through the first output terminal OUT1, so that the resistor current flowing through the resistor is also △ I, the compensation current provided by the second current source CS2 is K △ I/(1+ K), K is a positive integer, and the compensation current K △ I/(1+ K) flows from the node N to the second current source CS 2.
It can be seen from the above that, when the resistor current △ I flows to the node N, since the compensation current K △ I/(1+ K) flows from the node N to the second current source CS2, the capacitance current flowing through the capacitor C is equal to the difference obtained by subtracting the compensation current K △ I/(1+ K) from the resistor current △ I, i.e., the capacitance current flowing through the capacitor C is △ I/(1+ K).
In principle, the amplifier circuit 3 only needs to maintain the resistance current flowing through the resistor R at △ I, so that the output voltage VCOMP is not affected, when the value of K is larger, the capacitance current △ I/(1+ K) flowing through the capacitor C becomes relatively smaller, thereby achieving the effect of larger capacitor capacity, and (1+ K) is the multiplying factor of capacitor capacity.
Referring to fig. 3, fig. 3 is a diagram illustrating an embodiment of the capacitor amplifying circuit of fig. 4.
As shown in fig. 3, the second current source CS2 of the amplifier 30 may include a first current mirror circuit CM1 and a second current mirror circuit CM 2. The first current mirror circuit CM1 is coupled to the first input terminal IN1 and not coupled to the second input terminal IN 2; the second current mirror circuit CM2 is coupled to the second input IN2 and not coupled to the first input IN 1. The first current mirror circuit CM1 is configured to provide the first current Isource and the second current mirror circuit CM2 is configured to provide the second current Isink.
The first current mirror circuit CM1 includes transistors M8, M12, and M13. The gates of transistors M12 and M13 are butted against each other. One terminal of the transistor M12 is coupled to the second output terminal OUT 2. The transistor M8 is coupled between the transistor M13 and the ground GND. The second current mirror circuit CM2 includes transistors M6, M14, and M15. The gates of transistors M14 and M15 are butted against each other. The transistor M14 is coupled between the second output terminal OUT2 and the ground terminal GND. The transistor M15 is coupled between the transistor M6 and the ground GND.
The first input current IP flows from the transistor M10 to the transistor M11, the second input current IN flows from the transistor M5 to the transistor M7. through the resistor R with a resistor current △ I equal to K (IN-IP), the first current mirror circuit CM1 amplifies the first input current IP by a factor of K/(1+ K) to provide the first current Isource, i.e., the first current Isource is equal to K IP/(1+ K), the second current mirror circuit CM2 amplifies the second input current IN by a factor of K/(1+ K) to provide the second current Isink, i.e., the second current Isink is equal to K IN/(1+ K), since the compensation current K △ I/(1+ K) flows from the node N to the second output terminal OUT2, the compensation current K △ I/(1+ K) is equal to the difference of the second current Isink minus the first current Isource.
In practical applications, the circuit structure shown in fig. 3 is suitable for a dc output amplifier circuit because the dc current Δ I needs to be continuously provided to the current mirror circuit to maintain the normal operation of the circuit.
Referring to fig. 4, fig. 4 is another embodiment applying the capacitance amplifying circuit of fig. 2.
As shown in fig. 4, the second current source CS2 of the amplifier 30 may include a first current mirror circuit CM1 and a second current mirror circuit CM 2. The first current mirror circuit CM1 is coupled to the first input terminal IN1 and the second input terminal IN 2; the second current mirror circuit CM2 is coupled to the first input terminal IN1 and the second input terminal IN 2. The first current mirror circuit CM1 is configured to provide the first current Isource and the second current mirror circuit CM2 is configured to provide the second current Isink.
The first current mirror circuit CM1 includes transistors M7, M8, M14, and M15. The gates of transistors M14 and M15 are butted against each other. One terminal of the transistor M14 is coupled to the second output terminal OUT 2. The transistor M15 is coupled between the transistors M7 and M8 connected in series. The transistor M8 is coupled to the ground GND.
The second current mirror circuit CM2 includes transistors M10, M11, M16, and M17. The gates of transistors M16 and M17 are butted against each other. The transistor M16 is coupled between the second output terminal OUT2 and the ground terminal GND. The transistor M17 has one end coupled between the transistors M10 and M11 and the other end coupled to the ground GND.
The first input current IP flows from the transistor M12 to the transistor M13, the second input current IN flows from the transistor M5 to the transistor M6. through the resistor R with a resistor current △ I equal to K (IN-IP), the first current mirror circuit CM1 amplifies the first input current IP by a factor of K/(1+ K) to provide the first current Isource, i.e., the first current Isource is equal to K IP/(1+ K), the second current mirror circuit CM2 amplifies the second input current IN by a factor of K/(1+ K) to provide the second current Isink, i.e., the second current Isink is equal to K IN/(1+ K), since the compensation current K △ I/(1+ K) flows from the node N to the second output terminal OUT2, the compensation current K △ I/(1+ K) is equal to the difference of the second current Isink minus the first current Isource.
In practical applications, since the first current mirror circuit CM1 and the second current mirror circuit CM2 both have transistors (i.e., transistors M8 and M11) connected to ground, in a dc steady state, the voltage difference Δ V of the input signal is constant and the dc current is 0, so that the resistance current △ I flowing through the resistor R is 0, and only when the voltage difference Δ V of the input signal varies, the resistance current △ I flowing through the resistor R will be equal to Gm Δ V, which is suitable for a transductance amplifier for detecting the continuous variation of the input signal.
Referring to fig. 5, fig. 5 is a diagram illustrating the first element 320 of the rc circuit 32 as a capacitor C and the second element 322 as a resistor R.
As shown in fig. 5, the first current source CS1 is coupled between the first output terminal OUT1 and the ground terminal GND, and the second current source CS2 is coupled between the second output terminal OUT2 and the ground terminal GND. The capacitor C is coupled between the first output terminal OUT1 and the node N, and the resistor R is coupled between the node N and the ground GND. A node N between the capacitor C and the resistor R is coupled to the second output terminal OUT 2.
In this embodiment, the capacitance current provided by the first current source CS1 to the capacitor C through the first output terminal OUT1 is Δ I/(1+ K), and in order to keep the resistance current flowing through the resistor R at △ I, so that the output voltage VCOMP is not affected, the compensation current provided by the second current source CS2 flows from the node N to the second current source CS2, and the compensation current is the difference between the resistance current △ I and the capacitance current Δ I/(1+ K), that is, the compensation current is K △ I/(1+ K), where K is a positive integer.
In practice, the resistance current △ I is related to the voltage difference Δ V, i.e., the current Δ I is related to the difference between the first input signal S1 and the second input signal S2.
The output voltage VCOMP is not affected because the resistance current flowing through the resistor R is maintained at △ I, and the capacitance current △ I/(1+ K) flowing through the capacitor C becomes relatively smaller as the value of K is larger, so as to achieve the effect of larger capacitor capacity, and (1+ K) is the multiplying factor of the capacitor capacity.
Referring to fig. 6, fig. 6 is a diagram illustrating an embodiment of the capacitor amplifying circuit of fig. 5.
As shown in fig. 6, the second current source CS2 of the amplifier 30 is a current mirror circuit CM., the current mirror circuit CM includes transistors M6 and M8. connected in series, because the capacitance current △ I/(1+ K) output from the first output terminal OUT1 to the capacitor C is smaller than the resistance current △ I/(1+ K), the amplifier 30 amplifies the capacitance current △ I/(1+ K) by K times through the current CM to obtain the compensation current K △ I/(1+ K), and outputs the compensation current K △ I/(1+ K) through the second output terminal OUT2 located between the transistors M6 and M8 to the node N, so that the resistance current flowing through the resistor R is equal to the sum of the capacitance current △ I/(1+ K) and the capacitance current △ I/(1+ K), and the resistance current can be maintained at △ I, thereby ensuring that the output voltage VCOMP is not affected.
Compared with the prior art, the capacitor amplifying circuit of the invention is provided with an additional current mirror as a current source, generates an output current related to the voltage difference between two input signals received by the amplifier, and pumps/sinks most of the current K △ I/(1+ K) at a node coupled with the capacitor, so that the capacitor current flowing through the capacitor is reduced to △ I/(1+ K), and the resistance current flowing through the resistor can be maintained at △ I, thereby achieving the effect of amplifying the capacitor by (1+ K) times without affecting the output voltage VCOMP.
Claims (9)
1. A capacitance amplification circuit, characterized in that the capacitance amplification circuit comprises:
an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal receives a first input signal, the second input terminal receives a second input signal, the amplifier further comprises a first current source and a second current source, the first current source is coupled to the first output terminal, and the second current source is coupled to the second output terminal; and
and a resistor-capacitor circuit coupled to the first output terminal, the second output terminal and a ground terminal, wherein the resistor-capacitor circuit includes a resistor, a capacitor and a node, the node is located between the resistor and the capacitor, and the node is coupled to the second current source through the second output terminal.
2. The capacitance amplifying circuit according to claim 1, wherein the capacitance amplifying circuit utilizes the first current source and the second current source such that a resistance current flowing through the resistor is △ I, a capacitance current flowing through the capacitor is △ I/(1+ K), K is a positive integer, and the resistance current △ I is a difference value with respect to the first input signal and the second input signal.
3. The capacitance amplification circuit of claim 1, wherein the resistor is coupled between the first output terminal and the second output terminal, and the capacitor is coupled between the second output terminal and the ground terminal.
4. The capacitance amplifying circuit according to claim 3, wherein the compensation current provided by the second current source is K △ I/(1+ K), and the compensation current flows from the node to the second current source.
5. The capacitance amplifying circuit according to claim 1, wherein the second current source comprises:
a first current mirror circuit for providing a first current; and
a second current mirror circuit for providing a second current, wherein the second current is the sum of the compensation current K △ I/(1+ K) and the first current;
wherein the first current mirror circuit is coupled to the first input terminal; the second current mirror circuit is coupled to the second input terminal.
6. The capacitance amplifying circuit according to claim 1, wherein the second current source comprises:
a first current mirror circuit for providing a first current; and
a second current mirror circuit for providing a second current, wherein the second current is the sum of the compensation current K △ I/(1+ K) and the first current;
the first current mirror circuit and the second current mirror circuit are coupled to the first input terminal and the second input terminal.
7. The capacitance amplification circuit of claim 1, wherein the capacitor is coupled between the first output terminal and the second output terminal, and the resistor is coupled between the second output terminal and the ground terminal.
8. The capacitance amplifying circuit according to claim 7, wherein the compensation current provided by the second current source is K △ I/(1+ K), and flows from the second current source to the node.
9. The capacitor amplifying circuit according to claim 7, wherein the second current source is a current mirror circuit for amplifying the capacitor current △ I/(1+ K) flowing through the capacitor by K times as the compensation current K △ I/(1+ K).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811552625.3A CN111342778B (en) | 2018-12-19 | 2018-12-19 | Capacitance amplifying circuit |
| TW108145645A TW202025623A (en) | 2018-12-19 | 2019-12-13 | Capacitance amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811552625.3A CN111342778B (en) | 2018-12-19 | 2018-12-19 | Capacitance amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111342778A true CN111342778A (en) | 2020-06-26 |
| CN111342778B CN111342778B (en) | 2024-02-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811552625.3A Active CN111342778B (en) | 2018-12-19 | 2018-12-19 | Capacitance amplifying circuit |
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| Country | Link |
|---|---|
| CN (1) | CN111342778B (en) |
| TW (1) | TW202025623A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200529551A (en) * | 2004-02-27 | 2005-09-01 | Leadtrend Tech Corp | Capacitor amplifying circuit |
| US20130241635A1 (en) * | 2012-03-16 | 2013-09-19 | Upi Semiconductor Corporation | Capacitor Amplifying Circuit and Operating Method Thereof |
| CN104883039A (en) * | 2014-02-27 | 2015-09-02 | 通嘉科技股份有限公司 | Capacitance amplifying circuit applied to controller inside power converter and operation method thereof |
-
2018
- 2018-12-19 CN CN201811552625.3A patent/CN111342778B/en active Active
-
2019
- 2019-12-13 TW TW108145645A patent/TW202025623A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200529551A (en) * | 2004-02-27 | 2005-09-01 | Leadtrend Tech Corp | Capacitor amplifying circuit |
| US20130241635A1 (en) * | 2012-03-16 | 2013-09-19 | Upi Semiconductor Corporation | Capacitor Amplifying Circuit and Operating Method Thereof |
| TW201340596A (en) * | 2012-03-16 | 2013-10-01 | Upi Semiconductor Corp | Capacitor amplifying circuit and operating method thereof |
| CN104883039A (en) * | 2014-02-27 | 2015-09-02 | 通嘉科技股份有限公司 | Capacitance amplifying circuit applied to controller inside power converter and operation method thereof |
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| Publication number | Publication date |
|---|---|
| TW202025623A (en) | 2020-07-01 |
| CN111342778B (en) | 2024-02-20 |
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