CN111341713A - Packaging method and packaging structure - Google Patents

Packaging method and packaging structure Download PDF

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Publication number
CN111341713A
CN111341713A CN201811604403.1A CN201811604403A CN111341713A CN 111341713 A CN111341713 A CN 111341713A CN 201811604403 A CN201811604403 A CN 201811604403A CN 111341713 A CN111341713 A CN 111341713A
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China
Prior art keywords
substrate
layer
mark
chip
identification
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Inventor
石虎
刘孟彬
敖萨仁
李海江
李洪昌
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China Core Integrated Circuit Ningbo Co Ltd
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China Core Integrated Circuit Ningbo Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the invention provides a packaging method and a packaging structure, wherein the packaging method comprises the following steps: providing a substrate and a plurality of chips; forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged; and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate. The alignment is carried out through the first mark marking the first preset position of the chip, so that the alignment precision is improved; in addition, the first marks are positioned on the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the first marks are not limited, and the first marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.

Description

Packaging method and packaging structure
The present application claims priority from chinese patent application having application number 201811550752.X entitled "a packaging method and packaging structure" filed by the chinese patent office at 18/12/2018, the entire contents of which are incorporated herein by reference.
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a packaging method and a packaging structure.
Background
With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Among them, System In Package (SIP) is a System or subsystem that combines a plurality of active elements, passive elements, micro-electro-mechanical systems (MEMS), optical elements, etc. having different functions into one unit to form a System or subsystem that can provide multiple functions, allowing heterogeneous ICs to be integrated. Compared with a System On Chip (SOC), the System on Chip has the advantages of relatively simple integration of System-in-package, shorter design period and market period, lower cost, capability of realizing a more complex System, and relatively common packaging technology.
At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packages, Wafer Level System in Package (WLPSIP) and Panel Level System In Package (PLSIP) are mainly used in advanced packaging methods.
However, the yield and reliability of the package structure formed by the current packaging method still need to be improved.
Disclosure of Invention
The embodiment of the invention provides a packaging method and a packaging structure, and improves the yield and reliability of the packaging structure.
To solve the above problem, an embodiment of the present invention provides a packaging method, including: providing a substrate and a plurality of chips; forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged; and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate.
An embodiment of the present invention further provides a package structure, including: the chip comprises a substrate and a plurality of chips bonded on the substrate, wherein an identification layer is arranged on the surface of the substrate facing the chips, a first identification is arranged on the identification layer, and the first identification is used for marking a first preset position on the substrate, wherein the first preset position is provided with the chips.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the identification layer with the first identification is formed on the substrate, the first identification is used for marking the first preset position of the chip arranged on the substrate, and the chip is bonded to the first preset position above the substrate by identifying the first identification and aligning the chip with the first identification. The alignment is carried out through the first mark marking the first preset position of the chip, so that the alignment precision is improved; in addition, the first marks are positioned on the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the first marks are not limited, and the first marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
Drawings
FIG. 1 is a schematic diagram of a bonding step in a packaging method;
FIG. 2 is a flow chart of a packaging method according to an embodiment of the present invention;
FIGS. 3 to 7 are schematic structural diagrams corresponding to the steps in the embodiment shown in FIG. 2;
FIG. 8 is a flow chart of a packaging method according to another embodiment of the present invention;
FIGS. 9 to 11 are schematic structural diagrams corresponding to the steps in the embodiment shown in FIG. 8;
FIG. 12 is a flow chart of a packaging method according to another embodiment of the present invention;
fig. 13 is a corresponding schematic diagram of the embodiment shown in fig. 12.
Detailed Description
The yield and reliability of the package structure formed by the current packaging method are still to be improved. The reason why the yield and reliability of the package structure need to be improved is analyzed in combination with a packaging method.
The inventor has found that in the packaging method in the prior art, when bonding the chip to the substrate, the chip is usually required to be disposed at a predetermined position of the substrate, and taking a packaging structure as shown in fig. 1 as an example, the chip 130 should be bonded between two semiconductor structures 111 in the substrate 110. Therefore, when bonding a chip to a substrate, it is generally necessary to perform alignment of the chip with the substrate through a bonding alignment process. The current bonding alignment process mainly includes the following two types:
the first is a Global alignment (Global alignment) process, which sets a chip at a preset position of a substrate by recognizing a center of a circle of the substrate and determining a position of the preset position according to a distance between the center of the circle of the substrate and the preset position. This process is only an indirect alignment method, and the alignment of the preset position of the substrate is substantially a relative alignment, and the alignment accuracy is low compared to the direct alignment performed with the alignment mark that directly recognizes the preset position.
The second is a Local alignment (Local alignment) process, in which an alignment mark is formed on an upper surface of a substrate by photolithography, etching, or the like, and the alignment mark is directly disposed at a predetermined position of the substrate. However, the alignment mark formed by the photolithography and etching processes may damage the inside of the substrate, so that the substrate with the alignment mark portion cannot be provided with other internal structures. Therefore, the arrangement of the alignment mark can reduce the effective device area of the substrate. In order to reduce the occupied area of the alignment marks and increase the effective device area of the substrate, the number of the alignment marks is usually reduced as much as possible, and the area of the alignment marks is also reduced. The reduction of the number of the alignment marks increases the alignment difficulty of the alignment process, and the reduction of the area of the alignment marks further increases the alignment difficulty in the alignment process, so that the alignment precision of the alignment process is low.
When bonding a chip to a substrate, the low alignment accuracy causes a shift in the bonding position of the chip, which ultimately results in a low yield and reliability of the package structure.
In order to solve the technical problem, an embodiment of the present invention provides a packaging method, including: providing a substrate and a plurality of chips; forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged; and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate. The chip is aligned through the first mark marked with the first preset position, so that the alignment precision is improved; in addition, the first marks are positioned on the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the first marks are not limited, and the first marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
Referring to fig. 2, a flow chart of a packaging method according to an embodiment of the invention is shown. The package described in this embodiment includes the following basic steps:
step S110: providing a substrate and a plurality of chips;
step S120: forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged;
step S130: and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate.
In the embodiment of the invention, an identification layer with a first identification is formed on a substrate, the first identification is used for marking a first preset position on the substrate where the chip is arranged, and then the chip is bonded to the first preset position above the substrate by identifying the first identification and aligning the chip with the first identification. The alignment is carried out through the first mark which marks the first preset position of the chip on the substrate, and the alignment precision is improved. In addition, the first mark is positioned on the mark layer, and the first mark does not occupy the effective use area of the substrate, so that the number and the area of the first mark are not limited, and the first mark can be randomly arranged from the angle of reducing the alignment difficulty, thereby further reducing the alignment difficulty, improving the alignment precision and finally improving the yield and the reliability of the packaging structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Specifically, according to the flowchart of the encapsulation method in fig. 2, the specific implementation procedure of the encapsulation method is as follows:
first, referring to fig. 3 and 4, step S110 is performed to provide a substrate 210 (shown in fig. 3) and a plurality of chips 220 (shown in fig. 4).
When the packaging method is used to realize Wafer level system packaging, the substrate 210 is a device Wafer (cmos Wafer) or a Carrier, specifically, the Carrier is a Carrier Wafer (Carrier Wafer), and the Carrier Wafer may be a glass or silicon substrate. In particular, the carrier wafer may be a semiconductor substrate (e.g. silicon substrate) wafer, an organic glass wafer, an inorganic glass wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer or an inorganic oxide wafer.
When the packaging method is used to realize a Panel-level system package, the substrate 210 is a Panel (Panel). The panel is square, rectangular or any other desired shape, and the size of the panel is generally larger, so that more chips can be packaged, and the packaging cost is reduced. Specifically, the panel may be a Printed Wire Board (PWB), a Printed Circuit Board (PCB), a double-layer Printed Board, a multi-layer Printed Board, a flexible Circuit Board, or other types.
In this embodiment, the packaging method is used to implement wafer level system packaging, and the substrate 210 is a device wafer according to actual process requirements. Specifically, the substrate 210 is defined as a second device wafer. The second device wafer is a wafer which is already finished with device manufacturing and is manufactured by adopting a semiconductor chip manufacturing technology. Thus, the second device wafer has a plurality of semiconductor structures 211 integrated therein.
Chip 220 is a chip having at least one function. Different chips are divided into different function types according to different functions. The plurality of chips 220 may have at least one functional type. Specifically, the chip 220 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the chip may also be other functional chips.
In this embodiment, the wafer level system package is used to combine a plurality of chips 220 with different functions into one package structure, so that the function types of the plurality of chips 220 are multiple, and the chips 220 are obtained by cutting a plurality of device wafers with different function types. In other embodiments, the functional types of the plurality of chips may also be the same according to actual process requirements.
As shown in fig. 4, in the step of providing the plurality of chips 220, the plurality of chips 220 are integrated in the first device wafer 100. Taking the example of obtaining a plurality of chips 220 of the same function type, the step of providing the plurality of chips 220 includes: providing a first device wafer 100, where the first device wafer 100 includes a device region 100a and a scribe line region 100b surrounding the device region 100a, the plurality of chips 220 are integrated in the first device wafer 100 in the device region 100a, and the first device wafer 100 is diced along the scribe line region 100b to obtain a plurality of discrete chips 220 with bonding layers.
Accordingly, when the wafer level system package is used to combine a plurality of chips 220 with different functions into one package structure, a plurality of first device wafers 100 with different function types need to be provided in the step of providing the plurality of chips 220.
Next, referring to fig. 2 in combination with fig. 5 and fig. 6, fig. 6 is a top view structural diagram of the identification layer shown in fig. 5, and step S120 is executed to form an identification layer 230 (shown in fig. 5) having a first identifier 231 (shown in fig. 6) on the substrate 210 (shown in fig. 5), where the first identifier 231 is used to mark a first preset position on the substrate 210 where the chip 220 (shown in fig. 4) is disposed.
Because the first preset position for setting the chip is arranged on the first identification mark substrate, the chip is aligned according to the position of the first identification mark in the alignment process of the chip and the substrate, so that the alignment device can accurately identify the first preset position, and the alignment precision of the chip is improved. And moreover, the chip is positioned by adopting the identification layer, the process is simple, and the situation that the identification is not matched is not easy to occur, so that the accurate positioning of the chip can be realized.
In addition, in the forming process of the first mark, the substrate cannot be damaged, so that the effective use area of the substrate cannot be occupied, the number and the area of the marks are not limited, and the marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
In this embodiment, the mark layer 230 may be a single film layer only bearing the corresponding mark, or may be a composite film layer formed by a film layer bearing the corresponding mark and a film layer having adhesiveness. The composite film layer can be a composite film layer which can enable one side of the identification layer to be sticky, and can also be a composite film layer which can enable two opposite sides of the identification layer to be sticky, so that the identification layer can be adhered to the corresponding position.
Wherein, only the film layer bearing the corresponding mark is made of materials which are easy to be bonded, such as resin materials, plastic materials and the like; the film layer having adhesiveness may be a film layer formed of a material for bonding (bonding material), such as a Dry film (Dry film), Polyimide (Polyimide), Polybenzoxazole (PBO), benzocyclobutene (BCB), or the like, so that complete bonding of the chip and the substrate can be achieved when the chip is disposed to the substrate by using a bonding process.
In this embodiment, as shown in fig. 5, the identification layer 230 includes a first surface 233 facing the substrate 210 and a second surface 234 facing the chip 220. Wherein the indicia layer 230 has a first side 233 with an adhesive layer formed thereon, and the first side 233 is made adhesive to adhere the indicia layer 230 to the substrate 210. And, an adhesive film layer is formed on the second side 234 of the indicia layer 230 to adhere the chip 220 to the indicia layer 230 by making the second side 234 adhesive.
In this embodiment, the marking layer 230 is adhered to the substrate 210 by a mounting (mounting) process, a laminating (laminating) process, or a tape process. By adopting the above process, the identification layer 230 can be attached to the surface of the substrate 210 without bubbles, thereby improving the adhesive strength between the identification layer 230 and the substrate 210.
When a bonding step is included in the subsequent process and the substrate is adhered by using the adhesiveness of the identification layer, the adhesive material on the first surface 233 and/or the second surface 234 is a bonding material, and the bonding material is consistent with the adhesive material in the bonding layer for bonding, so as to ensure the process quality of the bonding process.
In this embodiment, as shown in fig. 6, the first mark 231 is a position alignment pattern marked with a first preset position. And in the alignment process of the chip, identifying the alignment pattern, and aligning the chip with the alignment pattern so as to bond the chip to the position of the alignment pattern mark. By performing alignment directly by the position of the first marker 231, the alignment accuracy is improved. In other embodiments, the first identifier may also be a grid.
In this embodiment, the step of forming the mark layer having the first mark on the substrate includes: forming a first mark on the mark layer; and after the first mark is formed, arranging a mark layer with the first mark on the substrate.
The first mark is formed on the mark layer, so that the process is easier to realize, and the mark layer is arranged only by considering the angle of the mark layer for arranging the specific first mark.
In other embodiments, the first mark may be formed on the mark layer after the mark layer is formed on the substrate.
In this embodiment, the first mark on the mark layer may be disposed on the mark layer by printing or laser printing, and the present invention is not limited thereto. It should be noted that the first mark on the mark layer should be a mark that can be recognized by a device that subsequently sets a chip to a substrate, such as a chip bonder (die attach device), so as to achieve alignment of the chip on the substrate.
Also, in this embodiment, the mark layer 230 further has a second mark 232 (as shown in fig. 6) for marking a second preset position of the substrate. The second mark 232 is used for realizing alignment between the mark layer and the substrate, and based on the alignment between the mark layer and the substrate, alignment between the chip and the substrate can be ensured, and the second mark can correspond to one or more specific positions of the substrate. The second mark may be disposed on the mark layer by printing or laser printing, or disposed on the mark layer by different processes from the first mark, respectively.
With reference to fig. 6, in this embodiment, the second preset position is an edge position of the substrate, and the second mark 232 is a pattern matched with the edge of the substrate. In other embodiments, the second predetermined position may also be a center position of the substrate, and the second mark 232 may be a graph for marking the center position of the substrate 210.
When the identification layer 230 includes the second identifier 232, in this embodiment, the step S120 may be to align the second identifier 232 on the identification layer 230 with a second preset position of the substrate, and attach the identification layer 230 on the substrate 210.
In other embodiments of the present invention, other attaching methods may be further provided according to the characteristics of the identification layer. For example, when the identification layer has a hot-melt property, the identification layer may be directly covered on the substrate, and the identification layer may be attached by a hot-melt method, which is not specifically limited herein.
Next, referring to fig. 2 in combination with fig. 7, step S130 is performed to identify the first mark 231 (as shown in fig. 6), align the chip 220 with the first mark 231, and bond the chip 220 to a first predetermined position above the substrate 210.
Specifically, the chip 220 is aligned with the alignment pattern 231, and the chip is bonded to the position marked by the alignment pattern.
In this embodiment, the second side 234 (shown in fig. 5) of the identification layer facing the chip has viscosity, so that the chip 220 is bonded to the first predetermined position of the first identification mark of the identification layer after the alignment is finished.
It can be seen that, in this embodiment, because the first preset position for setting the chip is on the first identification mark substrate, in the alignment process of the chip on the substrate, the alignment device can accurately identify the first preset position, so that the chip is aligned according to the position of the first identification mark, and the alignment precision of the chip is improved. And moreover, the chip is positioned by adopting the identification layer, the process is simple, and the situation that the identification is not matched is not easy to occur, so that the accurate positioning of the chip can be realized.
In addition, in the forming process of the first mark in the mark layer, the substrate is not damaged, so that the effective use area of the substrate is not occupied, the number and the area of the marks are not limited, and the marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
Referring to fig. 8, a flowchart of a packaging method according to another embodiment of the present invention is shown, where the packaging method includes:
step S210: providing a substrate and a plurality of chips;
step S220: forming a bonding layer on the substrate;
step S230: forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged;
step S240: and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: in this embodiment, step S220 is added, and a bonding layer is formed on the substrate.
In this embodiment, a step of forming a bonding layer is added for bonding the chip and the substrate in a subsequent bonding process, and meanwhile, when the surface of the identification layer facing the substrate has no viscosity, the bonding layer is also used as an adhesive layer to adhere the identification layer to the substrate.
Specifically, as shown in fig. 9, a bonding layer 240 is formed on the substrate 210.
The process of forming the bonding layer 240 on the substrate may be a mounting (mounting) process, a lamination (lamination) process, or an adhesion (tape) process. By adopting the above process, the bonding layer 240 can be attached to the surface of the substrate 210 without bubbles, thereby improving the adhesive strength between the bonding layer 240 and the substrate 210.
In this embodiment, the bonding layer 240 has double-sided adhesiveness. The bonding layer is a temporary bonding layer or a permanent bonding layer, wherein the temporary bonding layer is used for the temporary bonding process of the chip and the substrate, and the permanent bonding layer is used for the permanent bonding process of the chip and the substrate. The bonding layer can be a DAF film (die attach film), a laminating tape or a dry film, and the bonding layer can be made of Polyimide (Polyimide), Polybenzoxazole (PBO), benzocyclobutene (BCB) or the like, so that the bonding layer has the characteristics of higher bonding strength, good chemical resistance, acid and alkali resistance, high temperature resistance and the like. In other embodiments of the present invention, the bonding layer may be made of other materials according to specific process requirements.
It should be noted that, the bonding layer provided in this embodiment may be used for a step of bonding a chip to a substrate in a subsequent bonding process, and on the other hand, may be used for adhering the label layer to the substrate when a surface of the label layer facing the substrate is not sticky. Of course, this step can also be performed based on the consideration of the subsequent bonding process when the side of the label layer facing the substrate has tackiness.
Next, in step S230, the step of forming the mark layer on the substrate specifically includes: the identification layer 230 is adhered to the bonding layer 240 (as shown in fig. 10).
And, in step S230, the step of forming the mark layer having the first mark on the substrate includes:
s231: forming a first mark on the mark layer;
s232: and arranging an identification layer with the first identification on the substrate.
The first mark is formed on the mark layer, so that the process is easier to realize, and the mark layer is arranged only by considering the angle of the mark layer for arranging the specific first mark.
In step S231, a first mark may be formed on the mark layer by printing or laser printing.
In this embodiment, the identification layer may be adhered to the bonding layer based on the feature that the bonding layer 240 has double-sided adhesiveness. Therefore, in step S232, the mark layer with the first mark is directly attached to the substrate 210 by adhesion.
In this embodiment, as shown in fig. 11, the first mark 231 of the mark layer 230 is a grid for implementing a positioning function, and the grid positions the whole substrate position, so as to implement alignment from the chip to the substrate for the marking function of the first preset position.
Specifically, the step may include: identifying the grid, and determining a target grid corresponding to the first preset position according to the position of the grid on the substrate; aligning the chip with the target grid, and bonding the chip to the target grid.
In this embodiment, the arrangement of the grids is preset, and each grid corresponds to a different position on the substrate. After identifying the grid, a target grid 231a corresponding to the first preset position may be determined according to the position of the grid on the substrate. In the alignment process, the chip 220 is aligned with the target grid 231a, that is, the chip 220 is disposed at the first predetermined position, and the bonding process is performed to bond the chip.
It should be noted that, when the first mark is a mark (such as a grid, a matrix dot, etc.) for implementing a positioning function, the second mark may not be provided, so that positioning is performed only according to the relative positions of the chip and the substrate in the mark.
In this embodiment, the mark layer is a film attached to the substrate for positioning. The first mark on the film layer is adopted to position the chip, and the direct alignment of the chip and the substrate can be realized. And moreover, the chip is positioned by adopting the identification layer, the process is simple, and the situation that the identification is not matched is not easy to occur, so that the accurate positioning of the chip can be realized. In addition, the substrate is not damaged in the forming process of the first mark in the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the marks are not limited, and the marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
Next, step S240 is executed to identify the first mark, align the chip with the first mark, and bond the chip to a first preset position above the substrate.
In this embodiment, referring to fig. 10, the second side 234 of the identification layer 230 has adhesive properties, and the adhesive material of the second side conforms to the material of the bonding layer 240. After the first mark is identified in step S240, the chip 220 is aligned with the first mark, and the chip is adhered to a first preset position above the substrate.
The bonding process may be a thermal compression bonding process. The hot-press bonding process comprises pressurization treatment and heating treatment, and is suitable for bonding materials which can show certain bonding force under the heating condition.
Specifically, the chip 220 and the substrate 210 are subjected to a preheating treatment, so that the temperature of the chip 220 and the substrate 210 reaches a process temperature required by a subsequent first heating treatment, and the bonding layer 240 has a certain adhesive force, thereby being ready for a subsequent first pressing treatment and a subsequent first heating treatment; during the first heating process, the bonding layer 240 may be softened and the bonding layer 240 may have an adhesive force, so that the chip 220 may be preliminarily bonded by the first pressing process.
In this embodiment, the process temperature of the preheating treatment is 150 to 250 ℃, and the process time is 1 to 5 minutes.
Next, the first pressure treatment is performed on the chip 220 and the substrate 210, and the first heat treatment is performed simultaneously with the first pressure treatment.
In this embodiment, the process temperature of the first heating treatment is the process temperature of the preheating treatment, the process temperature of the first heating treatment is 150 to 250 degrees celsius, the pressure of the first pressure treatment is 100 to 800 newtons, and the process time of the first pressure treatment and the first heating treatment is 1 to 60 seconds.
In the actual packaging process, the process temperature of the preheating treatment, the process time of the preheating treatment, the pressure of the first pressurizing treatment and the process time of the first pressurizing treatment and the first heating treatment should be reasonably matched, so that the primary bonding effect is ensured, and meanwhile, the packaging efficiency is improved.
In this embodiment, the bonding layer may be configured to attach the identifier layer to the substrate when the surface of the identifier layer facing the substrate has no viscosity, which is simple in process, and may be used in a step of bonding the chip to the substrate in a bonding process to achieve bonding between the chip and the substrate.
For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
Referring to fig. 12, a flowchart of a packaging method according to another embodiment of the present invention is shown, where the packaging method includes:
step S310: providing a substrate and a plurality of chips;
step S320: forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged;
step S330: forming a bonding layer on the substrate;
step S340: and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: a forming method of the identification layer and an arrangement mode of the bonding layer. Wherein, after the step of forming the identification layer having the first identification, a bonding layer is formed on the substrate before the step of recognizing the first identification.
The bonding layer is used for bonding the chip and the substrate in a subsequent bonding process, and meanwhile, when the surface, facing the chip, of the identification layer is not sticky, the bonding layer is also used as an adhesive layer for adhering the chip to the identification layer.
In step S320 of this embodiment, the step of forming the mark layer having the first mark on the substrate includes:
step S321: forming a marking layer on the substrate;
step S322: forming a first mark on the mark layer.
In step S321, the identification layer may be formed by a mounting (mounting) process, a laminating (laminating) process, or an adhering (tape) process to achieve bubble-free attachment between the identification layer and the substrate.
In step S322, a first mark may be formed on the mark layer by printing or laser printing.
The mark layer is formed on the substrate, and then the first mark is formed on the mark layer, so that the problem of mark offset possibly caused by directly arranging the mark layer on the substrate can be avoided, and the alignment precision is further improved.
In this embodiment, the mark layer is a film attached to the substrate for positioning. The first mark on the film layer is adopted to position the chip, and the direct alignment of the chip and the substrate can be realized. And moreover, the chip is positioned by adopting the identification layer, the process is simple, and the situation that the identification is not matched is not easy to occur, so that the accurate positioning of the chip can be realized. In addition, the substrate is not damaged in the forming process of the first mark in the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the marks are not limited, and the marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
Further, in this embodiment, step S330 is added, and a bonding layer is formed on the substrate, specifically, in this embodiment, as shown in fig. 13, a bonding layer 250 is formed on the identification layer 230.
The bonding layer 250 has double-sided adhesion, and in particular, the process of forming the bonding layer 250 on the identification layer may be a mounting (mounting) process, a laminating (laminating) process or an adhering (tape) process. By adopting the above process, the bonding layer 250 can be attached to the surface of the identification layer 230 without bubbles, thereby improving the adhesive strength between the bonding layer 250 and the identification layer 230.
Since the bonding layer 250 is located above the identification layer 230, in the alignment process, the identification on the identification layer needs to be identified through the bonding layer 250, and in order to make the subsequent alignment process easily identify the corresponding identification and improve the alignment accuracy, the bonding layer has light transmittance.
In this embodiment, the light transmittance of the bonding layer is greater than or equal to 60%, in other embodiments of the present invention, the light transmittance may also be greater than 70%, 80%, or 90%, and in a preferred embodiment, the light transmittance of the bonding layer may also be greater than 95%.
The bonding layer may be a DAF film (die attach film), a laminate tape or a dry film, and the bonding layer may be made of PSA (pressure sensitive adhesive), Polybenzoxazole (PBO), benzocyclobutene (BCB), or the like, and has a high light transmittance on the premise of having adhesive strength, chemical resistance, acid and alkali resistance, and high temperature resistance.
Next, step S340 is performed to identify the first mark, align the chip with the first mark, and bond the chip to a first preset position above the substrate.
Since the bonding layer is formed on the first identifier, the first identifier needs to be identified through the bonding layer when being identified.
And when the chip is bonded to the first preset position above the substrate, the chip is bonded to the first preset position above the substrate through the bonding layer.
For the specific bonding step, reference may be made to the corresponding description in the foregoing embodiments, which are not repeated herein.
In this embodiment, the bonding layer is disposed on the identification layer, so that the bonding layer can be used for bonding a chip to a substrate in a subsequent bonding process, and on the other hand, when a surface of the identification layer facing the chip has no viscosity, the chip is attached to the identification layer.
Correspondingly, the embodiment of the invention also provides a packaging structure. With continued reference to fig. 7, a schematic structural diagram of an embodiment of the package structure of the present invention is shown.
The package structure 200 includes: the chip-on-chip module comprises a substrate 210 and a plurality of chips 220 bonded on the substrate, wherein the surface of the substrate 210 facing the chips 220 is provided with an identification layer 230, the identification layer 230 is provided with a first identification, and the first identification is used for marking a first preset position on the substrate where the chips are arranged.
When the package structure is formed by a wafer level system package, the substrate 210 is a device wafer or a carrier wafer, and the carrier wafer may be a glass or silicon substrate; when the package structure is formed by a panel-level system package, the substrate 210 is a panel. In this embodiment, the substrate 210 is a device wafer.
The chip 220 is a chip having at least one function. Different chips are divided into different function types according to different functions. The plurality of chips 220 may have at least one functional type. Specifically, the chip 220 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the chip may also be other functional chips.
In this embodiment, the package structure includes a plurality of chips 220 with different functions, so that the plurality of chips 220 have a plurality of functional types. In other embodiments, the functional types of the plurality of chips may also be the same according to actual process requirements.
The mark layer 230 has a first mark, and the first mark is used for marking a first preset position on the substrate 210 where the chip 220 is disposed. The first mark on the mark layer is adopted for alignment, so that the process is simple, and the alignment precision is high. In addition, the substrate is not damaged in the forming process of the first mark in the mark layer, so that the effective use area of the substrate is not occupied, the number and the area of the marks are not limited, and the marks can be randomly arranged from the angle of reducing the alignment difficulty, so that the alignment difficulty is further reduced, the alignment precision is improved, and the yield and the reliability of the packaging structure are finally improved.
In this embodiment, the mark layer has a second mark thereon for marking a second preset position of the substrate. In this embodiment, the second preset position is an edge position of the substrate, and the second mark is a pattern matched with the edge of the substrate.
Through setting up the second sign, can effectively aim at base plate and identification layer to make first sign on the identification layer can accurately mark out first preset position, thereby improve the alignment precision of aiming at technology.
In this embodiment, the identification layer may be a single film layer that only bears the corresponding identification, or may be a composite film layer that is composed of a film layer that bears the corresponding identification and a film layer with adhesiveness. The composite film layer can be a composite film layer which can enable one side of the identification layer to be sticky, and can also be a composite film layer which can enable two opposite sides of the identification layer to be sticky, so that the identification layer can be adhered to the corresponding position.
Wherein, only the film layer bearing the corresponding mark is made of materials which are easy to be bonded, such as resin materials, plastic materials and the like; the film layer having adhesiveness may be a film layer formed of a material for bonding (bonding material), such as a dry film, polyimide, polybenzoxazole, or benzocyclobutene, so that complete bonding of the chip and the substrate can be achieved when the chip is set to the substrate by a bonding process.
In this embodiment, the identification layer 230 includes a first side 233 (shown in fig. 5) for facing the substrate 210 and a second side 234 (shown in fig. 5) for facing the chip 220, wherein the first side 233 and the second side 234 of the identification layer 230 have an adhesive film layer formed thereon. The first side 233 is made adhesive so that the label layer 230 and the substrate 210 are bonded to each other.
The adhesive material on the first side 233 and the second side 234 may be a bonding material, and the bonding material is consistent with the adhesive material in the bonding layer, so as to ensure the bonding reliability of the chip and the substrate.
The packaging structure in this embodiment may be formed by the packaging method in the above embodiment, so that the alignment accuracy of the chip on the substrate in the packaging structure in this embodiment is improved, and further, the yield and reliability of the packaging structure are improved. For a specific description of the package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
In other embodiments, the package structure further includes a bonding layer on a surface of the identification layer facing the chip. In addition, in order to enable the alignment process to easily identify the corresponding mark and improve the alignment precision in the process of bonding the chip to the substrate, the bonding layer has light transmittance. Specifically, the bonding layer has a light transmittance of greater than or equal to 60%.
It should be further noted that, in other embodiments, the bonding layer may also be located between the identification layer and the substrate.
The bonding layer is used for realizing bonding of the chip and the substrate, and meanwhile, when the surface, facing the substrate, of the identification layer is not sticky, the bonding layer is used as a bonding layer for adhering the identification layer to the substrate.
The packaging structure in the embodiment is packaged by adopting the packaging method in the embodiment, so that the alignment precision of the chip on the substrate in the packaging structure in the embodiment is improved, and further, the yield and the reliability of the packaging structure are improved. For the specific description of the package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and this embodiment is not repeated herein
While various embodiments provided by the embodiments of the present invention have been described herein, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in the embodiments of the present invention.
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of packaging, comprising:
providing a substrate and a plurality of chips;
forming an identification layer with a first identification on the substrate, wherein the first identification is used for marking a first preset position on the substrate, where the chip is arranged;
and identifying the first mark, aligning the chip with the first mark, and bonding the chip to a first preset position above the substrate.
2. The packaging method of claim 1, wherein the label layer further has a second label corresponding to a second predetermined position of the substrate;
the step of forming the identification layer on the substrate includes: and aligning a second mark on the mark layer with a second preset position of the substrate, and attaching the mark layer to the substrate.
3. The packaging method of claim 1, wherein the first mark is a registration pattern or grid.
4. The packaging method of claim 1, wherein the step of forming an identification layer having a first identification on the substrate comprises:
forming a mark layer on the substrate, and then forming a first mark on the mark layer;
alternatively, an identification layer with a first identification is formed on the substrate.
5. The packaging method of claim 4, wherein the first mark is formed on the mark layer using a printing process or a laser printing process.
6. The packaging method of claim 1, wherein a bonding layer is formed on the substrate before or after the identification layer is formed.
7. The packaging method of claim 6, wherein the bonding layer is a temporary bonding layer or a permanent bonding layer.
8. The packaging method of claim 6, wherein the bonding layer is a DAF film, a laminate tape, or a dry film.
9. The packaging method of claim 6, wherein the bonding layer has a light transmittance of greater than or equal to 60%.
10. The packaging method of claim 1, wherein the substrate is a device wafer, carrier, or panel.
11. A package structure, comprising:
the chip comprises a substrate and a plurality of chips bonded on the substrate, wherein an identification layer is arranged on the surface of the substrate facing the chips, a first identification is arranged on the identification layer, and the first identification is used for marking a first preset position on the substrate, wherein the first preset position is provided with the chips.
12. The package structure of claim 11, wherein the label layer further has a second label thereon, the second label being for aligning with a second predetermined location of the substrate.
13. The package structure of claim 11, wherein the package structure further comprises: a bonding layer between the identification layer and the substrate; or the identification layer is positioned on the surface of the identification layer facing the chip.
14. The package structure of claim 11, wherein the bonding layer is on a side of the identification layer facing the chip, and wherein the bonding layer has a light transmittance of greater than or equal to 60%.
CN201811604403.1A 2018-12-18 2018-12-26 Packaging method and packaging structure Pending CN111341713A (en)

Applications Claiming Priority (2)

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CN201811550752X 2018-12-18

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Publication number Priority date Publication date Assignee Title
JP2007232928A (en) * 2006-02-28 2007-09-13 Tohoku Pioneer Corp Method for manufacturing light emitting panel, light emitting panel, and sealing member
CN102034799A (en) * 2009-10-07 2011-04-27 精材科技股份有限公司 Chip package and fabrication method thereof
JP2011204889A (en) * 2010-03-25 2011-10-13 Kyocera Corp Interposer substrate
CN104025728A (en) * 2011-10-31 2014-09-03 名幸电子有限公司 Method for manufacturing substrate having built-in component, and substrate having built-in component manufactured using same
JP2015109325A (en) * 2013-12-04 2015-06-11 株式会社ディスコ Processing method of package substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007232928A (en) * 2006-02-28 2007-09-13 Tohoku Pioneer Corp Method for manufacturing light emitting panel, light emitting panel, and sealing member
CN102034799A (en) * 2009-10-07 2011-04-27 精材科技股份有限公司 Chip package and fabrication method thereof
JP2011204889A (en) * 2010-03-25 2011-10-13 Kyocera Corp Interposer substrate
CN104025728A (en) * 2011-10-31 2014-09-03 名幸电子有限公司 Method for manufacturing substrate having built-in component, and substrate having built-in component manufactured using same
JP2015109325A (en) * 2013-12-04 2015-06-11 株式会社ディスコ Processing method of package substrate

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