CN111326205A - Test system, test method and test device for memory - Google Patents
Test system, test method and test device for memory Download PDFInfo
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- CN111326205A CN111326205A CN201811535042.XA CN201811535042A CN111326205A CN 111326205 A CN111326205 A CN 111326205A CN 201811535042 A CN201811535042 A CN 201811535042A CN 111326205 A CN111326205 A CN 111326205A
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Abstract
The disclosure provides a test system, a test method and a test device of a memory, and relates to the technical field of semiconductors. The test method comprises the following steps: establishing a state machine according to a plurality of operating states of a memory block of the memory and an instruction capable of being executed in each operating state; determining a plurality of candidate instructions corresponding to the current operation state according to the current operation state of the state machine; determining the running time between the current time and an initial time; randomly selecting a candidate instruction from all candidate instructions as a target instruction, and updating the current running state according to the target instruction until the running time reaches a preset value; generating an instruction sequence according to all target instructions; determining the coverage rate of each target instruction in the instruction sequence in all instructions; when the coverage rate reaches a threshold value, generating an execution file according to the instruction sequence; the execution file is executed to the memory by the tester.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a test system, a test method for a memory, and a test apparatus for a memory.
Background
With the development of semiconductor technology, the performance of the memory is gradually improved. Existing memories include Dynamic Random Access Memory (DRAM), Random Access Memory (RAM), and the like. In order to test the performance of a memory, it is often necessary to test the memory, with each test item being used for one test purpose.
At present, when a memory is detected, test items need to be written manually according to functions needing to be detected, and the memory is detected according to the written test items. However, the combination mode and the number of the manually written test items are fixed and limited, and the combination mode used by the user for each function of the memory is unlimited and unfixed, so that the efficiency of the existing test mode is low, the coverage rate of the test items is small, and the test effect needs to be improved.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a test system, a test method of a memory, and a test apparatus of a memory, which can improve test efficiency and test effect.
According to an aspect of the present disclosure, there is provided a method of testing a memory, including:
establishing a state machine according to a plurality of operating states of a storage block of a memory and an instruction capable of being executed in each operating state;
determining a plurality of candidate instructions corresponding to the current operation state according to the current operation state of the state machine;
determining the running time between the current time and an initial time;
randomly selecting one candidate instruction from all the candidate instructions as a target instruction, and updating the current running state according to the target instruction until the running time reaches a preset value;
generating an instruction sequence according to all the target instructions;
determining the coverage rate of each target instruction in the instruction sequence in all the instructions;
when the coverage rate reaches a threshold value, generating an execution file according to the instruction sequence;
executing the execution file on the memory through a tester.
In an exemplary embodiment of the present disclosure, randomly selecting one of the candidate instructions as a target instruction includes:
generating a current random number according to the random seed;
and selecting one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table, and generating a corresponding random address.
In an exemplary embodiment of the present disclosure, the test method further includes:
and controlling the target instruction to accord with a preset time sequence.
In an exemplary embodiment of the present disclosure, determining a coverage rate of each target instruction in the instruction sequence in all the instructions includes:
determining the number of combinations of a preset number of target instructions taken out from the target instructions of the instruction sequence as a first number of combinations, and the number of combinations of a preset number of instructions taken out from all the instructions as a second number of combinations;
determining a ratio of the first combined number to the second combined number as the coverage rate.
In an exemplary embodiment of the present disclosure, the test method further includes:
and when the coverage rate is less than the threshold value, regenerating the instruction sequence.
According to an aspect of the present disclosure, there is provided a test apparatus of a memory, including:
the state machine module is used for establishing a state machine according to a plurality of operating states of a storage block of the memory and an instruction which can be executed in each operating state;
the candidate module is used for determining a plurality of candidate instructions corresponding to the current running state according to the current running state of the state machine;
the time detection module is used for determining the running time between the current time and an initial time;
the random selection module is used for randomly selecting one candidate instruction from all the candidate instructions as a target instruction and updating the current running state according to the target instruction until the running time reaches a preset value;
the sequence generation module is used for generating an instruction sequence according to all the target instructions;
the coverage rate detection module is used for determining the coverage rate of each target instruction in the instruction sequence in all the instructions;
the coverage rate comparison module is used for generating an execution file according to the instruction sequence when the coverage rate is greater than a threshold value;
and the execution module is used for executing the execution file on the memory through a tester.
In an exemplary embodiment of the present disclosure, the random selection module includes:
a random number generation unit for generating a current random number according to the random seed;
and the instruction selection unit is used for selecting one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table and generating a corresponding random address.
In an exemplary embodiment of the present disclosure, the test apparatus further includes:
and the time sequence control module is used for controlling the target instruction to accord with a preset time sequence.
In an exemplary embodiment of the present disclosure, the coverage detection module includes:
a combination number determining unit, configured to determine a combination number of target instructions, which is a preset number, taken from the target instructions of the instruction sequence as a first combination number, and a combination number of instructions, which is a preset number, taken from all the instructions as a second combination number;
and the calculating unit is used for determining the ratio of the first combination number to the second combination number as the coverage rate.
According to an aspect of the present disclosure, there is provided a test system comprising a tester and the test apparatus of any one of the above.
According to the test system, the test method and the test device of the memory, the running state of the memory and the instructions which can be executed in each running state can be associated through the state machine, and each instruction can correspond to one test item; randomly selecting a target instruction from a plurality of candidate instructions corresponding to the current running state until the running time reaches a preset value, thereby selecting a plurality of target instructions, which is equivalent to randomly generating a plurality of test items; then, an instruction sequence can be generated according to each target instruction, and the coverage rate of each target instruction in the instruction sequence in all instructions is determined; when the coverage rate reaches a threshold value, an execution file can be generated according to the instruction sequence; and finally, executing the execution file on the memory through a tester to realize the test of the memory.
In the process, the test items can be prevented from being written manually, and the test efficiency can be improved. Meanwhile, in the process, each target instruction is randomly selected, so that compared with a test item written manually, the test item can contain more instruction combinations, and the coverage rate is detected, so that the coverage rate of the test item is increased, and the test effect is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a flow chart of an embodiment of a testing method of the present disclosure.
Fig. 2 is a flowchart of step S140 of the testing method in fig. 1.
FIG. 3 is a flow chart of another embodiment of a testing method of the present disclosure.
FIG. 4 is a state transition diagram of a state machine in an embodiment of a testing method of the present disclosure.
FIG. 5 is a schematic diagram of the operation of one embodiment of the disclosed test method.
FIG. 6 is a schematic diagram of a random selection module of the disclosed test device.
Fig. 7 is a schematic diagram of a coverage detection module of the testing device of the present disclosure.
FIG. 8 is a schematic view of another embodiment of a testing device of the present disclosure.
In the figure: 1. a state machine module; 2. a candidate module; 3. a time detection module; 4. a random selection module; 41. a random number generation unit; 42. an instruction selection unit; 5. a sequence generation module; 6. a coverage detection module; 61. a combination number determination unit; 62. a calculation unit; 7. a coverage comparison module; 8. an execution module; 9. and a time sequence control module.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and the like are used merely as labels, and are not limiting on the number of their objects.
In the present exemplary embodiment, a method for testing a memory is provided, where the memory may be a dynamic random access memory or other memories, and the dynamic random access memory is taken as an example in the embodiments of the present disclosure for description.
As shown in fig. 1, the testing method of the embodiments of the present disclosure may include:
step S110, establishing a state machine according to a plurality of operating states of a storage block of a memory and an instruction which can be executed in each operating state;
step S120, determining a plurality of candidate instructions corresponding to the current operation state according to the current operation state of the state machine;
step S130, determining the running time between the current time and an initial time;
step S140, randomly selecting one candidate instruction from all the candidate instructions as a target instruction, and updating the current running state according to the target instruction until the running time reaches a preset value;
step S150, generating an instruction sequence according to all the target instructions;
step S160, determining the coverage rate of each target instruction in the instruction sequence in all the instructions;
step S170, when the coverage rate reaches a threshold value, generating an execution file according to the instruction sequence;
step S180, executing the execution file on the memory through the tester.
The testing method of the embodiment of the disclosure can automatically generate the instruction sequence for executing the memory, and when the coverage reaches a threshold, the execution file is generated according to the instruction sequence, and then the execution file is executed by the testing machine, so as to realize the testing of the memory, thereby avoiding manually writing the test items, and being beneficial to improving the testing efficiency. Meanwhile, each target instruction is randomly selected, so that compared with a test item written manually, the test item can contain more instruction combinations, and the coverage rate is detected, so that the coverage rate of the test item is increased, and the test effect is improved.
The following describes in detail the steps of the test method of the embodiments of the present disclosure:
in step S110, a state machine is established according to a plurality of operating states of a memory block of the memory and instructions executable in each of the operating states.
As shown in fig. 3, the memory may include one or more memory blocks, i.e., banks, and the running states of the memory may include Bank Active state, precharge state, and Idle state, but may also include other states. The specific structure of the state machine is not particularly limited, and it may correspond any operating state to an instruction executable in the operating state, where each operating state may include a plurality of instructions, that is, each operating state corresponds to an array formed by a plurality of instructions. The same instruction may correspond to one or more operating states. Each memory block has a sense amplifier.
As shown in fig. 3, for example, the executable instructions in the Bank Active state may include PED instructions, WRITE a instructions, READ a instructions, PRE a instructions, but not limited thereto, and may also include other instructions, which are not listed herein. After an instruction is executed, the running state is updated and converted into another running state, for example, in the Bank Active state, after the PRE instruction is executed, the running state is updated from the Bank Active state to the charging state.
In step S120, a plurality of candidate instructions corresponding to the current operating state are determined according to the current operating state of the state machine.
The current operating state may be an operating state at an initial time, that is, an initial state, or an operating state at any time after the initial time. All instructions executable in the current running state can be determined as candidate instructions according to the state machine and the current running state.
For example, as shown in fig. 3, the current operating state is a Bank Active state, and the candidate commands in this state may include a PED command, a WRITE a command, a READ a command, a PRE command, and a PRE a command, but may also include other commands.
It should be noted that the state machine in fig. 3 is only used to illustrate the operation principle of the state machine, and is not limited to the state machine actually used in the embodiment of the testing method of the present disclosure.
In step S130, the operation time between the current time and an initial time is determined.
The initial time can be the starting time of the state machine operation, the current time is the time of the current state, the operation time of the state machine can be detected in real time through the time detection module, and the operation time between the current time and the initial time is determined.
In step S140, one candidate instruction is randomly selected from the candidate instructions as a target instruction, and the current operation state is updated according to the target instruction until the operation time reaches a preset value.
The target instruction may be any one of candidate instructions in a current running state, which may be randomly selected. Meanwhile, the running state after the target instruction is executed can be determined through the state machine, and the current running state is updated to the running state corresponding to the target instruction to serve as a new current state, so that the plurality of target instructions are determined in a circulating manner.
The more the number of target instructions, the more items tested on the memory, the greater the coverage of the test items, but the higher the test cost, and the test items may be duplicated after the number of target instructions reaches a certain range. Therefore, the number of target instructions needs to be limited to avoid wasting cost and time while meeting the test requirements. The number of target instructions is limited by the running time, and the longer the running time is, the more the number of target instructions is, so that the number of target instructions can be controlled by limiting the running time, specifically, when the running time of the state machine reaches a preset value, that is, when the time between the current time and the initial time reaches the preset value, the number of target instructions is sufficient, and at this time, the process of determining the target instructions can be stopped. For example, the random number may be a random number generated by a preset random number generator, which may be a pseudo-random number generator, and the instructions may be randomly selected according to the random number corresponding to each instruction, specifically, as shown in fig. 2, the determining step S140 may include steps S1410 and S1420, in which:
and step S1410, generating a current random number according to the random seed.
The random seed may be used as an initial condition of the random number generator, which may be a number, and a set of random numbers may be generated by the random number generator according to the random seed through a predetermined rule, which may be a predetermined formula. The number of the random seeds can be multiple and different, and each random seed corresponds to a group of random numbers. Where the random seed is known, the random number generated by the random number generator is known.
For example, a random seed may be generated first, and then the random seed is input to the random number generator as an initial condition, so that the random number generator calculates a random number, i.e. the current random number, according to a preset random number generation rule. For example, the random number generation rule may include a predetermined formula, the random seed is a number, and the random number generator may substitute the random seed into the formula to calculate the current random number.
Step S1420, selecting one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table, and generating a corresponding random address.
The corresponding relation between each instruction and the random number can be pre-established, each instruction corresponds to one random number, and the same random number can correspond to the same instruction or different instructions. Each instruction may be assigned a certain random number, that is, each instruction is associated with a certain number, so that the corresponding instruction is determined based on the random number. For example, the PED command may correspond to a number "2", and when the number "2" appears, the corresponding command may be determined to be the PED command.
Also, since different instructions have different degrees of importance during the test, for example, some instructions are related to the core function of the memory and may need to be executed multiple times, and some instructions are not related to the core function and may only need to be executed once or even not executed. Therefore, in order to ensure the testing effect, different weights may be assigned to each instruction, for example, as shown in fig. 4, the weight of the Activate instruction is 30%, the weight of the Power down instruction is 20%, and the weight of the Self Refresh instruction is 50%, which are not listed here. Therefore, an instruction weight arrangement table may be established in advance, and the weight of each instruction is the weight of each random number corresponding to each instruction. The weights may be the same for different instructions or may be different. When the target instruction is randomly selected from the candidate instructions, the probability that the random number with higher weight appears is higher, so that the probability that the instruction corresponding to the random number is selected is higher; the random numbers with smaller weights have a smaller probability of occurrence, and therefore the corresponding commands have a smaller probability of being selected. Since the corresponding relation between the random number and the instruction weight configuration table are known, the corresponding candidate instruction can be determined according to the current random number and the instruction weight configuration table, and the target instruction is obtained.
It should be noted that, in the case that the random seed is known, the random number generated by the random number generator is known, so that the target instruction selected according to the random number is also known. Thus, target instructions randomly selected based on any random seed may be replicated based on the random seed.
Of course, in other embodiments of the present disclosure, the random number may also be a true random number generated by a hardware random number generator, and the random number may be obtained by repeatedly sampling a randomly varying signal.
In addition, a legitimate random address may be generated for the target instruction by the random address generator while a target instruction is selected from the candidate instructions, which may be used for storage, identification, or other functions of the target instruction. For example, the random address generator randomly generates the address according to the above-mentioned principle of pseudo random numbers, and the random number and the random address corresponding to the same instruction can be generated according to the same random seed, so that the target instruction and the random address corresponding to each target instruction can be reproduced as long as the random seed is known.
In an embodiment, the testing method of the embodiments of the present disclosure may further include:
and step S190, controlling the target instruction to accord with a preset time sequence.
The timing sequence of the target instructions can be controlled in real time by a timing control module, so that the target instructions in the instruction sequence conform to a preset timing sequence, which is not particularly limited herein, and may include a time interval having a preset time between two adjacent target instructions, for example.
In step S150, an instruction sequence is generated according to all the target instructions.
The instruction sequence may include all target instructions determined when the running time reaches a preset value; and the target instructions of the instruction sequence are ordered in the selected order.
In step S160, the coverage rate of each target instruction in the instruction sequence in all the instructions is determined.
In order to ensure the testing effect, the coverage rate of the target instruction of the instruction sequence in all the instructions can be detected, and the coverage rate can be used for measuring whether the target instruction of the instruction sequence sufficiently meets the testing requirement, which can be the proportion of the target instruction in the instruction sequence in all the instructions. For example, if the coverage reaches a threshold, the test items that the target number of instructions of the instruction sequence has met are indicated.
In one embodiment, the coverage may be determined through steps S1610 and S1620, i.e., step S160 may include steps S1610 and S1620, wherein:
step S1610, determining the number of combinations of the target instructions of which the preset number is taken out from the target instructions of the instruction sequence as a first number of combinations, and determining the number of combinations of the instructions of which the preset number is taken out from all the instructions as a second number of combinations.
The preset number may be one, two or three, but is not limited thereto, and may also be more. The first number of combinations is the number of all combinations of the preset number of target instructions taken from the target instructions of the instruction sequence, and the second number of combinations is the number of all combinations of the preset number of instructions taken from all instructions. For example: the total number of the instructions is 20, the number of the target instructions of the instruction sequence is 10, the preset number is 2, and the first combination number is
The second combination number is
Step S1620, determining a ratio of the first number of combinations to the second number of combinations as the coverage.
The coverage rate can be used to reflect the proportion of the number of combinations of the target instruction in the number of combinations of all instructions, so as to measure whether the number of target instructions of the instruction sequence is enough to cover the required test items.
In step S170, when the coverage reaches a threshold, an execution file is generated according to the instruction sequence.
The specific value of the threshold is not particularly limited, and for example, the threshold may be 20%, 15%, etc., which are not listed herein. When the coverage reaches the threshold value, namely is larger than or equal to the threshold value, the number of target instructions of the instruction sequence is enough to cover the required test item. One skilled in the art can determine the size of the threshold based on the number of target instructions required for the test item.
The executable command generator may generate an execution file for a tester to execute according to the instruction sequence, and the format of the execution file is not particularly limited herein, for example, 4way pattern (4-channel format), 8way pattern (8-channel format), and the like, which may be determined according to the type of the tester.
During testing, the memory can be tested by a tester, and the execution file can be executed by the tester to execute each target instruction on the memory, so that a plurality of test items are realized.
In an embodiment, the testing method of the embodiments of the present disclosure may further include:
and step S210, when the coverage rate is less than the threshold value, regenerating the instruction sequence.
If the coverage rate is less than the threshold value, it indicates that the number of target instructions of the instruction sequence is not enough to cover the required test item, so the instruction sequence may be regenerated, i.e. the step S120 is returned, the steps S120 to S160 are executed again until the coverage rate reaches the threshold value, and the execution file is generated. The specific process from step S120 to step S160 can refer to the above, and is not described in detail here.
In step S180, the execution file is executed on the memory by the tester.
The type and structure of the tester are not particularly limited, and it may execute the execution file, i.e., execute each target instruction of the instruction sequence, to test the memory.
The following are embodiments of the disclosed test device that may be used to perform embodiments of the disclosed test method. For details that are not disclosed in the embodiments of the testing device of the present disclosure, please refer to the embodiments of the testing method of the present disclosure.
As shown in fig. 5, fig. 5 illustrates the working principle of the testing method according to the embodiment of the present disclosure, and the specific process may refer to the above description of each step, which is not described in detail herein.
The present exemplary embodiment further provides a testing apparatus of a memory, as shown in fig. 5, the testing apparatus may include a state machine module 1, a candidate module 2, a time detection module 3, a random selection module 4, a sequence generation module 5, a coverage detection module 6, a coverage comparison module 7, and an execution module 8, where:
the state machine module 1 may be configured to build a state machine based on a plurality of operating states of a memory block of the memory and instructions executable in each of said operating states.
The candidate module 2 may be configured to determine a plurality of candidate instructions corresponding to the current operating state according to the current operating state of the state machine.
The time detection module 3 can be used for determining the running time between the current time and an initial time;
the random selection module 4 may be configured to randomly select one candidate instruction from each candidate instruction as a target instruction, and update a current operation state according to the target instruction until the operation time reaches a preset value.
The sequence generating module 5 may be configured to generate an instruction sequence according to all the target instructions.
The coverage comparison module 7 may be configured to generate an execution file according to the instruction sequence when the coverage is greater than a threshold.
Execution module 8 may be used to execute the execution file on the memory by the tester.
In one embodiment, as shown in fig. 6, the random selection module 4 may include a random number generation unit 41 and an instruction selection unit 42, wherein:
the random number generation unit 41 may be configured to generate a current random number according to a random seed.
The instruction selection unit may be configured to select one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table, and generate a corresponding random address.
In one embodiment, as shown in fig. 7, the coverage detection module 6 includes a combination number determination unit 61 and a calculation unit 62, wherein:
the number-of-combinations determination unit 61 may be configured to determine, as a first number of combinations, a number of combinations of a preset number of target instructions taken from the target instructions of the instruction sequence, and as a second number of combinations, a number of combinations of a preset number of instructions taken from all the instructions.
The calculation unit 62 may be configured to determine a ratio of the first combined number and the second combined number as the coverage rate.
As shown in fig. 8, in an embodiment, the testing apparatus of the present disclosure may further include a timing control module 9, and the timing control module 9 may be configured to control the target instruction to conform to a preset timing.
The specific details of each module, unit, component and circuit in the testing apparatus have been described in detail in the corresponding testing method, and therefore are not described herein again.
The embodiment of the present disclosure further provides a test system, configured to test a memory, where the test system may include the test apparatus and the test machine in the above embodiments, where the test machine may be configured to test the memory, and may execute an execution file generated by the test apparatus to test the memory, and a specific structure of the test system is not particularly limited herein, and of course, the test system may further include other components such as a power supply, which are not listed herein.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A method for testing a memory, comprising:
establishing a state machine according to a plurality of operating states of a storage block of a memory and an instruction capable of being executed in each operating state;
determining a plurality of candidate instructions corresponding to the current operation state according to the current operation state of the state machine;
determining the running time between the current time and an initial time;
randomly selecting one candidate instruction from all the candidate instructions as a target instruction, and updating the current running state according to the target instruction until the running time reaches a preset value;
generating an instruction sequence according to all the target instructions;
determining the coverage rate of each target instruction in the instruction sequence in all the instructions;
when the coverage rate reaches a threshold value, generating an execution file according to the instruction sequence;
executing the execution file on the memory through a tester.
2. The method of claim 1, wherein randomly selecting one of the candidate instructions as a target instruction comprises:
generating a current random number according to the random seed;
and selecting one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table and generating a corresponding random address.
3. The testing method of claim 1, further comprising:
and controlling the target instruction to accord with a preset time sequence.
4. The method of claim 1, wherein determining the coverage of each target instruction in the sequence of instructions among all the instructions comprises:
determining the number of combinations of a preset number of target instructions taken out from the target instructions of the instruction sequence as a first number of combinations, and the number of combinations of a preset number of instructions taken out from all the instructions as a second number of combinations;
determining a ratio of the first combined number to the second combined number as the coverage rate.
5. The testing method of claim 1, further comprising:
and when the coverage rate is less than the threshold value, regenerating the instruction sequence.
6. An apparatus for testing a memory, comprising:
the state machine module is used for establishing a state machine according to a plurality of operating states of a storage block of the memory and an instruction which can be executed in each operating state;
the candidate module is used for determining a plurality of candidate instructions corresponding to the current running state according to the current running state of the state machine;
the time detection module is used for determining the running time between the current time and an initial time;
the random selection module is used for randomly selecting one candidate instruction from all the candidate instructions as a target instruction and updating the current running state according to the target instruction until the running time reaches a preset value;
the sequence generation module is used for generating an instruction sequence according to all the target instructions;
the coverage rate detection module is used for determining the coverage rate of each target instruction in the instruction sequence in all the instructions;
the coverage rate comparison module is used for generating an execution file according to the instruction sequence when the coverage rate is greater than a threshold value;
and the execution module is used for executing the execution file on the memory through a tester.
7. The testing device of claim 6, wherein the random selection module comprises:
a random number generation unit for generating a current random number according to the random seed;
and the instruction selection unit is used for selecting one candidate instruction from the candidate instructions as a target instruction according to the current random number and a preset instruction weight configuration table and generating a corresponding random address.
8. The testing device of claim 6, further comprising:
and the time sequence control module is used for controlling the target instruction to accord with a preset time sequence.
9. The testing device of claim 6, wherein the coverage detection module comprises:
a combination number determining unit, configured to determine a combination number of target instructions, which is a preset number, taken from the target instructions of the instruction sequence as a first combination number, and a combination number of instructions, which is a preset number, taken from all the instructions as a second combination number;
and the calculating unit is used for determining the ratio of the first combination number to the second combination number as the coverage rate.
10. A test system comprising a tester and the test apparatus of any one of claims 6-9.
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