CN111313848B - Charge transfer type sensitive amplifier - Google Patents
Charge transfer type sensitive amplifier Download PDFInfo
- Publication number
- CN111313848B CN111313848B CN202010118207.4A CN202010118207A CN111313848B CN 111313848 B CN111313848 B CN 111313848B CN 202010118207 A CN202010118207 A CN 202010118207A CN 111313848 B CN111313848 B CN 111313848B
- Authority
- CN
- China
- Prior art keywords
- unit
- charging
- voltage
- pmos tube
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a semiconductor integrated circuit, and more particularly to a charge transfer type sense amplifier comprising: the first pre-charging unit is connected between the power supply voltage and the data node, and the control end is connected with the pre-charging control voltage and is used for electrifying the data node in the pre-charging stage; the output unit is used for reading the voltage signals of the data nodes and then outputting data; a first voltage holding unit between the power supply voltage and the current compensation unit for charging in a precharge phase and discharging in a comparison phase; the control end of the current compensation unit is connected with the compensation control voltage, and the output end of the voltage holding unit is connected with the data node and is used for providing compensation current for the data node in the comparison stage; and the bit line adjusting unit is used for controlling the connection between the bit line node and the data node. The invention can maintain the normal function of the circuit through the voltage holding unit when the circuit is disconnected from the power supply in the comparison stage, and improves the reliability of the sensitive amplifier.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge transfer type sense amplifier.
Background
The charge transfer type sense amplifier can amplify a weak charge amount to output a dot data signal with low impedance.
As shown in fig. 1, a circuit diagram of a charge transfer type sense amplifier in the related art includes:
NMOS tube n0, the grid connects and blocks the voltage VCLA, keep the open state; the source is connected to a bit line node B through which a memory cell (cell) is connected.
The PMOS tube p0 has a gate connected to the precharge voltage PR, a source connected to the power supply voltage VDD, and a drain connected to the drain of the NMOS tube n0 and to the data node D.
The PMOS transistor p1 has a gate connected to a control signal PBI, which is a fixed voltage, such as a bias voltage through current mirroring.
The output unit 101, a first input terminal of the output unit 101 is connected to the data node D, and a second input terminal is connected to the reference voltage NBI, which is a fixed voltage, such as a bias voltage through current mirroring. The output terminal of the output unit 101 serves as the output terminal DOUT of the charge transfer type sense amplifier, and an output signal is formed at the output terminal DOUT by comparison of the data node D and the reference voltage NBI.
In practical application, the related art will often encounter the condition of electric pulse, that is, the power supply voltage VDD will have a large amplitude and high frequency jitter (for example, the amplitude of 20MHz is 5V-2V change), so that the sense amplifier will read out erroneous data due to the large current change, and the reliability of the circuit is low.
Disclosure of Invention
The invention provides a charge transfer type sensitive amplifier, which can solve the problem of error data reading caused by great current change of the sensitive amplifier in the related technology.
A charge transfer type sense amplifier comprising:
the first pre-charging unit is connected between the power supply voltage and the data node, and the control end of the first pre-charging unit is connected with the pre-charging control voltage and is used for electrifying the data node in the pre-charging stage;
the output unit is used for reading the voltage signals of the data nodes and then outputting data;
a first voltage holding unit connected between the power supply voltage and the current compensation unit for charging in a precharge phase and discharging in a comparison phase;
the control end of the current compensation unit is connected with compensation control voltage, and the output end of the voltage holding unit is connected with the data node and is used for providing compensation current for the data node in a comparison stage;
and the bit line adjusting unit is connected between the bit line node of the memory unit and the data node and used for controlling the connection between the bit line node and the data node.
Optionally, the first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel;
the second pre-charging unit is connected between the power supply voltage and the current compensation unit, the control end of the second pre-charging unit is connected with the pre-charging control voltage, and the second pre-charging unit is used for charging the first charging and discharging unit in the pre-charging stage;
the first charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
Optionally, the second pre-charging unit includes a first PMOS tube;
the grid of the first PMOS tube is the control end of the second pre-charging unit, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the current compensation unit and the first charging and discharging unit.
Optionally, the first charge and discharge unit further includes: and one end of the first capacitor is connected with the drain electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
Optionally, the output unit includes:
the control end of the comparison passage A module is connected with the data node;
the control end of the comparison passage B module is connected with a comparison control voltage;
the output unit is used for comparing the voltage signal of the data node with the comparison control voltage and then outputting data.
Optionally, the charge transfer type sense amplifier further includes: and a second voltage holding unit connected between the power supply voltage and the output unit for charging in the precharge phase and discharging in the comparison phase.
Optionally, the second voltage holding unit includes: the third pre-charging unit and the second charging and discharging unit are connected in parallel;
the third pre-charging unit is connected between the power supply voltage and the output unit, the control end of the third pre-charging unit is connected with the pre-charging control voltage, and the third pre-charging unit is used for charging the second charging and discharging unit in the pre-charging stage;
the second charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
Optionally, the third pre-charging unit includes a second PMOS tube;
the grid of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit.
Optionally, the second charge-discharge unit includes a second capacitor, one end of the second capacitor is connected to the drain electrode of the second PMOS transistor, and the other end is grounded.
Optionally, the first pre-charging unit includes a third PMOS tube;
the grid of the third PMOS tube is the control end of the first pre-charging unit, the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the data node.
The technical scheme of the invention at least comprises the following advantages: the first pre-charging unit and the first voltage holding unit are used for alternately electrifying the data node VD in a pre-charging stage and a comparison stage, and the first voltage holding unit can be used for self-charging and charging to a power supply voltage in the pre-charging stage, so that even if no power supply voltage is used for supplying power in the comparison stage, the current compensation unit can still work normally, the power supply voltage of the data node VD can be prevented from changing due to the fact that the power supply is subjected to high-frequency shaking in the comparison stage in actual application, and the reliability of data output of the output unit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit diagram of a charge transfer type sense amplifier in the related art.
Fig. 2 is a timing diagram of a charge transfer sense amplifier according to the present invention.
Fig. 3 is a circuit diagram of an embodiment of a charge transfer type sense amplifier of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1:
the present embodiment provides a charge transfer type sense amplifier including:
the control end of the first PRE-charging unit is connected with a PRE-charging control voltage PRE and is used for electrifying the data node VD in a PRE-charging stage;
the precharge control voltage PRE can control the charge transfer type sense amplifier to be in the precharge stage by changing the voltage value. Referring to fig. 3, when the precharge control voltage PRE is set to a low level, the charge transfer type sense amplifier is in a precharge phase, and after the precharge phase is ended, when the precharge control voltage PRE is set to a high level, the charge transfer type sense amplifier is in a comparison phase.
And the output unit is used for reading the voltage signal of the data node VD and outputting data.
The first voltage holding unit is connected between the power supply voltage and the current compensation unit and is used for charging in a precharge stage and discharging in a comparison stage; the first voltage holding unit is able to supply the current compensation unit with power when discharging is performed, so that in the comparison phase the current compensation unit can still function normally even if no supply voltage is supplied to the current compensation unit.
The control end of the current compensation unit is connected with the compensation control voltage PBIAS, and the output end of the voltage holding unit is connected with the data node VD and is used for providing compensation current for the data node VD in the comparison stage; when the current compensation unit is operating normally, a compensation current can be supplied to the data node VD.
And the bit line adjusting unit is connected between the bit line node BL and the data node VD of the memory cell and used for controlling the connection between the bit line node BL and the data node VD.
It should be explained that the first pre-charging unit is able to energize the data node VD during the pre-charging phase, and the first voltage holding unit is able to charge, whereas during the comparison phase, the first pre-charging unit is disconnected from the power supply voltage, and the first voltage holding unit is disconnected from the power supply voltage, and is able to discharge the amount of charge during the pre-charging phase.
The working process of the charge transfer type sensitive amplifier of the embodiment of the invention comprises the following steps:
a first phase, a precharge phase: the PRE-charging control voltage PRE is set to be low level, and the first PRE-charging unit is used for electrifies the data node VD so that the data node VD is charged to the power supply voltage; the first voltage holding unit performs self-charging such that the first voltage holding unit is charged to a power supply voltage.
A second stage, a comparison stage: the precharge control voltage PRE is set to a high level, the first precharge unit is disconnected from the power supply voltage, the energizing of the data node VD is stopped, and meanwhile, the first voltage holding unit is self-charged and charged to the power supply voltage in the precharge stage, so that the first voltage holding unit keeps supplying power to the data node VD with the power supply voltage in the comparison stage;
when the memory cell is an erase cell (e cell), the e cell has a current, and in the comparison stage, the voltage of the bit line node BL is reduced, so that the voltage of the data node VD is reduced, and the output circuit outputs high level data.
When the memory cell is a write cell (p cell), the p cell has no current, the voltage of the data node VD still keeps the power voltage VDD unchanged, and the output circuit outputs low level data.
In the embodiment, the first pre-charging unit and the first voltage holding unit are used for alternately electrifying the data node VD in the pre-charging stage and the comparison stage, and the first voltage holding unit can be used for self-charging and charging to the power supply voltage in the pre-charging stage, so that even if no power supply voltage is used for supplying power in the comparison stage, the current compensation unit can still work normally, and the power supply voltage of the data node VD can be prevented from changing due to the fact that the power supply is subjected to high-frequency shaking in the comparison stage in actual application, and the reliability of data output of the output unit is improved.
Example 2:
this example is based on example 1
The first pre-charging unit comprises a third PMOS tube P3; the grid electrode of the third PMOS tube P3 is a control end of the first pre-charging unit, the source electrode of the third PMOS tube P3 is connected with a power supply voltage, and the drain electrode of the third PMOS tube P3 is connected with a data node VD.
An output unit comprising: the control end of the comparison passage A module is connected with the data node VD; the control end of the comparison path B module is connected with the comparison control voltage NBIAS; the output unit is used for comparing the voltage signal of the data node VD with the comparison control voltage NBIAS and outputting data.
The comparison path A module comprises a fifth PMOS tube P5, and the comparison path B module comprises a first NMOS tube N1; the grid electrode of the fifth PMOS tube P5 is a control end of the comparison passage A module and is connected with the data node VD; the drain electrode of the fifth PMOS tube P5 is connected with the power supply voltage; the source electrode of the fifth PMOS tube P5 is connected with the drain electrode of the first NMOS tube N1 to serve as an output end DOUT of the output unit, the source electrode of the first NMOS tube N1 is grounded, and the grid electrode of the first NMOS tube N1 is the control end of the comparison passage B module.
The first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel; the second PRE-charging unit is connected between the power supply voltage and the current compensation unit, the control end of the second PRE-charging unit is connected with the PRE-charging control voltage PRE, and the second PRE-charging unit is used for charging the first charging and discharging unit in the PRE-charging stage; the first charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The second pre-charging unit comprises a first PMOS tube P1; the grid of the first PMOS tube P1 is the control end of the second pre-charging unit, the source electrode of the first PMOS tube P1 is connected with the power supply voltage, and the drain electrode of the first PMOS tube P1 is connected with the current compensation unit and the first charging and discharging unit. The second precharge unit further includes: and one end of the first capacitor C1 is connected with the drain electrode of the first PMOS tube P1, and the other end of the first capacitor C1 is grounded.
The current compensation unit comprises a fourth PMOS tube P4, wherein the grid electrode of the fourth PMOS tube P4 is a control end of the current compensation unit and is connected with a compensation control voltage PBIAS; the source electrode of the fourth PMOS tube P4 is connected with the drain electrode of the first PMOS tube P1; the drain electrode of the fourth PMOS tube P4 is connected with the data node VD.
The bit line adjusting unit comprises a second NMOS tube N2, wherein the grid electrode of the second NMOS tube N2 is the control end of the bit line adjusting unit and is connected with the clamping voltage VCLAMP; the source electrode of the second NMOS tube N2 is connected with the bit line node BL of the memory cell; the drain electrode of the second NMOS transistor N2 is connected with the data node VD. The clamping voltage VCLAMP is kept unchanged, and the on-off of the second NMOS tube N2 is controlled through the change of the voltage of the bit line node BL of the memory cell; when the voltage of the bit line node BL is low level, the second NMOS tube N2 is conducted; when the voltage of the bit line node BL is high, the second NMOS transistor N2 is turned off.
The working process of the charge transfer type sensitive amplifier of the embodiment of the invention comprises the following steps:
a first phase, a precharge phase: the PRE-charge control voltage PRE is set to be low level, the first PMOS tube P1 and the third PMOS tube P3 are conducted, the power supply voltage is electrified to the data node VD through the third PMOS tube P3, and the power supply voltage charges the first capacitor C1 through the first PMOS tube P1.
A second stage, a comparison stage: the PRE-charge control voltage PRE is set to be high level, the first PMOS tube P1 and the third PMOS tube P3 are turned off, and the first capacitor C1 is charged to the power supply voltage in the PRE-charge stage due to the fact that the first PMOS tube P1 charges the first capacitor C1, so that the first capacitor C1 keeps supplying power to the data node VD with the power supply voltage in the comparison stage; so that the fourth PMOS tube P4 works normally;
when the memory cell is an erase cell (e cell), the e cell has a current, and in the comparison stage, the voltage of the bit line node BL is reduced, so that the voltage of the data node VD is reduced, and the output circuit outputs high level data.
When the memory cell is a write cell (p cell), the p cell has no current, the voltage of the data node VD still keeps the power voltage VDD unchanged, and the output circuit outputs low level data.
Example 3:
referring to fig. 2 and 3, the present embodiment is based on embodiment 1
The first pre-charging unit comprises a third PMOS tube P3; the grid electrode of the third PMOS tube P3 is a control end of the first pre-charging unit, the source electrode of the third PMOS tube P3 is connected with a power supply voltage, and the drain electrode of the third PMOS tube P3 is connected with a data node VD.
An output unit comprising: the control end of the comparison passage A module is connected with the data node VD; the control end of the comparison path B module is connected with the comparison control voltage NBIAS; the output unit is used for comparing the voltage signal of the data node VD with the comparison control voltage NBIAS and outputting data.
The comparison path A module comprises a fifth PMOS tube P5, and the comparison path B module comprises a first NMOS tube N1; the grid electrode of the fifth PMOS tube P5 is a control end of the comparison passage A module and is connected with the data node VD; the source electrode of the fifth PMOS tube P5 is connected with the drain electrode of the first NMOS tube N1 to serve as the output end of the output unit, the source electrode of the first NMOS tube N1 is grounded, and the grid electrode of the first NMOS tube N1 is the control end of the comparison passage B module.
The first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel; the second PRE-charging unit is connected between the power supply voltage and the current compensation unit, the control end of the second PRE-charging unit is connected with the PRE-charging control voltage PRE, and the second PRE-charging unit is used for charging the first charging and discharging unit in the PRE-charging stage; the first charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The second pre-charging unit comprises a first PMOS tube P1; the grid of the first PMOS tube P1 is the control end of the second pre-charging unit, the source electrode of the first PMOS tube P1 is connected with the power supply voltage, and the drain electrode of the first PMOS tube P1 is connected with the current compensation unit and the first charging and discharging unit. The first charge and discharge unit further includes: and one end of the first capacitor C1 is connected with the drain electrode of the first PMOS tube P1, and the other end of the first capacitor C1 is grounded.
And a second voltage holding unit connected between the power supply voltage and the output unit for charging in the precharge phase and discharging in the comparison phase. The second voltage holding unit includes: the third pre-charging unit and the second charging and discharging unit are connected in parallel; the third PRE-charging unit is connected between the power supply voltage and the output unit, the control end of the third PRE-charging unit is connected with the PRE-charging control voltage PRE, and the third PRE-charging unit is used for charging the second charging and discharging unit in the PRE-charging stage; the second charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The third pre-charging unit comprises a second PMOS tube; the grid electrode of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit. The second charge-discharge unit comprises a second capacitor C2, one end of the second capacitor C2 is connected with the drain electrode of the second PMOS tube, and the other end of the second capacitor C2 is grounded.
The current compensation unit comprises a fourth PMOS tube P4, wherein the grid electrode of the fourth PMOS tube P4 is a control end of the current compensation unit and is connected with a compensation control voltage PBIAS; the source electrode of the fourth PMOS tube P4 is connected with the drain electrode of the first PMOS tube P1; the drain electrode of the fourth PMOS tube P4 is connected with the data node VD.
The bit line adjusting unit comprises a second NMOS tube N2, wherein the grid electrode of the second NMOS tube N2 is the control end of the bit line adjusting unit and is connected with the clamping voltage VCLAMP; the source electrode of the second NMOS tube N2 is connected with the bit line node BL of the memory cell; the drain electrode of the second NMOS transistor N2 is connected with the data node VD. The clamping voltage VCLAMP is kept unchanged, and the on-off of the second NMOS tube N2 is controlled through the change of the voltage of the bit line node BL of the memory cell; when the voltage of the bit line node BL is low level, the second NMOS tube N2 is conducted; when the voltage of the bit line node BL is high, the second NMOS transistor N2 is turned off.
It should be noted that, according to the capacitance value C of the first capacitor C1 in the above embodiment at the time of design 1 The method comprises the following steps:capacitance C of the second capacitor C2 2 The method comprises the following steps: />
Wherein t is 1 To compare the phase times, I cell For the current of the memory cell, V clamp For the clamping voltage VCLAMP, I n1 Is the current of the first NMOS transistor N1.
The working process of the charge transfer type sensitive amplifier of the embodiment of the invention comprises the following steps:
a first phase, a precharge phase: the PRE-charge control voltage PRE is set to be low level, the first PMOS tube P1, the second PMOS tube and the third PMOS tube P3 are conducted, the power supply voltage is electrified to the data node VD through the third PMOS tube P3, the power supply voltage charges the first capacitor C1 through the first PMOS tube P1, and the power supply voltage charges the second capacitor C2 through the second PMOS tube.
A second stage, a comparison stage: the PRE-charge control voltage PRE is set to be high level, the first PMOS tube P1, the second PMOS tube and the third PMOS tube P3 are turned off, and the first capacitor C1 is charged to the power supply voltage in the PRE-charge stage due to the fact that the first PMOS tube P1 charges the first capacitor C1, so that the first capacitor C1 keeps supplying power to the data node VD with the power supply voltage in the comparison stage; so that the fourth PMOS tube P4 works normally; because the second PMOS tube charges the second capacitor C2 in the pre-charging stage and charges to the power supply voltage, the second capacitor C2 keeps supplying power to the fifth PMOS tube P5 with the power supply voltage in the comparison stage, so that the output unit works normally;
when the memory cell is an erase cell (e cell), the e cell has a current, and in the comparison stage, the voltage of the bit line node BL is reduced, so that the voltage of the data node VD is reduced, and the output circuit outputs high level data.
When the memory cell is a write cell (p cell), the p cell has no current, the voltage of the data node VD still keeps the power voltage VDD unchanged, and the output circuit outputs low level data.
The present embodiment alternately energizes the data node VD in the precharge phase and the comparison phase by the first precharge unit and the first voltage holding unit, and since the first voltage holding unit is capable of self-charging and charging to the power supply voltage in the precharge phase, and the second voltage holding unit is capable of self-charging and charging to the power supply voltage; therefore, even if no power supply voltage is used for supplying power in the comparison stage, the current compensation unit and the output unit can still work normally, and the change of the power supply voltage of the data node VD caused by the shaking of the power supply with large amplitude and high frequency in the comparison stage can be prevented in practical application, so that the reliability of the output unit for outputting data is improved.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (9)
1. A charge transfer type sense amplifier, comprising:
the first pre-charging unit is connected between the power supply voltage and the data node, and the control end of the first pre-charging unit is connected with the pre-charging control voltage and is used for electrifying the data node in the pre-charging stage;
the output unit is used for reading the voltage signals of the data nodes and then outputting data;
a first voltage holding unit connected between the power supply voltage and the current compensation unit for charging in the precharge phase and discharging in the comparison phase;
the control end of the current compensation unit is connected with a compensation control voltage, and the output end of the first voltage holding unit is connected with the data node and is used for providing compensation current for the data node in the comparison stage;
a bit line adjustment unit connected between a bit line node of a memory unit and the data node for controlling connection between the bit line node and the data node;
the first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel;
the second pre-charging unit is connected between the power supply voltage and the current compensation unit, the control end of the second pre-charging unit is connected with the pre-charging control voltage, and the second pre-charging unit is used for charging the first charging and discharging unit in the pre-charging stage;
the first charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
2. The charge transfer type sense amplifier of claim 1 wherein the second pre-charge unit comprises a first PMOS tube;
the grid of the first PMOS tube is the control end of the second pre-charging unit, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the current compensation unit and the first charging and discharging unit.
3. The charge transfer type sense amplifier of claim 2 wherein the first charge-discharge unit comprises: and one end of the first capacitor is connected with the drain electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
4. The charge transfer type sense amplifier of claim 1, wherein the output unit comprises:
the control end of the comparison passage A module is connected with the data node;
the control end of the comparison passage B module is connected with a comparison control voltage;
the output unit is used for comparing the voltage signal of the data node with the comparison control voltage and then outputting data.
5. The charge transfer type sense amplifier of claim 1 or 4, further comprising: and a second voltage holding unit connected between the power supply voltage and the output unit for charging in the precharge phase and discharging in the comparison phase.
6. The charge transfer type sense amplifier of claim 5, wherein the second voltage holding unit comprises: the third pre-charging unit and the second charging and discharging unit are connected in parallel;
the third pre-charging unit is connected between the power supply voltage and the output unit, the control end of the third pre-charging unit is connected with the pre-charging control voltage, and the third pre-charging unit is used for charging the second charging and discharging unit in the pre-charging stage;
the second charge-discharge unit is used for discharging in the comparison stage and electrifying the current compensation unit.
7. The charge transfer type sense amplifier of claim 6 wherein the third pre-charge unit comprises a second PMOS transistor;
the grid of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit.
8. The charge transfer type sense amplifier of claim 7 wherein the second charge and discharge unit comprises a second capacitor, one end of the second capacitor is connected to the drain of the second PMOS transistor, and the other end is grounded.
9. The charge transfer type sense amplifier of claim 1 wherein the first pre-charge unit comprises a third PMOS transistor;
the grid of the third PMOS tube is the control end of the first pre-charging unit, the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the data node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010118207.4A CN111313848B (en) | 2020-02-26 | 2020-02-26 | Charge transfer type sensitive amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010118207.4A CN111313848B (en) | 2020-02-26 | 2020-02-26 | Charge transfer type sensitive amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111313848A CN111313848A (en) | 2020-06-19 |
| CN111313848B true CN111313848B (en) | 2023-08-22 |
Family
ID=71147773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010118207.4A Active CN111313848B (en) | 2020-02-26 | 2020-02-26 | Charge transfer type sensitive amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111313848B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863055B (en) * | 2020-08-13 | 2022-10-28 | 安徽大学 | Sense amplifier, memory and control method of sense amplifier |
| US11887655B2 (en) | 2020-08-13 | 2024-01-30 | Anhui University | Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches |
| US11929111B2 (en) | 2020-09-01 | 2024-03-12 | Anhui University | Sense amplifier, memory and method for controlling sense amplifier |
| US11862285B2 (en) | 2020-09-01 | 2024-01-02 | Anhui University | Sense amplifier, memory and control method of sense amplifier |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217059A (en) * | 2007-12-26 | 2008-07-09 | 中国航天时代电子公司第七七一研究所 | Self-timing SRAM access control circuit |
| CN101546604A (en) * | 2009-04-29 | 2009-09-30 | 深圳市远望谷信息技术股份有限公司 | Sensitive amplifier applied to EEPROM |
| CN101872643A (en) * | 2009-04-22 | 2010-10-27 | 索尼公司 | Variable-resistance memory device and method of operating thereof |
| CN101916583A (en) * | 2010-07-30 | 2010-12-15 | 上海宏力半导体制造有限公司 | Sense amplifier and memory |
| CN102013268A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Bit line adjusting method and unit as well as sensitive amplifier |
| CN203858864U (en) * | 2014-05-12 | 2014-10-01 | 北京兆易创新科技股份有限公司 | Pre-charging system of bit line in memorizer |
| CN107195319A (en) * | 2017-05-23 | 2017-09-22 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifier circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050264322A1 (en) * | 2004-05-25 | 2005-12-01 | Takaaki Nakazato | SOI sense amplifier with pre-charge |
| KR102563767B1 (en) * | 2017-02-24 | 2023-08-03 | 삼성전자주식회사 | Memory device and method for operating memory device |
-
2020
- 2020-02-26 CN CN202010118207.4A patent/CN111313848B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217059A (en) * | 2007-12-26 | 2008-07-09 | 中国航天时代电子公司第七七一研究所 | Self-timing SRAM access control circuit |
| CN101872643A (en) * | 2009-04-22 | 2010-10-27 | 索尼公司 | Variable-resistance memory device and method of operating thereof |
| CN101546604A (en) * | 2009-04-29 | 2009-09-30 | 深圳市远望谷信息技术股份有限公司 | Sensitive amplifier applied to EEPROM |
| CN102013268A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Bit line adjusting method and unit as well as sensitive amplifier |
| CN101916583A (en) * | 2010-07-30 | 2010-12-15 | 上海宏力半导体制造有限公司 | Sense amplifier and memory |
| CN203858864U (en) * | 2014-05-12 | 2014-10-01 | 北京兆易创新科技股份有限公司 | Pre-charging system of bit line in memorizer |
| CN107195319A (en) * | 2017-05-23 | 2017-09-22 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111313848A (en) | 2020-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111313848B (en) | Charge transfer type sensitive amplifier | |
| CN111383674B (en) | Sense amplifier for compensating SONOS memory | |
| US6487103B2 (en) | Data read-out circuit, data read-out method, and data storage device | |
| EP1739682B1 (en) | Voltage supply circuit and semiconductor memory | |
| US6937088B2 (en) | Potential generating circuit capable of correctly controlling output potential | |
| KR100221939B1 (en) | Semiconductor memory device and high-voltage switching circuit | |
| JP4927356B2 (en) | Semiconductor device | |
| CN100538901C (en) | The semiconductor sensing circuit | |
| JP3782227B2 (en) | Semiconductor memory device | |
| US20120033506A1 (en) | Semiconductor device | |
| US20070097769A1 (en) | Semiconductor memory | |
| CN111383696B (en) | Data reading circuit of embedded flash memory unit | |
| EP1493158A1 (en) | Single-ended current sense amplifier | |
| KR20060118733A (en) | Temperature compensation oscillator of semiconductor device | |
| CN105185404B (en) | charge transfer type sense amplifier | |
| US8553487B2 (en) | Internal power supply circuit, semiconductor device, and manufacturing method of semiconductor device | |
| KR100848418B1 (en) | Ferroelectric memory device, electronic apparatus, and ferroelectric memory device driving method | |
| KR100925368B1 (en) | Circuit for providing an operation voltage of a sense amplifier and driving method thereof | |
| US7872913B2 (en) | Nonvolatile analog memory | |
| US7859135B2 (en) | Internal power supply circuit having a cascode current mirror circuit | |
| US7746161B2 (en) | Semiconductor integrated circuit device having internal voltage generating circuit | |
| CN111583975B (en) | Sensitive amplifier | |
| CN102290087A (en) | Memory and sensitive amplifier | |
| CN107665718B (en) | Charge transfer type sense amplifier | |
| JP4374539B2 (en) | Ferroelectric memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |