CN111313848A - Charge transfer type sense amplifier - Google Patents
Charge transfer type sense amplifier Download PDFInfo
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- CN111313848A CN111313848A CN202010118207.4A CN202010118207A CN111313848A CN 111313848 A CN111313848 A CN 111313848A CN 202010118207 A CN202010118207 A CN 202010118207A CN 111313848 A CN111313848 A CN 111313848A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge transfer type sense amplifier, including: the first pre-charging unit is connected between a power supply voltage and a data node, and a control end of the first pre-charging unit is connected with a pre-charging control voltage and used for electrifying the data node in a pre-charging stage; the output unit is used for reading the voltage signal of the data node and then outputting data; a first voltage holding unit between the power voltage and the current compensation unit for charging in a pre-charge stage and discharging in a comparison stage; the control end of the current compensation unit is connected with the compensation control voltage, and the output end of the voltage holding unit is connected with the data node and used for providing compensation current for the data node in the comparison stage; and a bit line adjusting unit for controlling connection between the bit line node and the data node. The invention can maintain the normal function of the circuit through the voltage holding unit when the circuit is disconnected with the power supply in the comparison stage, thereby improving the reliability of the sensitive amplifier.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge transfer type sense amplifier.
Background
The charge transfer type sense amplifier can amplify a weak electric charge amount to output a low-impedance point data signal.
As shown in fig. 1, a circuit diagram of a charge transfer type sense amplifier in the related art is provided, which includes:
the gate of the NMOS transistor n0 is connected with a clamping voltage VCLA and keeps the opening state; the source is connected to a bit line node B through which a memory cell (cell) is connected.
The PMOS transistor p0 has a gate connected to the precharge voltage PR, a source connected to the power supply voltage VDD, and a drain connected to the drain of the NMOS transistor n0 and to the data node D.
The PMOS transistor p1 has a gate connected to a control signal PBI, which is a fixed voltage, such as a bias voltage through a current mirror.
And an output unit 101, wherein a first input terminal of the output unit 101 is connected to the data node D, and a second input terminal is connected to a reference voltage NBI, and the reference voltage NBI is a fixed voltage, such as a bias voltage through current mirroring. The output terminal of the output unit 101 serves as an output terminal DOUT of the charge transfer type sense amplifier, and an output signal is formed at the output terminal DOUT by comparing the data node D with the reference voltage NBI.
In practical applications, the related art often encounters the situation of electrical pulses, that is, the power voltage VDD has large-amplitude high-frequency jitter (for example, 20MHz amplitude is 5V to 2V), so that the sense amplifier reads out erroneous data due to large current changes, and the circuit reliability is low.
Disclosure of Invention
The invention provides a charge transfer type sensitive amplifier, which can solve the problem that the sensitive amplifier in the related technology reads wrong data due to the large current change.
A charge transfer type sense amplifier comprising:
the first pre-charging unit is connected between a power supply voltage and a data node, and a control end of the first pre-charging unit is connected with a pre-charging control voltage and used for electrifying the data node in a pre-charging stage;
the output unit is used for reading the voltage signal of the data node and then outputting data;
a first voltage holding unit connected between the power voltage and the current compensation unit for charging in a pre-charge stage and discharging in a comparison stage;
the control end of the current compensation unit is connected with a compensation control voltage, and the output end of the voltage holding unit is connected with the data node and used for providing compensation current for the data node in a comparison stage;
a bit line adjustment unit connected between a bit line node of a memory cell and the data node for controlling a connection between the bit line node and the data node.
Optionally, the first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel;
the second pre-charging unit is connected between the power supply voltage and the current compensation unit, a control end is connected with the pre-charging control voltage, and the second pre-charging unit is used for charging the first charging and discharging unit in the pre-charging stage;
the first charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
Optionally, the second pre-charge unit includes a first PMOS transistor;
the grid electrode of the first PMOS tube is the control end of the second pre-charging unit, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the current compensation unit and the first charging and discharging unit.
Optionally, the first charge and discharge unit further includes: and one end of the first capacitor is connected with the drain electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
Optionally, the output unit includes:
a comparison path A module, wherein the control end of the comparison path A module is connected with the data node;
the control end of the comparison path B module is connected with a comparison control voltage;
the output unit is used for comparing the voltage signal of the data node with the comparison control voltage and then outputting data.
Optionally, the charge transfer type sense amplifier further includes: a second voltage holding unit connected between the power supply voltage and the output unit, for charging in the pre-charge phase and discharging in the comparison phase.
Optionally, the second voltage holding unit includes: the third pre-charging unit and the second charging and discharging unit are connected in parallel;
the third pre-charging unit is connected between the power supply voltage and the output unit, a control end is connected with the pre-charging control voltage, and the third pre-charging unit is used for charging the second charging and discharging unit in the pre-charging stage;
the second charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
Optionally, the third pre-charge unit includes a second PMOS transistor;
the grid electrode of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit.
Optionally, the second charge and discharge unit includes a second capacitor, one end of the second capacitor is connected to the drain of the second PMOS transistor, and the other end of the second capacitor is grounded.
Optionally, the first pre-charge unit includes a third PMOS transistor;
the grid electrode of the third PMOS tube is the control end of the first pre-charging unit, the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the data node.
The technical scheme of the invention at least comprises the following advantages: the data node VD is powered on alternately in the pre-charging stage and the comparing stage through the first pre-charging unit and the first voltage holding unit, and the first voltage holding unit can be self-charged and charged to the power supply voltage in the pre-charging stage, so that the current compensation unit can still normally work even if no power supply voltage is supplied in the comparing stage, the situation that the power supply voltage of the data node VD is changed due to the fact that the power supply shakes at a high frequency in the comparing stage in a large range in practical application can be prevented, and the reliability of data output by the output unit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a circuit diagram of a charge transfer type sense amplifier in the related art.
Fig. 2 is a timing diagram of a charge transfer type sense amplifier in the present invention.
Fig. 3 is a circuit diagram of an embodiment of a charge transfer type sense amplifier in the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
the present embodiment provides a charge transfer type sense amplifier including:
the first PRE-charging unit is connected between a power supply voltage and a data node VD, and a control end of the first PRE-charging unit is connected with a PRE-charging control voltage PRE and used for electrifying the data node VD in a PRE-charging stage;
the precharge control voltage PRE can control the charge transfer type sense amplifier to be in the precharge stage by changing the voltage value. Referring to fig. 3, the charge transfer type sense amplifier is in the precharge phase when the precharge control voltage PRE is low, and in the comparison phase when the precharge control voltage PRE is high after the precharge phase is finished.
And the output unit is used for reading the voltage signal of the data node VD and then outputting data.
A first voltage holding unit connected between the power voltage and the current compensation unit for charging in a pre-charge stage and discharging in a comparison stage; when discharging, the first voltage holding unit can supply power to the current compensation unit, so that the current compensation unit can normally work even if the current compensation unit is not supplied with power supply voltage in the comparison stage.
The control end of the current compensation unit is connected with a compensation control voltage PBIAS, and the output end of the voltage holding unit is connected with a data node VD and used for providing compensation current for the data node VD at a comparison stage; when the current compensation unit normally operates, the compensation current can be supplied to the data node VD.
And the bit line adjusting unit is connected between a bit line node BL of the memory cell and the data node VD and is used for controlling the connection between the bit line node BL and the data node VD.
It is to be explained that during the pre-charge phase the first pre-charge unit is able to energize the data node VD and the first voltage holding unit is able to charge, whereas during the comparison phase the first pre-charge unit is disconnected from the supply voltage, the first voltage holding unit is disconnected from the supply voltage and the charge amount charged during the pre-charge phase is able to be discharged.
The working process of the charge transfer type sensitive amplifier comprises the following steps:
first phase, precharge phase: the PRE-charging control voltage PRE is set to be a low level, and the first PRE-charging unit is used for electrifying the data node VD, so that the data node VD is charged to a power supply voltage; the first voltage holding unit performs self-charging so that the first voltage holding unit is charged to the power supply voltage.
The second stage, the comparison stage: the precharge control voltage PRE is set to be a high level, the first precharge unit is disconnected from the power supply voltage, the data node VD is stopped being electrified, and meanwhile, the first voltage holding unit is self-charged in the precharge stage and charged to the power supply voltage, so that the first voltage holding unit is kept supplying power to the data node VD with the power supply voltage in the comparison stage;
when the memory cell is an erase cell (e-cell), the e-cell has a current, and in the comparison stage, the voltage of the bit line node BL is decreased, so that the voltage of the data node VD is decreased, and the output circuit outputs high-level data.
When the memory cell is a write cell (program cell, pcell), the pcell has no current, the voltage of the data node VD still maintains the power voltage VDD, and the output circuit outputs low level data.
In the embodiment, the data node VD is powered on alternately in the pre-charge stage and the comparison stage through the first pre-charge unit and the first voltage holding unit, and the first voltage holding unit can be self-charged and charged to the power voltage in the pre-charge stage, so that the current compensation unit can still normally operate even if no power voltage is supplied in the comparison stage, and the power supply voltage to the data node VD is prevented from changing due to the large-amplitude high-frequency jitter of the power supply in the comparison stage in practical application, thereby improving the reliability of the output data of the output unit.
Example 2:
this example is based on example 1
A first precharge unit including a third PMOS transistor P3; the gate of the third PMOS transistor P3 is the control terminal of the first precharge unit, the source of the third PMOS transistor P3 is connected to the power voltage, and the drain of the third PMOS transistor P3 is connected to the data node VD.
An output unit including: the comparison access A module is connected with a data node VD at the control end; the control end of the comparison channel B module is connected with comparison control voltage NBIAS; the output unit is used for comparing the voltage signal of the data node VD with the comparison control voltage NBIAS and then outputting data.
The comparison path A module comprises a fifth PMOS transistor P5, and the comparison path B module comprises a first NMOS transistor N1; the grid electrode of the fifth PMOS pipe P5 is the control end of the comparison access A module and is connected with a data node VD; the drain electrode of the fifth PMOS pipe P5 is connected with the power supply voltage; the source of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 as the output terminal DOUT of the output unit, the source of the first NMOS transistor N1 is grounded, and the gate of the first NMOS transistor N1 is the control terminal of the comparison path B module.
The first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel; the second PRE-charging unit is connected between the power supply voltage and the current compensation unit, the control end is connected with a PRE-charging control voltage PRE, and the second PRE-charging unit is used for charging the first charging and discharging unit in a PRE-charging stage; the first charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The second precharge unit comprises a first PMOS pipe P1; the gate of the first PMOS transistor P1 is the control terminal of the second precharge unit, the source of the first PMOS transistor P1 is connected to the power voltage, and the drain of the first PMOS transistor P1 is connected to the current compensation unit and the first charge/discharge unit. The second precharge unit further includes: one end of the first capacitor C1, the first capacitor C1 is connected to the drain of the first PMOS transistor P1, and the other end is grounded.
The current compensation unit comprises a fourth PMOS tube P4, and the grid electrode of the fourth PMOS tube P4 is the control end of the current compensation unit and is connected with the compensation control voltage PBIAS; the source electrode of the fourth PMOS pipe P4 is connected with the drain electrode of the first PMOS pipe P1; the drain of the fourth PMOS transistor P4 is connected to the data node VD.
The bit line adjusting unit comprises a second NMOS transistor N2, and the grid electrode of the second NMOS transistor N2 is the control end of the bit line adjusting unit and is connected with a clamping voltage VCLAMP; the source of the second NMOS transistor N2 is connected to the bit line node BL of the memory cell; the drain of the second NMOS transistor N2 is connected to the data node VD. The clamping voltage VCLAMP is kept unchanged, and the on-off of the second NMOS transistor N2 is controlled through the change of the voltage of the bit line node BL of the memory cell; when the voltage of the bit line node BL is at a low level, the second NMOS transistor N2 is turned on; when the voltage at the bit line node BL is high, the second NMOS transistor N2 is turned off.
The working process of the charge transfer type sensitive amplifier comprises the following steps:
first phase, precharge phase: the precharge control voltage PRE is set to be a low level, the first PMOS transistor P1 and the third PMOS transistor P3 are turned on, the power supply voltage energizes the data node VD through the third PMOS transistor P3, and the power supply voltage charges the first capacitor C1 through the first PMOS transistor P1.
The second stage, the comparison stage: the precharge control voltage PRE is set to a high level, the first PMOS transistor P1 and the third PMOS transistor P3 are turned off, and since the first PMOS transistor P1 charges the first capacitor C1 in the precharge phase and charges to the power voltage, the first capacitor C1 keeps supplying power to the data node VD with the power voltage in the comparison phase; so that the fourth PMOS transistor P4 works normally;
when the memory cell is an erase cell (e-cell), the e-cell has a current, and in the comparison stage, the voltage of the bit line node BL is decreased, so that the voltage of the data node VD is decreased, and the output circuit outputs high-level data.
When the memory cell is a write cell (program cell, pcell), the pcell has no current, the voltage of the data node VD still maintains the power voltage VDD, and the output circuit outputs low level data.
Example 3:
referring to fig. 2 and 3, the present embodiment is based on embodiment 1
A first precharge unit including a third PMOS transistor P3; the gate of the third PMOS transistor P3 is the control terminal of the first precharge unit, the source of the third PMOS transistor P3 is connected to the power voltage, and the drain of the third PMOS transistor P3 is connected to the data node VD.
An output unit including: the comparison access A module is connected with a data node VD at the control end; the control end of the comparison channel B module is connected with comparison control voltage NBIAS; the output unit is used for comparing the voltage signal of the data node VD with the comparison control voltage NBIAS and then outputting data.
The comparison path A module comprises a fifth PMOS transistor P5, and the comparison path B module comprises a first NMOS transistor N1; the grid electrode of the fifth PMOS pipe P5 is the control end of the comparison access A module and is connected with a data node VD; the source of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 as the output terminal of the output unit, the source of the first NMOS transistor N1 is grounded, and the gate of the first NMOS transistor N1 is the control terminal of the comparison path B module.
The first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel; the second PRE-charging unit is connected between the power supply voltage and the current compensation unit, the control end is connected with a PRE-charging control voltage PRE, and the second PRE-charging unit is used for charging the first charging and discharging unit in a PRE-charging stage; the first charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The second precharge unit comprises a first PMOS pipe P1; the gate of the first PMOS transistor P1 is the control terminal of the second precharge unit, the source of the first PMOS transistor P1 is connected to the power voltage, and the drain of the first PMOS transistor P1 is connected to the current compensation unit and the first charge/discharge unit. The first charge and discharge unit further includes: one end of the first capacitor C1, the first capacitor C1 is connected to the drain of the first PMOS transistor P1, and the other end is grounded.
And a second voltage holding unit connected between the power voltage and the output unit, for charging in a pre-charge stage and discharging in a comparison stage. The second voltage holding unit includes: the third pre-charging unit and the second charging and discharging unit are connected in parallel; the third PRE-charging unit is connected between the power supply voltage and the output unit, the control end is connected with a PRE-charging control voltage PRE, and the third PRE-charging unit is used for charging the second charging and discharging unit in a PRE-charging stage; the second charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
The third pre-charging unit comprises a second PMOS tube; the grid electrode of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit. The second charge and discharge unit comprises a second capacitor C2, one end of the second capacitor C2 is connected with the drain of the second PMOS tube, and the other end is grounded.
The current compensation unit comprises a fourth PMOS tube P4, and the grid electrode of the fourth PMOS tube P4 is the control end of the current compensation unit and is connected with the compensation control voltage PBIAS; the source electrode of the fourth PMOS pipe P4 is connected with the drain electrode of the first PMOS pipe P1; the drain of the fourth PMOS transistor P4 is connected to the data node VD.
The bit line adjusting unit comprises a second NMOS transistor N2, and the grid electrode of the second NMOS transistor N2 is the control end of the bit line adjusting unit and is connected with a clamping voltage VCLAMP; the source of the second NMOS transistor N2 is connected to the bit line node BL of the memory cell; the drain of the second NMOS transistor N2 is connected to the data node VD. The clamping voltage VCLAMP is kept unchanged, and the on-off of the second NMOS transistor N2 is controlled through the change of the voltage of the bit line node BL of the memory cell; when the voltage of the bit line node BL is at a low level, the second NMOS transistor N2 is turned on; when the voltage at the bit line node BL is high, the second NMOS transistor N2 is turned off.
Note that, the capacitance value C of the first capacitor C1 in the above embodiment is designed according to the design1Comprises the following steps:
capacitance value C of second capacitor C22Comprises the following steps:
wherein, t1To compare the time of the phases, IcellIs the current, V, of the memory cellclampTo clamp the voltage VCLAMP, In1Is the current of the first NMOS transistor N1.
The working process of the charge transfer type sensitive amplifier comprises the following steps:
first phase, precharge phase: the PRE-charging control voltage PRE is set to be at a low level, the first PMOS tube P1, the second PMOS tube and the third PMOS tube P3 are conducted, the power supply voltage energizes the data node VD through the third PMOS tube P3, the power supply voltage charges the first capacitor C1 through the first PMOS tube P1, and the power supply voltage charges the second capacitor C2 through the second PMOS tube.
The second stage, the comparison stage: the precharge control voltage PRE is set to be a high level, the first PMOS transistor P1, the second PMOS transistor P3 and the third PMOS transistor P3 are turned off, and since the first PMOS transistor P1 charges the first capacitor C1 in the precharge stage and charges to the power voltage, the first capacitor C1 keeps supplying power to the data node VD with the power voltage in the comparison stage; so that the fourth PMOS transistor P4 works normally; since the second PMOS transistor charges the second capacitor C2 to the power voltage during the pre-charge phase, the second capacitor C2 keeps supplying power to the fifth PMOS transistor P5 at the power voltage during the comparison phase, so that the output unit operates normally;
when the memory cell is an erase cell (e-cell), the e-cell has a current, and in the comparison stage, the voltage of the bit line node BL is decreased, so that the voltage of the data node VD is decreased, and the output circuit outputs high-level data.
When the memory cell is a write cell (program cell, pcell), the pcell has no current, the voltage of the data node VD still maintains the power voltage VDD, and the output circuit outputs low level data.
The present embodiment alternately energizes the data node VD in the precharge phase and the comparison phase by the first precharge unit and the first voltage holding unit, and since the first voltage holding unit can self-charge and charge to the power supply voltage and the second voltage holding unit can self-charge and charge to the power supply voltage in the precharge phase; therefore, even if no power supply voltage supplies power in the comparison stage, the current compensation unit and the output unit can still work normally, and the situation that the power supply voltage of the data node VD is changed due to the fact that the power supply shakes at a high frequency in the comparison stage in a large range in practical application can be prevented, so that the reliability of data output by the output unit is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A charge transfer type sense amplifier, comprising:
the first pre-charging unit is connected between a power supply voltage and a data node, and a control end of the first pre-charging unit is connected with a pre-charging control voltage and used for electrifying the data node in a pre-charging stage;
the output unit is used for reading the voltage signal of the data node and then outputting data;
a first voltage holding unit connected between the power voltage and the current compensation unit for charging in the pre-charge stage and discharging in the comparison stage;
the control end of the current compensation unit is connected with a compensation control voltage, and the output end of the voltage holding unit is connected with the data node and used for providing compensation current for the data node in the comparison stage;
a bit line adjustment unit connected between a bit line node of a memory cell and the data node for controlling a connection between the bit line node and the data node.
2. The charge transfer type sense amplifier according to claim 1, wherein the first voltage holding unit includes: the second pre-charging unit and the first charging and discharging unit are connected in parallel;
the second pre-charging unit is connected between the power supply voltage and the current compensation unit, a control end of the second pre-charging unit is connected with the pre-charging control voltage, and the second pre-charging unit is used for charging the first charging and discharging unit in the pre-charging stage;
the first charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
3. The charge transfer type sense amplifier of claim 2, wherein the second precharge unit comprises a first PMOS transistor;
the grid electrode of the first PMOS tube is the control end of the second pre-charging unit, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube is connected with the current compensation unit and the first charging and discharging unit.
4. The charge transfer type sense amplifier according to claim 3, wherein the first charge and discharge unit includes: and one end of the first capacitor is connected with the drain electrode of the first PMOS tube, and the other end of the first capacitor is grounded.
5. The charge transfer type sense amplifier according to claim 1, wherein the output unit includes:
a comparison path A module, wherein the control end of the comparison path A module is connected with the data node;
the control end of the comparison path B module is connected with a comparison control voltage;
the output unit is used for comparing the voltage signal of the data node with the comparison control voltage and then outputting data.
6. The charge transfer type sense amplifier according to claim 1 or 5, further comprising: a second voltage holding unit connected between the power supply voltage and the output unit, for charging in the pre-charge phase and discharging in the comparison phase.
7. The charge transfer type sense amplifier according to claim 6, wherein the second voltage holding unit includes: the third pre-charging unit and the second charging and discharging unit are connected in parallel;
the third pre-charging unit is connected between the power supply voltage and the output unit, a control end of the third pre-charging unit is connected with the pre-charging control voltage, and the third pre-charging unit is used for charging the second charging and discharging unit in the pre-charging stage;
the second charging and discharging unit is used for discharging in the comparison stage and electrifying the current compensation unit.
8. The charge transfer type sense amplifier of claim 7, wherein the third precharge unit comprises a second PMOS transistor;
the grid electrode of the second PMOS tube is the control end of the third pre-charging unit, the source electrode of the second PMOS tube is connected with the power supply voltage, and the drain electrode of the second PMOS tube is connected with the output unit and the second charging and discharging unit.
9. The charge transfer type sense amplifier of claim 8, wherein the second charge/discharge unit comprises a second capacitor, one end of the second capacitor is connected to the drain of the second PMOS transistor, and the other end of the second capacitor is grounded.
10. The charge transfer type sense amplifier of claim 1, wherein the first precharge unit includes a third PMOS transistor;
the grid electrode of the third PMOS tube is the control end of the first pre-charging unit, the source electrode of the third PMOS tube is connected with the power supply voltage, and the drain electrode of the third PMOS tube is connected with the data node.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863055A (en) * | 2020-08-13 | 2020-10-30 | 安徽大学 | Sense amplifier, memory and control method of sense amplifier |
| US11862285B2 (en) | 2020-09-01 | 2024-01-02 | Anhui University | Sense amplifier, memory and control method of sense amplifier |
| US11887655B2 (en) | 2020-08-13 | 2024-01-30 | Anhui University | Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches |
| US11929111B2 (en) | 2020-09-01 | 2024-03-12 | Anhui University | Sense amplifier, memory and method for controlling sense amplifier |
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| US11862285B2 (en) | 2020-09-01 | 2024-01-02 | Anhui University | Sense amplifier, memory and control method of sense amplifier |
| US11929111B2 (en) | 2020-09-01 | 2024-03-12 | Anhui University | Sense amplifier, memory and method for controlling sense amplifier |
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