CN111313393B

CN111313393B - Output circuit with electrostatic discharge protection function

Info

Publication number: CN111313393B
Application number: CN202010116151.9A
Authority: CN
Inventors: 程智修; 黄如琳; 吴嘉恩
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2016-05-03
Filing date: 2017-02-24
Publication date: 2022-07-12
Anticipated expiration: 2037-02-24
Also published as: CN107342280B; CN111313393A; CN107342280A

Abstract

The invention discloses an output circuit of a semiconductor chip, which is used for electrostatic discharge protection and comprises a first metal-oxide-semiconductor field effect transistor and a first resistor. The first mosfet includes a first terminal coupled to an output pad of the semiconductor chip, a base terminal, and a gate terminal. The first resistor is coupled between the base terminal of the first metal-oxide-semiconductor field effect transistor and a first power supply terminal.

Description

Output circuit with electrostatic discharge protection function

The application date of the original application is 2017, 2, 24, the application number of the original application is 201710104268.3, and the invention name of the original application is "output circuit with electrostatic discharge protection function".

Technical Field

The present invention relates to an output circuit of a semiconductor chip, and more particularly, to an output circuit having an Electrostatic Discharge (ESD) protection function in a semiconductor chip.

Background

As semiconductor processing technology evolves, the size of circuit elements has decreased to sub-micron levels, which has greatly increased the efficiency and speed of semiconductor chips, however, as device dimensions have decreased, the importance of reliability issues has increased. Among them, Electrostatic Discharge (ESD) is one of the most important reliability issues. Under the condition that the quantity of static electricity existing outside is the same, the tolerance to static electricity discharge is poor due to the fact that circuit components in advanced technology have small sizes. Therefore, advanced circuit elements are more susceptible to electrostatic discharge damage.

In order to solve the problem of electrostatic discharge at the output end of the chip, a current-limiting resistor can be arranged in the signal output path and connected in series with the output end. When the ESD reaches, the current-limiting resistor can block the ESD current or reduce the ESD current flowing into the internal circuit of the chip. However, under normal operation of the chip, the output signal passing through the current limiting resistor generates heat energy, which causes the operating temperature of the chip to rise. In view of this, there is a need for improvement in the art.

Disclosure of Invention

Therefore, it is a primary objective of the claimed invention to provide an output circuit on a semiconductor chip, which can provide an Electrostatic Discharge (ESD) protection function and prevent the operating temperature of the semiconductor chip from being raised due to heat energy during normal operation.

The invention discloses an output circuit of a Semiconductor chip, which is used for electrostatic discharge protection and comprises a first Metal Oxide Semiconductor Transistor (MOS Transistor) and a first resistor. The first mosfet includes a first terminal coupled to an output pad (output pad) of the semiconductor chip, a base (bulk) terminal, and a gate (gate) terminal. The first resistor is coupled between the base terminal of the first metal-oxide-semiconductor field effect transistor and a first power supply terminal.

The invention also discloses an output circuit of the semiconductor chip, which is used for performing electrostatic discharge protection and comprises a transmission gate (transmission gate) and a first resistor. The transmission gate is coupled to an output pad of the semiconductor chip and comprises a first metal oxide semiconductor field effect transistor and a second metal oxide semiconductor field effect transistor. The first MOSFET comprises a first terminal, a base terminal and a gate terminal, wherein the first terminal is coupled to the output pad. The second MOSFET comprises a first terminal, a base terminal and a gate terminal, wherein the first terminal is coupled to the output pad. The first resistor is coupled between the base terminal of the first metal-oxide-semiconductor field effect transistor and a first power supply terminal.

The invention also discloses an output circuit of the semiconductor chip, which is used for performing electrostatic discharge protection and comprises an output buffer and a first resistor. The output buffer is coupled to an output pad of the semiconductor chip and comprises a first metal oxide semiconductor field effect transistor and a second metal oxide semiconductor field effect transistor. The first MOSFET comprises a first terminal, a base terminal and a gate terminal, wherein the first terminal is coupled to the output pad. The second MOSFET comprises a first terminal, a base terminal and a gate terminal, wherein the first terminal is coupled to the output pad. The first resistor is coupled between the base terminal of the first metal oxide semiconductor field effect transistor and a first power supply terminal.

Drawings

Fig. 1A and 1B are schematic diagrams of a general circuit structure of an output circuit of a semiconductor chip.

Fig. 2A and 2B are schematic diagrams illustrating detailed operations of the output circuit of fig. 1A and 1B.

Fig. 3A and 3B are schematic diagrams of an output circuit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of another output circuit according to an embodiment of the invention.

FIG. 5 is a diagram of another output circuit according to an embodiment of the present invention.

Fig. 6A and 6B are schematic diagrams of a general circuit structure of an output circuit not including a switch.

Fig. 7A and 7B are schematic diagrams of an output circuit according to an embodiment of the invention.

Fig. 8 is a schematic diagram of an output circuit according to an embodiment of the invention.

Fig. 9 is a schematic diagram of an output circuit according to an embodiment of the invention.

Wherein the reference numerals are as follows:

10. 30, 40, 50, 60, 70, 80, 90 output circuit

102 output buffer

104 switching device

106 output pad

R _ CL, R _ CL', R _ CLP and R _ CLN current limiting resistors

ESD1 and ESD2 electrostatic discharge protection unit

VDD system power supply terminal

VSS system ground terminal

P-SW, P1, P2P type metal oxide semiconductor field effect transistor

N-SW, N1, N2N type metal oxide semiconductor field effect transistor

VD1, VS1 power supply terminal

802. 902 pull-up circuit

804. 904 pull-down circuit

SA, SB, SC signals

Detailed Description

Referring to fig. 1A and 1B, fig. 1A and 1B are schematic diagrams illustrating a general circuit structure of an output circuit 10 of a semiconductor chip. The output circuit 10 includes an output buffer 102, a switch 104, an output pad (output pad)106, and a current limiting resistor R _ CL. An Electrostatic Discharge (ESD) protection unit ESD1 and ESD2 may not be included in the output circuit 10, but are shown in fig. 1A and 1B for illustrating the path of the Electrostatic Discharge current or charge. The output Circuit 10 may be used in a panel driver Integrated Circuit (IC) for outputting data voltages to a panel. The output buffer 102 may be an operational amplifier (op amp). The data voltage is output to the output pad 106 through the switch 104, and the switch 104 can control the on/off of the output path of the data voltage, and may be composed of a transmission gate (transmission gate) including a P-type Metal Oxide Semiconductor Transistor (PMOS Transistor) and an N-type Metal Oxide Semiconductor Transistor (NMOS Transistor). The output pad 106 may be used as an output interface of the output circuit 10 for connecting external components (e.g., panels). The current limiting resistor R _ CL is disposed on the output path between the output buffer 102 and the output pad 106, and is used to prevent the esd current from entering the internal circuit of the semiconductor chip or to reduce the esd current entering the internal circuit. The ESD protection cells ESD1 and ESD2 provide a conduction path for ESD current, so as to improve the ESD protection efficiency of the output circuit 10.

FIG. 1A shows an electrostatic discharge phase in which electrostatic discharge energy is applied to the output pad 106. With the common operation of the current limiting resistor R _ CL and the ESD protection units ESD1 and ESD2, the current generated by the ESD applied to the output pad 106 can flow through the ESD protection unit ESD1 to the system power supply terminal VDD or flow from the system ground terminal VSS through the ESD protection unit ESD 2. In this case, no current or only a small amount of current flows into the output buffer 102, and the current limiting resistor R _ CL can protect the circuit components inside the semiconductor chip from being burned by the esd current.

Fig. 1B shows a normal operation of the semiconductor chip, in which the output circuit 10 outputs the data voltage through the output pad 106. For example, when the output circuit 10 for a source driving device outputs a data voltage, a charging current flows from the output buffer 102 to the output pad 106 if the current data voltage is higher than the previous data voltage, and a discharging current flows from the output pad 106 to the output buffer 102 if the current data voltage is lower than the previous data voltage. In the case where the charging and discharging currents are both lost through the current limiting resistor R _ CL, the driving capability of the output circuit 10 is reduced due to the power loss of the current limiting resistor R _ CL, and the lost power is converted into heat energy, which increases the operating temperature of the semiconductor chip. Since a source driver often includes a large number of output circuits (each having a structure such as the output circuit 10), the large number of current limiting resistors in the large number of output circuits will greatly increase the operating temperature.

Referring to fig. 2A and 2B, fig. 2A and 2B are schematic diagrams illustrating a detailed operation of the output circuit 10 of fig. 1A and 1B. More specifically, fig. 2A shows a current path during an electrostatic discharge stage, and fig. 2B shows a current path during a normal operation of the semiconductor chip.

For convenience of illustration, fig. 2A only shows the switch 104, the output pad 106, the current limiting resistor R _ CL, and the ESD protection units ESD1 and ESD 2. The switch 104 may be composed of a P-type MOSFET P-SW and an N-type MOSFET N-SW, and is implemented by a transmission gate connection. A P-N junction (which may be considered a diode) exists between the end of the pmos P-SW near the output pad 106 (which may be the source or drain end of the pmos P-SW) and the base (bulk) end of the pmos P-SW, while a P-N junction exists between the base end of the nmos N-SW and the end of the nmos N-SW near the output pad 106 (which may be the source or drain end of the nmos N-SW). In the ESD phase, when an ESD with a positive polarity is applied to the output pad 106, an ESD current is generated on the output pad 106. In the case of the current limiting resistor R _ CL, most of the ESD current is conducted to the system power supply VDD through the ESD protection unit ESD1, and only a few of the ESD current flows to the switch 104 through the current limiting resistor R _ CL, which is conducted to the system power supply VDD through the P-N junction of the P-type MOSFET P-SW. On the other hand, when the ESD with negative polarity is applied to the output pad 106, an ESD current flowing to the output pad 106 is generated. In the case of the current limiting resistor R _ CL, most of the ESD current is introduced from the system ground VSS through the ESD protection unit ESD2, and only a few of the ESD current flows from the switch 104 through the current limiting resistor R _ CL, and the ESD current is introduced from the system ground VSS through the P-N junction of the nmos N-SW. In this case, the current limiting resistor R _ CL may limit the magnitude of the ESD current through the P-N junction to prevent the P-N junction from being burned or damaged by the ESD current.

For convenience of illustration, only the switch 104, the output pad 106 and the current limiting resistor R _ CL are shown in fig. 2B. Since the output circuit 10 is in a normal operation state to output the data voltage, the ESD protection units ESD1 and ESD2 are turned off, and therefore the ESD protection units ESD1 and ESD2 do not affect the operation of the output circuit 10, and are not shown in fig. 2B. As described above, the driving current of the output signal or data passes through the current limiting resistor R _ CL, so that the power loss on the current limiting resistor R _ CL causes the operating temperature of the semiconductor chip to increase.

Referring to fig. 3A and 3B, fig. 3A and 3B are schematic diagrams of an output circuit 30 according to an embodiment of the invention. The structure of the output circuit 30 is similar to that of the output circuit 10 in fig. 2A and 2B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 30 and the output circuit 10 is that the output circuit 30 is provided with current limiting resistors R _ CLP and R _ CLN instead of the current limiting resistor R _ CL in the output path of the output circuit 10.

As shown in fig. 3A and 3B, the drain terminal (or source terminal) of the pmos P-SW is directly coupled to the output pad 106 without passing through any resistor, and the source terminal (or drain terminal) of the nmos N-SW is directly coupled to the output pad 106 without passing through any resistor. The current limiting resistor R _ CLP is coupled to the base terminal of the PMOS transistor P-SW, and more specifically, coupled between the base terminal of the PMOS transistor P-SW and a power supply terminal VD 1. The power supply terminal VD1 can be a system power supply terminal (e.g., system power supply terminal VDD) of the semiconductor chip or any power source that can provide a voltage level greater than or equal to the source voltage and drain voltage of the PMOS transistor P-SW. The current limiting resistor R _ CLN is coupled to a base terminal of the NMOS transistor N-SW, and more particularly, coupled between the base terminal of the NMOS transistor N-SW and a power supply terminal VS 1. The power supply VS1 may be a system ground (e.g., system ground VSS) of the semiconductor chip or any voltage source that provides a voltage level less than or equal to the source and drain voltages of the NMOS transistors N-SW.

Fig. 3A shows the current path under the electrostatic discharge phase. In one embodiment, when an ESD with a positive polarity is applied to the output pad 106, an ESD current is generated on the output pad 106. In the case of the current limiting resistor R _ CLP, most of the ESD current is conducted to the system power supply terminal VDD through the ESD protection unit ESD1, and only a few of the ESD current is conducted to the power supply terminal VD1 through the P-N junction of the pmos P-SW and the current limiting resistor R _ CLP. In another embodiment, when an ESD with a negative polarity is applied to the output pad 106, an ESD current flows to the output pad 106. In the case of the current limiting resistor R _ CLN, most of the ESD current is introduced from the system ground VSS through the ESD protection unit ESD2, and only a few of the ESD current is introduced from the power supply VS1 through the P-N junction of the nmos N-SW and the current limiting resistor R _ CLN.

In this case, when the current limiting resistor R _ CLP is provided, the current flowing through the P-N junction between the drain terminal (or source terminal) and the base terminal of the PMOS transistor P-SW under the positive polarity electrostatic discharge applied to the output pad 106 is limited; when the current limiting resistor R _ CLN is provided, the current flowing through the P-N junction between the source terminal (or drain terminal) and the base terminal of the NMOS transistor N-SW under the negative electrostatic discharge applied to the output pad 106 is limited. Therefore, in the ESD stage, the current limiting resistors R _ CLP and R _ CLN coupled to the base terminal can reduce the ESD current passing through the P-N junction, thereby preventing the P-N junction from being damaged or burnt due to the ESD current. In other words, the current limiting resistors R _ CLP and R _ CLN provide esd protection efficiency equivalent to that provided by the current limiting resistor R _ CL in fig. 2A.

Fig. 3B shows a current path under normal operation of the semiconductor chip, in this case, there is no current limiting resistor in the output path of the driving current, and the driving current does not pass through the current limiting resistors R _ CLP and R _ CLN coupled to the base terminals of the pmos and nmos transistors P-SW and N-SW, so that the driving capability of the output circuit 30 will not be degraded by the current limiting resistors R _ CLP and R _ CLN. In addition, since there is no power loss in the current limiting resistors R _ CLP and R _ CLN during normal operation, the operating temperature of the semiconductor chip does not rise.

Referring to fig. 4, fig. 4 is a schematic diagram of another output circuit 40 according to an embodiment of the invention. The structure of the output circuit 40 is similar to that of the output circuit 30 in fig. 3A and 3B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 40 and the output circuit 30 is that the output circuit 40 additionally includes a current limiting resistor R _ CL' disposed in the output path between the output pad 106 and the end of the switch 104 (i.e., the transmission gate) close to the output pad 106. One end of the switch 104 near the output pad 106 is coupled to both the drain terminal (or source terminal) of the P-type mosfet P-SW and the source terminal (or drain terminal) of the N-type mosfet N-SW. The resistance of the current limiting resistor R _ CL' is smaller than the resistance of the current limiting resistor R _ CL in the output path of the output circuit 10 in fig. 2A and 2B. The additional current limiting resistor R _ CL' provides higher ESD protection capability to further reduce the ESD current flowing into the P-N junction of the P-type MOSFET P-SW and the N-type MOSFET N-SW. Because the resistance value of the current-limiting resistor R _ CL 'is smaller than that of the current-limiting resistor R _ CL in the prior art, the current-limiting resistor R _ CL' can cause lower power loss and can also achieve the effects of reducing the temperature and improving the driving capability.

Referring to fig. 5, fig. 5 is a schematic diagram of another output circuit 50 according to an embodiment of the invention. The structure of the output circuit 50 is similar to that of the output circuit 30 in fig. 3A and 3B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 50 and the output circuit 30 is that in the output circuit 50, the current limiting resistor R _ CLN is coupled between the output pad 106 and the source terminal (or drain terminal) of the NMOS transistor N-SW, rather than being coupled to the base terminal of the NMOS transistor N-SW. Similarly, the current limiting resistor R _ CLN coupled to the output pad 106 is also used to limit the current flowing through the P-N junction between the source (or drain) and base terminals of the NMOS transistor N-SW under the negative electrostatic discharge applied to the output pad 106. Since the current limiting resistor R _ CLP is still coupled to the base terminal of the pmos P-SW, the resistance of the output path of the output circuit 50 is smaller than that of the current limiting resistor R _ CL in the prior art, and in this case, the power loss of the current limiting resistor R _ CLN on the output path of the output circuit 50 is lower, and the effects of reducing the temperature and improving the driving capability can be achieved. In another embodiment, the current limiting resistor R _ CLP may be coupled to the drain terminal (or source terminal) of the P-type MOSFET P-SW, and the current limiting resistor R _ CLN may be coupled to the base terminal of the N-type MOSFET N-SW.

It is noted that the output circuit of the present invention provides an esd protection mechanism capable of reducing temperature and improving driving capability, wherein the current limiting resistor is coupled to a base terminal of a transistor in the output circuit. Those skilled in the art can make modifications or changes thereto without being limited thereto. For example, according to the contents of fig. 3A, 3B, 4 and 5 and the related descriptions, the number and arrangement of the current limiting resistors can be modified according to the system requirements, as long as there is at least one current limiting resistor coupled to the base terminal of the transistor connected to the output pad.

In another embodiment, the ESD protection mechanism of the present invention can be used in another output circuit structure without a transmission gate or a switch. Referring to fig. 6A and 6B, fig. 6A and 6B are schematic diagrams of a general circuit structure of an output circuit 60 not including a switch. The structure of the output circuit 60 is similar to that of the output circuit 10 in fig. 1A and 1B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 60 and the output circuit 10 is that there is no switch (i.e., transmission gate) in the output path of the output circuit 60. In this case, the output buffer 102 is directly connected to the current limiting resistor R _ CL.

The operation illustrated in FIGS. 6A and 6B is similar to the example of FIGS. 1A and 1B. As shown in FIG. 6A, during the ESD phase, when ESD energy is applied to the output pad 106, most of the ESD current is conducted to the system power supply terminal VDD through the ESD protection unit ESD1, or is conducted from the system ground terminal VSS through the ESD protection unit ESD 2. As shown in fig. 6B, under normal operation of the semiconductor chip, the charging and discharging current flows through the current limiting resistor R _ CL and generates power loss, in which case the driving capability of the output circuit 60 is reduced by the power loss of the current limiting resistor R _ CL, and the power loss is converted into heat energy, which causes the operating temperature of the semiconductor chip to increase.

Referring to fig. 7A and 7B, fig. 7A and 7B are schematic diagrams of an output circuit 70 according to an embodiment of the invention. The structure of the output circuit 70 is similar to that of the output circuit 60 in fig. 6A and 6B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 70 and the output circuit 60 is that the output circuit 70 is provided with current limiting resistors R _ CLP and R _ CLN instead of the current limiting resistor R _ CL in the output path of the output circuit 60.

As shown in fig. 7A and 7B, the output stage circuit of the output buffer 102 includes a pmos P1 and an nmos N1. The drain terminal of pmos P1 and nmos N1 are coupled directly to the output pad 106 without any resistor. The current limiting resistor R _ CLP is coupled between the base terminal of the P-type MOSFET P1 and a power supply terminal VD 1. The power supply terminal VD1 may be a system power supply terminal (e.g., system power supply terminal VDD) of the semiconductor chip or any voltage source that provides a voltage level greater than or equal to the source voltage and drain voltage of the pmos P1. The current limiting resistor R _ CLN is coupled between the base terminal of the NMOS transistor N1 and a power supply terminal VS 1. The power supply VS1 may be a system ground (e.g., system ground VSS) of the semiconductor chip or any voltage source that provides a voltage level less than or equal to the source voltage and drain voltage of NMOS transistor N1.

Fig. 7A shows the current path under the electrostatic discharge phase. Under the positive polarity ESD applied to the output pad 106, most of the ESD current is conducted to the system power supply terminal VDD through the ESD protection unit ESD1, and only a few ESD currents flow to the power supply terminal VD1 through the P-N junction of the PMOS transistor P1 and the current limiting resistor R _ CLP. Under negative electrostatic discharge applied to the output pad 106, most of the electrostatic discharge current is conducted from the system ground VSS through the ESD2, and only a few of the electrostatic discharge current is conducted from the power supply VS1 through the P-N junction of the nmos N1 and the current limiting resistor R _ CLN. Under this condition, under the ESD energy, the ESD current flowing through the P-N junction of the PMOS 1 and the NMOS N1 is limited, thereby preventing the P-N junction from being damaged or burnt due to the ESD current. Fig. 7B shows the current path under normal operation of the semiconductor chip, in which the driving currents (i.e. the charging current and the discharging current) do not pass through the current limiting resistors R _ CLP and R _ CLN coupled to the base terminals of the pmos transistor P1 and the nmos transistor N1, so that the driving capability of the output circuit 70 is not degraded by the current limiting resistors R _ CLP and R _ CLN. In addition, since there is no power loss in the current-limiting resistors R _ CLP and R _ CLN during normal operation, the operating temperature of the semiconductor chip does not rise.

It should be noted that, according to the above description related to fig. 4 and fig. 5, those skilled in the art should understand that the number of the current limiting resistors in the output circuit 70 and the arrangement thereof can be modified arbitrarily to meet the driving capability and esd protection requirements of the semiconductor chip. For example, in the output circuit 70, a current limiting resistor with a smaller resistance value may be additionally disposed between the output pad 106 and the output buffer 102 for providing a higher esd protection capability. In another embodiment, the current limiting resistor R _ CLN in the output circuit 70 may be replaced by a current limiting resistor coupled between the drain terminal of the NMOS transistor N1 and the output pad 106; alternatively, the current limiting resistor R _ CLP of the output circuit 70 may be replaced by a current limiting resistor coupled between the drain terminal of the PMOS transistor P1 and the output pad 106. Those skilled in the art should be able to deduce various resistor setting modes and operation modes according to the above paragraphs, which are not described herein again.

Referring to fig. 8, fig. 8 is a schematic diagram of an output circuit 80 according to an embodiment of the invention. The structure of the output circuit 80 is similar to that of the output circuit 30 in fig. 3A and 3B, and therefore similar components are denoted by the same reference numerals. The main difference between the output circuit 80 and the output circuit 30 is that the output circuit 80 additionally includes a pull-up circuit 802 and a pull-down circuit 804. For convenience of illustration, the esd protection unit is not shown in fig. 8, and the signals SA, SB and SC are from an output buffer, which is also not shown in fig. 8.

In detail, the pull-up circuit 802 is coupled to the gate terminal of the pmos P-SW, the pull-up circuit 802 may be implemented by a pmos P2, the pmos P2 is coupled between the gate terminal of the pmos P-SW and the system power supply terminal VDD, and the gate terminal of the pmos P2 is connected to the source terminal of the pmos P2. The pull-up circuit 802 may be used to control the voltage level at the gate terminal of the pmos P-SW to prevent the pmos P-SW from turning on due to the positive polarity electrostatic discharge applied to the output pad 106 when the semiconductor chip including the output circuit 80 is powered off. The pull-down circuit 804 is coupled to the gate terminal of the nmos transistor N-SW, the pull-down circuit 804 can be implemented by an nmos transistor N2, the nmos transistor N2 is coupled between the gate terminal of the nmos transistor N-SW and the system ground terminal VSS, and the gate terminal of the nmos transistor N2 is connected to the source terminal of the nmos transistor N2. The pull-down circuit 804 is used to control the voltage level of the gate terminal of the nmos fet N-SW to prevent the nmos fet N-SW from being turned on by the negative electrostatic discharge applied to the output pad 106 when the semiconductor chip is powered off.

Under normal operation of the semiconductor chip, the signals SA and SB turn on the transistors P-SW and N-SW of the transmission gate, respectively, to drive current through the transmission gate. Under the device-level ESD test, the semiconductor chip is powered off, so the signals SA and SB are floating, and the transistors P-SW and N-SW of the pass gates may be turned on or off. Because there is no current-limiting resistor on the output path, if any one of the transistors P-SW and N-SW is turned on during the esd test, the esd current can easily enter the internal circuit of the output buffer through the pass gate, causing the circuit components in the output buffer or other internal circuit components of the semiconductor chip to be damaged, and the semiconductor chip can not pass the esd test. To avoid this problem, a pull-up circuit 802 and a pull-down circuit 804 may be disposed in the output circuit 80 and coupled to the gate terminals of the PMOS transistor P-SW and the NMOS transistor N-SW, respectively. The pull-up 802 and pull-down 804 circuits ensure that the transistors P-SW and N-SW are turned off when the semiconductor chip is powered down. Therefore, when the output circuit performs the device-level ESD test, the ESD current will not pass through the channel of the transmission gate, and most of the ESD current will be conducted to the ESD protection unit (not shown in FIG. 8), and only a few of the ESD current will be conducted to the P-N junctions of the transistors P-SW and N-SW, wherein the P-N junctions can be protected by the current-limiting resistors R _ CLP and R _ CLN, so as to prevent the P-N junctions from receiving a large amount of ESD current and being burnt or damaged.

Referring to fig. 9, fig. 9 is a schematic diagram of an output circuit 90 according to an embodiment of the invention. Similar to fig. 8, fig. 9 shows a pull-up and pull-down mechanism for an output circuit configuration in which the output buffer 102 is directly connected to the output pad 106 without passing through a switch (i.e., a transmission gate), such as the configuration of the output circuit 70 in fig. 7A and 7B. In fig. 9, the circuit components are all similar to the output circuit 70 and are therefore denoted by the same symbols. A pull-up circuit 902 is coupled to the gate terminal of the pmos P1 for controlling the voltage level at the gate terminal of the pmos P1 to prevent the pmos P1 from turning on due to the positive polarity esd applied to the output pad 106 when the semiconductor chip including the output circuit 90 is powered down. The pull-down circuit 904 is coupled to the gate terminal of the nmos transistor N1, and is used to control the voltage level at the gate terminal of the nmos transistor N1, so as to prevent the nmos transistor N1 from turning on due to the negative electrostatic discharge applied to the output pad 106 when the semiconductor chip is in the power-off state. When the output circuit 90 performs the device-level esd test, the semiconductor chip is in a power-off state, and the pull-up circuit 902 and the pull-down circuit 904 can turn off the transistors P1 and N1, respectively, so as to prevent the esd current from entering the internal circuit of the output buffer 102 and causing the circuit devices in the output buffer 102 or other internal circuit devices of the semiconductor chip to be damaged. The pull-up circuit 902 and the pull-down circuit 904 of the output circuit 90 operate in a manner similar to the pull-up circuit 802 and the pull-down circuit 804 of the output circuit 80, and are not described herein again.

In summary, the present invention provides an output circuit of a semiconductor chip. The output circuit has the function of electrostatic discharge protection, and can prevent the working temperature from being increased due to heat energy generated by the loss of the current-limiting resistor when the semiconductor chip is in normal operation. In the output circuit of the present invention, a transistor is coupled to the output pad of the output circuit, and a current limiting resistor is coupled to the base terminal of the transistor, and the transistor may be included in an output switch (e.g., a transmission gate) or an output buffer. The current limiting resistor coupled to the base terminal can achieve the electrostatic discharge protection capability similar to the current limiting resistor arranged on the output path in the traditional circuit structure. The current limiting resistor is coupled to the base terminal and is not positioned on the output path, and the driving current for transmitting the data voltage cannot pass through the current limiting resistor, so that the driving capability of the output circuit is not reduced by the influence of the current limiting resistor, and the semiconductor chip does not have any power loss on the current limiting resistor during normal operation, thereby reducing the heat energy and the working temperature of the semiconductor chip.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An output circuit in a semiconductor chip of a source driver for performing electrostatic discharge protection, the source driver for driving a display panel, the output circuit comprising:

an output buffer;

an output pad;

a switch coupled between the output buffer and the output pad, wherein a data voltage for driving the display panel is transmitted from the output buffer to the output pad through the switch, the switch comprises a first metal oxide semiconductor field effect transistor, the first metal oxide semiconductor field effect transistor comprises a first end, a base end and a grid end, and the first end is coupled to the output pad; and

the first resistor is coupled between the base terminal of the first metal-oxide-semiconductor field effect transistor and a first power supply terminal.

2. The output circuit of claim 1, further comprising:

the first pull-up circuit is coupled to the gate terminal of the first metal-oxide-semiconductor field effect transistor and a first system power supply terminal and is used for controlling a voltage level of the gate terminal of the first metal-oxide-semiconductor field effect transistor.

3. The output circuit of claim 1, further comprising a second resistor coupled between the output pad and the first end of the first mosfet.

4. The output circuit of claim 1, wherein the switch further comprises:

a second metal oxide semiconductor field effect transistor comprising a first end, a base end and a grid end, wherein the first end of the second metal oxide semiconductor field effect transistor is coupled with the output gasket; and

and the second resistor is coupled between the base terminal of the second metal-oxide-semiconductor field effect transistor and a second power supply terminal.

5. The output circuit of claim 4, wherein the first and second MOSFETs are a P-type and an N-type MOSFET in a transmission gate.

6. The output circuit of claim 4, further comprising:

a first pull-up circuit coupled to the gate terminal of the first MOSFET and a first system power supply terminal for controlling a voltage level of the gate terminal of the first MOSFET; and

the second pull-up circuit is coupled to the gate terminal of the second metal-oxide-semiconductor field effect transistor and a second system power supply terminal and is used for controlling a voltage level of the gate terminal of the second metal-oxide-semiconductor field effect transistor.

7. The output circuit of claim 4, wherein the first resistor is configured to limit a current flowing through a P-N junction between the first terminal of the first MOSFET and the base terminal of the first MOSFET under an ESD of a first polarity applied to the output pad, and the second resistor is configured to limit a current flowing through a P-N junction between the first terminal of the second MOSFET and the base terminal of the second MOSFET under an ESD of a second polarity applied to the output pad.

8. The output circuit of claim 5, further comprising a third resistor coupled between the output pad and a terminal of the transmission gate coupled to the first terminal of the first MOSFET and the first terminal of the second MOSFET.

9. The output circuit of claim 1, wherein the switch further comprises:

a second metal oxide semiconductor field effect transistor including a first terminal and a base terminal; and

and the second resistor is coupled between the first end of the second metal-oxide-semiconductor field effect transistor and the output gasket.

10. The output circuit of claim 9, wherein the first and second mosfets are a pmos and an nmos in a transmission gate.

11. The output circuit of claim 9, further comprising:

the second pull-up circuit is coupled to the gate terminal of the second metal-oxide-semiconductor field-effect transistor and a second system power supply terminal, and is used for controlling a voltage level of the gate terminal of the second metal-oxide-semiconductor field-effect transistor.

12. The output circuit of claim 9, wherein the first resistor is configured to limit a current flowing through a P-N junction between the first terminal of the first mosfet and the base terminal of the first mosfet under an esd of a first polarity applied to the output pad, and the second resistor is configured to limit a current flowing through a P-N junction between the first terminal of the second mosfet and the base terminal of the second mosfet under an esd of a second polarity applied to the output pad.

13. The output circuit of claim 1, wherein the output pad is coupled to an ESD protection unit.